TL F 9584
54F74F657
Octal
Bidirectional
Transceiver
with
8-Bit
Parity
GeneratorChecker
and
TRI-STATE
Outputs
December 1994
54F 74F657 Octal Bidirectional Transceiver
with 8-Bit Parity Generator Checker
and TRI-STATE
Outputs
General Description
The
'F657
contains
eight
non-inverting
buffers
with
TRI-STATE
outputs and an 8-bit parity generator checker
It is intended for bus-oriented applications The buffers have
a guaranteed current sinking capability of 24 mA (20 mA mil)
at the A port and 64 mA (48 mA mil) at the B port
Features
Y
300 Mil 24-pin slimline DIP
Y
Combines 'F245 and 'F280A functions in one package
Y
TRI-STATE outputs
Y
B Outputs sink 64 mA (48 mA mil)
Y
12 mA source current B side
Y
Input diodes for termination effects
Commercial
Military
Package
Package Description
Number
74F657SPC
N24C
24-Lead (0 300 Wide) Molded Dual-In-Line
54F657SDM (Note 2)
J24F
24-Lead (0 300 Wide) Ceramic Dual-In-Line
75F657SC (Note 1)
M24B
24-Lead (0 300 Wide) Molded Small Outline JEDEC
54F657FM (Note 2)
W24C
24-Lead Cerpack
54F657LM (Note 2)
E28A
24-Lead Ceramic Leadless Chip Carrier Type C
Note 1
Devices also available in 13
reel Use suffix
e
SCX
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Logic Symbols
IEEE IEC
TL F 9584 5
TL F 9584 1
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M75 Printed in U S A
Connection Diagrams
Pin Assignment
for DIP SOIC
and Flatpak
TL F 9584 2
Pin Assignment
for LCC
TL F 9584 3
Unit Loading Fan Out
54F 74F
Pin Names
Description
U L
Input I
IH
I
IL
HIGH LOW
Output I
OH
I
OL
A
0
A
7
Data Inputs
4 5 0 15
90 mA
b
90 mA
TRI-STATE Outputs
150 40 (33 3)
b
3 mA 24 mA (20 mA)
B
0
B
7
Data Inputs
3 5 0 117
70 mA
b
70 mA
TRI-STATE Outputs
600 106 6 (80)
b
12 mA 64 mA (48 mA)
T R
Transmit Receive Input
2 0 0 067
40 mA
b
40 mA
OE
Enable Input
2 0 0 067
40 mA
b
40 mA
PARITY
Parity Input
3 5 0 117
70 mA
b
70mA
TRI-STATE Output
600 106 6 (80)
b
12 mA 64 mA (48 mA)
ODD EVEN ODD EVEN Parity Input
1 0 0 033
20 mA
b
20 mA
ERROR
Error Output
600 106 6 (80)
b
12 mA 64 mA (48 mA)
Functional Description
The Transmit Receive (T R) input determines the direction
of the data flow through the bidirectional transceivers
Transmit (active HIGH) enables data from the A port to the
B port Receive (active LOW) enables data from the B port
to the A port
The Output Enable (OE) input disables the parity and
ERROR outputs and both the A and B ports by placing them
in a HIGH-Z condition when the Output Enable input is
HIGH
When transmitting (T R HIGH) the parity generator detects
whether an even or odd number of bits on the A port are
HIGH and compares these with the condition of the pari-
ty select (ODD EVEN) If the Parity Select is HIGH and an
even number of A inputs are HIGH the Parity output is
HIGH
In receiving mode (T R LOW) the parity select and number
of HIGH inputs on port B are compared to the condition of
the Parity input If an even number of bits on the B port are
HIGH the parity select is HIGH and the PARITY input is
HIGH then ERROR will be HIGH to indicate no error If an
odd number of bits on the B port are HIGH the parity select
is HIGH and the PARITY input is HIGH the ERROR will be
LOW indicating an error
2
Function Table
Number of
Inputs
Input
Outputs
Inputs That
Output
Are High
OE
T R
ODD EVEN
Parity
ERROR
Outputs Mode
0 2 4 6 8
L
H
H
H
Z
Transmit
L
H
L
L
Z
Transmit
L
L
H
H
H
Receive
L
L
H
L
L
Receive
L
L
L
H
L
Receive
L
L
L
L
H
Receive
1 3 5 7
L
H
H
L
Z
Transmit
L
H
L
H
Z
Transmit
L
L
H
H
L
Receive
L
L
H
L
H
Receive
L
L
L
H
H
Receive
L
L
L
L
L
Receive
Immaterial
H
X
X
Z
Z
Z
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Z
e
High Impedance
Function Table
Inputs
Outputs
OE
T R
L
L
Bus B Data to Bus A
L
H
Bus A Data to Bus B
H
X
High-Z State
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
3
Functional Block Diagram
TL F 9584 4
4
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
b
65 C to
a
150 C
Ambient Temperature under Bias
b
55 C to
a
125 C
Junction Temperature under Bias
b
55 C to
a
175 C
Plastic
b
55 C to
a
150 C
V
CC
Pin Potential to
Ground Pin
b
0 5V to
a
7 0V
Input Voltage (Note 2)
b
0 5V to
a
7 0V
Input Current (Note 2)
b
30 mA to
a
5 0 mA
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
b
0 5V to V
CC
TRI-STATE Output
b
0 5V to
a
5 5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
b
55 C to
a
125 C
Commercial
0 C to
a
70 C
Supply Voltage
Military
a
4 5V to
a
5 5V
Commercial
a
4 5V to
a
5 5V
DC Electrical Characteristics
Symbol
Parameter
54F 74F
Units
V
CC
Conditions
Min
Typ
Max
V
IH
Input HIGH Voltage
2 0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0 8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
b
1 2
V
Min
I
IN
e b
18 mA
V
OH
Output HIGH
54F 10%V
CC
2 5
I
OH
e b
1 mA (A
n
)
Voltage
54F 10% V
CC
2 4
I
OH
e b
3 mA (A
n
B
n
Parity ERROR)
54F 10% V
CC
2 0
I
OH
e b
12 mA (B
n
Parity ERROR)
74F 10% V
CC
2 5
V
Min
I
OH
e b
1 mA (A
n
)
74F 10% V
CC
2 4
I
OH
e b
3 mA (A
n
B
n
Parity ERROR)
74F 10% V
CC
2 0
I
OH
e b
15 mA (B
n
Parity ERROR)
74F 5% V
CC
2 7
I
OH
e b
1 mA (A
n
)
74F 5% V
CC
2 7
I
OH
e b
3 mA (A
n
B
n
Parity ERROR)
V
OL
Output LOW
54F 10% V
CC
0 5
I
OL
e
20 mA (A
n
)
Voltage
54F 10% V
CC
0 55
V
Min
I
OL
e
48 mA (B
n
Parity ERROR)
74F 10% V
CC
0 5
I
OL
e
24 mA (A
n
)
74F 10% V
CC
0 55
I
OL
e
64 mA (B
n
Parity ERROR)
I
IH
Input HIGH Current
20
m
A
Max
V
IN
e
2 7V (ODD EVEN)
40
V
IN
2 7V (T R OE)
I
BVI
Input HIGH Current
100
m
A
V
CC
e
0
V
IN
e
7 0V (T R OE ODD EVEN)
Breakdown Test
I
BVIT
Input HIGH Current
1 0
mA
Max
V
IN
e
5 5V (Parity B
n
)
Breakdown Test (I O)
2 0
V
IN
e
5 5V (A
n
)
I
IL
Input LOW Current
b
20
m
A
Max
V
IN
e
0 5V (ODD EVEN)
b
40
V
IN
e
0 5V (T R OE)
I
OZH
Output Leakage Current
50
m
A
Max
V
OUT
e
2 7V (ERROR)
I
OZL
Output Leakage Current
b
50
m
A
Max
V
OUT
e
0 5V (ERROR)
I
IH
a
I
OZH
Output Leakage Current
70
m
A
Max
V
I O
e
2 7V (B
n
Parity)
90
V
I O
e
2 7V (A
n
)
I
IL
a
I
OZL
Output Leakage Current
b
70
m
A
Max
V
I O
e
0 5V (B
n
Parity)
b
90
V
I O
e
0 5V (A
n
)
I
OS
Output Short-Circuit Current
b
60
b
150
mA
Max
V
OUT
e
0V (A
n
)
b
100
b
225
V
OUT
e
0V (B
n
Parity ERROR)
I
CEX
Output HIGH Leakage
250
m
A
Max
V
OUT
e
V
CC
(ERROR)
Current
1 0
mA
Max
V
OUT
e
V
CC
(B
n
Parity)
2 0
mA
Max
V
OUT
e
V
CC
(A
n
)
I
ZZ
Bus Drainage Test
500
m
A
0 0V
V
OUT
e
5 25V (A
n
B
n
Parity ERROR)
I
CCH
Power Supply Current
101
125
mA
Max
V
O
e
HIGH
I
CCL
Power Supply Current
112
150
mA
Max
V
O
e
LOW
I
CCZ
Power Supply Current
109
145
mA
Max
V
O
e
HIGH Z
5
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