TL F 9469
54F74F74
Dual
D-Type
Positive
Edge-Triggered
Flip-Flop
December 1994
54F 74F74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The 'F74 is a dual D-type flip-flop with Direct Clear and Set
inputs and complementary (Q Q) outputs Information at the
input is transferred to the outputs on the positive edge of
the clock pulse Clock triggering occurs at a voltage level of
the clock pulse and is not directly related to the transition
time of the positive-going pulse After the Clock Pulse input
threshold voltage has been passed the Data input is locked
out and information present will not be transferred to the
outputs until the next rising edge of the Clock Pulse input
Asynchronous Inputs
LOW input to S
D
sets Q to HIGH level
LOW input to C
D
sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q HIGH
Features
Y
Guaranteed 4000V minimum ESD protection
Commercial
Military
Package
Package Description
Number
74F74PC
N14A
14-Lead (0 300 Wide) Molded Dual-In-Line
54F74DM (Note 2)
J14A
14-Lead Ceramic Dual-In-Line
74F74SC (Note 1)
M14A
14-Lead (0 150 Wide) Molded Small Outline JEDEC
74F74SJ (Note 1)
M14D
14-Lead (0 300 Wide) Molded Small Outline EIAJ
54F74FM (Note 2)
W14B
14-Lead Cerpack
54F74LM (Note 2)
E20A
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1
Devices also available in 13
reel Use Suffix
e
SCX
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Logic Symbols
TL F 9469 3
TL F 9469 4
IEEE IEC
TL F 9469 6
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M75 Printed in U S A
Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
TL F 9469 1
Pin Assignment
for LCC
TL F 9469 2
Unit Loading Fan Out
54F 74F
Pin Names
Description
U L
Input I
IH
I
IL
HIGH LOW
Output I
OH
I
OL
D
1
D
2
Data Inputs
1 0 1 0
20 mA
b
0 6 mA
CP
1
CP
2
Clock Pulse Inputs (Active Rising Edge)
1 0 1 0
20 mA
b
0 6 mA
C
D1
C
D2
Direct Clear Inputs (Active LOW)
1 0 3 0
20 mA
b
1 8 mA
S
D1
S
D2
Direct Set Inputs (Active LOW)
1 0 3 0
20 mA
b
1 8 mA
Q
1
Q
1
Q
2
Q
2
Outputs
50 33 3
b
1 mA 20 mA
Truth Table
Inputs
Outputs
S
D
C
D
CP
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
L
h
H
L
H
H
L
l
L
H
H
H
L
X
Q
0
Q
0
H (h)
e
HIGH Voltage Level
L (l)
e
LOW Voltage Level
X
e
Immaterial
Q
0
e
Previous Q (Q) before LOW-to-HIGH Clock Transition
Lower case letters indicate the state of the referenced input or output one
setup time prior to the LOW-to-HIGH clock transition
Logic Diagram
TL F 9469 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
b
65 C to
a
150 C
Ambient Temperature under Bias
b
55 C to
a
125 C
Junction Temperature under Bias
b
55 C to
a
175 C
Plastic
b
55 C to
a
150 C
V
CC
Pin Potential to
Ground Pin
b
0 5V to
a
7 0V
Input Voltage (Note 2)
b
0 5V to
a
7 0V
Input Current (Note 2)
b
30 mA to
a
5 0 mA
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
b
0 5V to V
CC
TRI-STATE Output
b
0 5V to
a
5 5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min)
4000V
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
b
55 C to
a
125 C
Commercial
0 C to
a
70 C
Supply Voltage
Military
a
4 5V to
a
5 5V
Commercial
a
4 5V to
a
5 5V
DC Electrical Characteristics
Symbol
Parameter
54F 74F
Units
V
CC
Conditions
Min
Typ
Max
V
IH
Input HIGH Voltage
2 0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0 8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
b
1 2
V
Min
I
IN
e b
18 mA
V
OH
Output HIGH
54F 10% V
CC
2 5
I
OH
e b
1 mA
Voltage
74F 10% V
CC
2 5
V
Min
I
OH
e b
1 mA
74F 5% V
CC
2 7
I
OH
e b
1 mA
V
OL
Output LOW
54F 10% V
CC
0 5
V
Min
I
OL
e
20 mA
Voltage
74F 10% V
CC
0 5
I
OL
e
20 mA
I
IH
Input HIGH
54F
20 0
m
A
Max
V
IN
e
2 7V
Current
74F
5 0
I
BVI
Input HIGH Current
54F
100
m
A
Max
V
IN
e
7 0V
Breakdown Test
74F
7 0
I
CEX
Output HIGH
54F
250
m
A
Max
V
OUT
e
V
CC
Leakage Current
74F
50
V
ID
Input Leakage
74F
4 75
V
0 0
I
ID
e
1 9 mA
Test
All Other Pins Grounded
I
OD
Output Leakage
74F
3 75
m
A
0 0
V
IOD
e
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
b
0 6
mA
Max
V
IN
e
0 5V (D CP)
b
1 8
V
IN
e
0 5V (C
D
S
D
)
I
OS
Output Short-Circuit Current
b
60
b
150
mA
Max
V
OUT
e
0V
I
CC
Power Supply Current
10 5
16 0
mA
Max
3
AC Electrical Characteristics
74F
54F
74F
T
A
e a
25 C
T
A
V
CC
e
Mil
T
A
V
CC
e
Com
Symbol
Parameter
V
CC
e a
5 0V
C
L
e
50 pF
C
L
e
50 pF
Units
C
L
e
50 pF
Min
Typ
Max
Min
Max
Min
Max
f
max
Maximum Clock Frequency
100
125
80
100
MHz
t
PLH
Propagation Delay
3 8
5 3
6 8
3 8
8 5
3 8
7 8
ns
t
PHL
CP
n
to Q
n
or Q
n
4 4
6 2
8 0
4 4
10 5
4 4
9 2
t
PLH
Propagation Delay
3 2
4 6
6 1
3 2
8 0
3 2
7 1
ns
t
PHL
C
Dn
or S
Dn
to Q
n
or Q
n
3 5
7 0
9 0
3 5
11 5
3 5
10 5
AC Operating Requirements
74F
54F
74F
Symbol
Parameter
T
A
e a
25 C
T
A
V
CC
e
Mil
T
A
V
CC
e
Com
Units
V
CC
e a
5 0V
Min
Max
Min
Max
Min
Max
t
s
(H)
Setup Time HIGH or LOW
2 0
3 0
2 0
t
s
(L)
D
n
to CP
n
3 0
4 0
3 0
ns
t
h
(H)
Hold Time HIGH or LOW
1 0
2 0
1 0
t
h
(L)
D
n
to CP
n
1 0
2 0
1 0
t
w
(H)
CP
n
Pulse Width
4 0
4 0
4 0
ns
t
w
(L)
HIGH or LOW
5 0
6 0
5 0
t
w
(L)
C
Dn
or S
Dn
Pulse Width
4 0
4 0
4 0
ns
LOW
t
rec
Recovery Time
2 0
3 0
2 0
ns
C
Dn
or S
Dn
to CP
4
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows
74F
74
S
C
X
Temperature Range Family
Special Variations
74F
e
Commercial
QB
e
Military grade device with
54F
e
Military
environmental and burn-in
processing
Device Type
X
e
Devices shipped in 13 reel
Package Code
Temperature Range
P
e
Plastic DIP
C
e
Commercial (0 C to
a
70 C)
D
e
Ceramic DIP
M
e
Military (
b
55 C to
a
125 C)
F
e
Flatpak
L
e
Leadless Chip Carrier (LCC)
S
e
Small Outline SOIC JEDEC
SJ
e
Small Outline SOIC EIAJ
Physical Dimensions
inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
5
Physical Dimensions
inches (millimeters) (Continued)
14-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J14A
14-Lead (0 150 Wide) Molded Small Outline JEDEC (S)
NS Package Number M14A
6
Physical Dimensions
inches (millimeters) (Continued)
14-Lead (0 300 Wide) Molded Small Outline EIAJ (SJ)
NS Package Number M14D
14-Lead (0 300 Wide) Molded Dual-In-Line Package (P)
NS Package Number N14A
7
54F74F74
Dual
D-Type
Positive
Edge-Triggered
Flip-Flop
Physical Dimensions
inches (millimeters) (Continued)
14-Lead Ceramic Flatpak (F)
NS Package Number W14B
LIFE SUPPORT POLICY
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION As used herein
1 Life support devices or systems are devices or
2 A critical component is any component of a life
systems which (a) are intended for surgical implant
support device or system whose failure to perform can
into the body or (b) support or sustain life and whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system or to affect its safety or
with instructions for use provided in the labeling can
effectiveness
be reasonably expected to result in a significant injury
to the user
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