100355
Low Power Quad Multiplexer/Latch
General Description
The 100355 contains four transparent latches, each of which
can accept and store data from two sources. When both En-
able (E
n
) inputs are LOW, the data that appears at an output
is controlled by the Select (S
n
) inputs, as shown in the Oper-
ating Mode table. In addition to routing data from either D
0
or
D
1
, the Select inputs can force the outputs LOW for the case
where the latch is transparent (both Enables are LOW) and
can steer a HIGH signal from either D
0
or D
1
to an output.
The Select inputs can be tied together for applications re-
quiring only that data be steered from either D
0
or D
1
. A
positive-going signal on either Enable input latches the out-
puts. A HIGH signal on the Master Reset (MR) input over-
rides all the other inputs and forces the Q outputs LOW. All
inputs have 50 k
pulldown resistors.
Features
n
Greater than 40% power reduction of the 100155
n
2000V ESD protection
n
Pin/function compatible with 100155
n
Voltage compensated operating range = -4.2V to -5.7V
n
Standard Microcircuit Drawing
(SMD) 5962-9165401
Logic Symbol
Pin Names
Description
E
1
, E
2
Enable Inputs (Active LOW)
S
0
, S
1
Select Inputs
MR
Master Reset
D
na
D
nd
Data Inputs
Q
a
Q
d
Data Outputs
Q
a
Q
d
Complementary Data Outputs
Connection Diagrams
DS100294-1
24-Pin DIP
DS100294-2
24-Pin Quad Cerpak
DS100294-3
August 1998
100355
Low
Power
Quad
Multiplexer/Latch
1998 National Semiconductor Corporation
DS100294
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Logic Diagram
DS100294-5
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2
Operating Mode Table
Controls
Outputs
E
1
E
2
S
1
S
0
Q
n
H
X
X
X
Latched (Note 1)
X
H
X
X
Latched (Note 1)
L
L
L
L
D
0x
L
L
H
L
D
0x
+ D
1x
L
L
L
H
L
L
L
H
H
D
1x
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Note 1: Stores data present before E went HIGH
Truth Table
Inputs
Outputs
MR
E
1
E
2
S
1
S
0
D
1x
D
0x
Q
x
Q
x
H
X
X
X
X
X
X
H
L
L
L
L
H
H
H
X
L
H
L
L
L
H
H
L
X
H
L
L
L
L
L
L
X
H
L
H
L
L
L
L
L
X
L
H
L
L
L
L
L
H
X
X
H
L
L
L
L
H
L
H
X
L
H
L
L
L
H
L
X
H
L
H
L
L
L
H
L
L
L
H
L
L
H
X
X
X
X
X
Latched (Note 1)
L
X
H
X
X
X
X
Latched (Note 1)
3
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Absolute Maximum Ratings
(Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Above
which the useful life may be impaired.
Storage Temperature (T
STG
)
-65C to +150C
Maximum Junction Temperature (T
J
)
Ceramic
+175C
V
EE
Pin Potential to Ground Pin
-7.0V to +0.5V
Input Voltage (DC)
V
EE
to +0.5V
Output Current (DC Output HIGH)
-50 mA
ESD (Note 3)
2000V
Recommended Operating
Conditions
Case Temperature (T
C
)
Military
-55C to +125C
Supply Voltage (V
EE
)
-5.7V to -4.2V
Note 2: Absolute maximum ratings are those values beyond which the de-
vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version
DC Electrical Characteristics
V
EE
= -4.2V to -5.7V, V
CC
= V
CCA
= GND, T
C
= -55C to +125C
Symbol
Parameter
Min
Max
Units
T
C
Conditions
Notes
V
OH
Output HIGH Voltage
-1025
-870
mV
0C to +125C
-1085
-870
mV
-55C
V
IN
= V
IH (Max)
Loading with
(Notes 4, 5,
6)
V
OL
Output LOW Voltage
-1830
-1620
mV
0C to +125C
or V
IL (Min)
50
to -2.0V
-1830
-1555
mV
-55C
V
OHC
Output HIGH Voltage
-1035
mV
0C to +125C
-1085
mV
-55C
V
IN
= V
IH (Min)
Loading with
(Notes 4, 5,
6)
V
OLC
Output LOW Voltage
-1610
mV
0C to +125C
or V
IL (Max)
50
to -2.0V
-1555
mV
-55C
V
IH
Input HIGH Voltage
-1165
-870
mV
-55C to
Guaranteed HIGH Signal
(Notes 4, 5,
6, 7)
+125C
for ALL Inputs
V
IL
Input LOW Voltage
-1830
-1475
mV
-55C to
Guaranteed LOW Signal
(Notes 4, 5,
6, 7)
+125C
for ALL Inputs
I
IL
Input LOW Current
0.50
A
-55C to
V
EE
= -4.2V
(Notes 4, 5,
6)
+125C
V
IN
= V
IL (Min)
I
IH
Input HIGH Current
S
0
, S
1
220
E
1
, E
2
350
A
0C to +125C
D
na
D
nd
340
V
EE
= -5.7V
MR
430
V
IN
= V
IH (Max)
(Notes 4, 5,
6)
S
0
, S
1
320
E
1
, E
2
500
A
-55C
D
na
D
nd
490
MR
630
I
EE
Power Supply Current
-95
-32
mA
-55C to +125C
Inputs Open
(Notes 4, 5,
6)
Note 4: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides "cold start" specs which can be considered a worst case
condition at cold temperatures.
Note 5: Screen tested 100% on each device at -55C, +25C, and +125C Temp., Subgroups 1, 2, 3, 7, and 8.
Note 6: Sample tested (Method 5005, Table 1) on each Mfg. lot at +25, +125C, and -55C Temp., Subgroups 1, 2, 3, 7, and 8.
Note 7: Guaranteed by applying specified input condition and testing V
OH
/V
OL
.
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4
Military Version
AC Electrical Characteristics
V
EE
= -4.2V to -5.7V, V
CC
= V
CCA
= GND
Symbol
Parameter
T
C
= -55C
T
C
= +25C
T
C
= +125C
Units
Conditions
Notes
Min
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
t
PHL
D
na
D
nd
to Output
0.40
2.30
0.50
2.20
0.50
2.60
ns
(Transparent Mode)
t
PLH
Propagation Delay
Figures 1, 2
(Notes 8, 9,
10)
t
PHL
S
0
, S
1
to Output
0.60
3.00
0.80
2.70
0.80
3.20
ns
(Transparent Mode)
t
PLH
Propagation Delay
0.50
2.60
0.60
2.30
0.70
2.70
ns
t
PHL
E
1
, E
2
to Output
t
PLH
Propagation Delay
0.60
2.80
0.70
2.60
0.70
2.90
ns
Figures 1, 3
(Notes 8, 9,
10)
t
PHL
MR to Output
t
TLH
Transition Time
0.40
1.90
0.40
1.90
0.40
1.90
ns
Figures 1, 2
(Note 11)
t
THL
20% to 80%, 80% to 20%
t
S
Setup Time
D
na
D
nd
0.90
0.90
0.90
ns
Figure 4
(Note 11)
S
0
, S
1
2.40
2.40
2.40
MR (Release Time)
1.50
1.50
1.50
Figure 3
t
H
Hold Time
D
na
D
nd
0.40
0.40
0.40
ns
Figure 4
(Note 11)
S
0
, S
1
0.00
0.00
0.00
t
pw
(L)
Pulse Width LOW E
1
, E
2
2.00
2.00
2.00
ns
Figure 2
(Note 11)
t
pw
(H)
Pulse Width HIGH MR
2.00
2.00
2.00
ns
Figure 3
(Note 11)
Note 8: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides "cold start" specs which can be considered a worst case
condition at cold temperatures.
Note 9: Screen tested 100% on each device at +25C, Temperature only, Subgroup A9.
Note 10: Sample tested (Method 5005, Table 1) on each Mfg. lot at +25, Subgroup A9, and at +125C, and -55C Temp., Subgroups A10 & A11.
Note 11: Not tested at +25C, +125C and -55C Temperature (design characterization data).
5
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