TL F 9894
54ACT74ACT823
9-Bit
D
Flip-Flop
March 1993
54ACT 74ACT823
9-Bit D Flip-Flop
General Description
The 'ACT823 is a 9-bit buffered register It features Clock
Enable and Clear which are ideal for parity bus interfacing in
high
performance
microprogramming
systems
The
'ACT823 offers noninverting outputs and is fully compatible
with AMD's Am29823
Features
Y
Outputs source sink 24 mA
Y
TRI-STATE
outputs for bus interfacing
Y
Inputs and outputs are on opposite sides
Y
'ACT823 has TTL-compatible inputs
Logic Symbols
Connection Diagrams
TL F 9894 1
IEEE IEC
TL F 9894 2
Pin Assignment
for DIP Flatpak and SOIC
TL F 9894 3
Pin Assignment
for LCC
TL F 9894 4
Pin Names
Description
D
0
D
8
Data Inputs
O
0
O
8
Data Outputs
OE
Output Enable
CLR
Clear
CP
Clock Input
EN
Clock Enable
FACT
TM
is a trademark of National Semiconductor Corporation
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M75 Printed in U S A
Functional Description
The 'ACT823 consists of nine D-type edge-triggered flip-
flops These have TRI-STATE outputs for bus systems or-
ganized with inputs and outputs on opposite sides The buff-
ered clock (CP) and buffered Output Enable (OE) are com-
mon to all flip-flops The flip-flops will store the state of their
individual D inputs that meet the setup and hold time re-
quirements on the LOW-to-HIGH CP transition With OE
LOW the contents of the flip-flops are available at the out-
puts When OE is HIGH the outputs go to the high imped-
ance state Operation of the OE input does not affect
the state of the flip-flops In addition to the Clock and Output
Enable pins there are Clear (CLR) and Clock Enable (EN)
pins These devices are ideal for parity bus interfacing in
high performance systems
When CLR is LOW and OE is LOW the outputs are LOW
When CLR is HIGH data can be entered into the flip-flops
When EN is LOW data on the inputs is transferred to the
outputs on the LOW-to-HIGH clock transition When the EN
is HIGH the outputs do not change state regardless of the
data or clock input transitions
Function Table
Inputs
Internal
Output
Function
OE
CLR
EN
CP
D
Q
O
H
X
L
L
L
L
Z
High Z
H
X
L
L
H
H
Z
High Z
H
L
X
X
X
L
Z
Clear
L
L
X
X
X
L
L
Clear
H
H
H
X
X
NC
Z
Hold
L
H
H
X
X
NC
NC
Hold
H
H
L
L
L
L
Z
Load
H
H
L
L
H
H
Z
Load
L
H
L
L
L
L
L
Load
L
H
L
L
H
H
H
Load
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Z
e
High Impedance
L
e
LOW-to-HIGH Transition
NC
e
No Change
Logic Diagram
TL F 9894 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
CC
)
b
0 5V to 7 0V
DC Input Diode Current (I
IK
)
V
I
e b
0 5V
b
20 mA
V
I
e
V
CC
a
0 5V
a
20 mA
DC Input Voltage (V
I
)
b
0 5V to V
CC
a
0 5V
DC Output Diode Current (I
OK
)
V
O
e b
0 5V
b
20 mA
V
O
e
V
CC
a
0 5V
a
20 mA
DC Output Voltage (V
O
)
b
0 5V to V
CC
a
0 5V
DC Output Source or Sink Current (I
O
)
g
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
g
50 mA
Storage Temperature (T
STG
)
b
65 C to
a
150 C
Junction Temperature (T
J
)
CDIP
175 C
PDIP
140 C
Note 1
Absolute maximum ratings are those values beyond which damage
to the device may occur The databook specifications should be met without
exception to ensure that the system design is reliable over its power supply
temperature and output input loading variables National does not recom-
mend operation of FACT
TM
circuits outside databook specifications
Recommended Operating
Conditions
Supply Voltage (V
CC
)
'ACT
4 5V to 5 5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
74ACT
b
40 C to
a
85 C
54ACT
b
55 C to
a
125 C
Minimum Input Edge Rate (DV Dt)
'ACT Devices
V
IN
from 0 8V to 2 0V
V
CC
4 5V 5 5V
125 mV ns
DC Electrical Characteristics
74ACT
54ACT
74ACT
Symbol
Parameter
V
CC
T
A
e
25 C
T
A
e
T
A
e
Units
Conditions
(V)
b
55 C to
a
125 C
b
40 C to
a
85 C
Typ
Guaranteed Limits
V
IH
Minimum High Level
4 5
1 5
2 0
2 0
2 0
V
V
OUT
e
0 1V
Input Voltage
5 5
1 5
2 0
2 0
2 0
or V
CC
b
0 1V
V
IL
Maximum Low Level
4 5
1 5
0 8
0 8
0 8
V
V
OUT
e
0 1V
Input Voltage
4 5
1 5
0 8
0 8
0 8
or V
CC
b
0 1V
V
OH
Minimum High Level
4 5
4 49
4 4
4 4
4 4
V
I
OUT
e b
50 mA
5 49
5 4
5 4
5 4
V
IN
e
V
IL
or V
IH
4 5
3 86
3 70
3 76
V
I
OH
b
24 mA
4 86
4 70
4 76
b
24 mA
V
OL
Maximum Low Level
4 5
0 001
0 1
0 1
0 1
V
I
OUT
e
50 mA
Output Voltage
5 5
0 001
0 1
0 1
0 1
V
IN
e
V
IL
or V
IH
4 5
0 36
0 50
0 44
V
I
OL
24 mA
5 5
0 36
0 50
0 44
24 mA
I
IN
Maximum Input
5 5
g
0 1
g
1 0
g
1 0
m
A
V
I
e
V
CC
GND
Leakage Current
I
OZ
Maximum TRI-STATE Current
5 5
g
0 5
g
10 0
g
5 0
m
A
V
I
e
V
IL
V
IH
V
O
e
V
CC
GND
I
CCT
Maximum I
CC
Input
5 5
0 6
1 6
1 5
mA
V
I
e
V
CC
b
2 1V
I
OLD
Minimum Dynamic
5 5
50
75
mA
V
OLD
e
1 65V Max
I
OHD
Output Current
5 5
b
50
b
75
mA
V
OHD
e
3 85V Min
I
CC
Maximum Quiescent
5 5
8 0
160
80
m
A
V
IN
e
V
CC
Supply Current
or GND
All outputs loaded thresholds on input associated with output under test
Maximum test duration 2 0 ms one output loaded at a time
Note
I
CC
limit for 54ACT
25 C is identical to 74ACT
25 C
3
AC Electrical Characteristics
74ACT
54ACT
74ACT
T
A
e a
25 C
T
A
e b
55 C
T
A
e b
40 C
Symbol
Parameter
V
CC
C
L
e
50pF
to
a
125 C
to
a
85 C
Units
(V)
C
L
e
50 pF
C
L
e
50 pF
Min
Typ
Max
Min
Max
Min
Max
f
max
Maximum Clock
5 0
120
158
95
109
MHz
Frequency
t
PLH
Propagation Delay
5 0
1 5
5 5
9 5
1 5
12 0
1 5
10 5
ns
CP to O
n
t
PHL
Propagation Delay
5 0
2 0
5 5
9 5
1 5
12 0
1 5
10 5
ns
CP to O
n
t
PHL
Propagation Delay
5 0
2 5
8 0
13 5
1 5
18 0
2 0
15 5
ns
CLR to O
n
t
PZH
Output Enable Time
5 0
1 5
6 0
10 5
1 5
11 5
1 5
11 5
ns
OE to O
n
t
PZL
Output Enable Time
5 0
2 0
6 5
11 0
1 5
12 0
1 5
12 0
ns
OE to O
n
t
PHZ
Output Disable Time
5 0
1 5
6 5
11 0
1 5
13 5
1 5
12 0
ns
OE to O
n
t
PLZ
Output Disable Time
5 0
1 5
6 0
10 5
1 5
12 0
1 5
11 5
ns
OE to O
n
Voltage Range 5 0 is 5 0V
g
0 5V
AC Operating Requirements
74ACT
54ACT
74ACT
T
A
e a
25 C
T
A
e b
55 C
T
A
e b
40 C
Symbol
Parameter
V
CC
C
L
e
50 pF
to
a
125 C
to
a
85 C
Units
(V)
C
L
e
50 pF
C
L
e
50 pF
Typ
Guaranteed Minimum
t
s
Setup Time HIGH or LOW
5 0
0 5
2 5
4 0
2 5
ns
D to CP
t
h
Hold Time HIGH or LOW
5 0
0
2 5
3 0
2 5
ns
D
n
to CP
t
s
Setup Time HIGH or LOW
5 0
0
2 0
4 0
2 5
ns
EN to CP
t
h
Hold Time HIGH or LOW
5 0
0
1 0
3 0
1 0
ns
EN to CP
t
w
CP Pulse Width
5 0
2 5
4 5
6 0
5 5
ns
HIGH or LOW
t
w
CLR Pulse Width LOW
5 0
3 0
5 5
7 0
5 5
ns
t
rec
CLR to CP
5 0
1 5
3 5
4 5
4 0
ns
Recovery Time
Voltage Range 5 0 is 5 0V
g
0 5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4 5
pF
V
CC
e
OPEN
C
PD
Power Dissipation
44
pF
V
CC
e
5 0V
Capacitance
4
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows
74ACT
823
P
C
QR
Temperature Range Family
Special Variations
74ACT
e
Commercial TTL-Compatible
X
e
Devices shipped in 13 reels
54ACT
e
Military TTL-Compatible
QR
e
Commercial grade device with
burn-in
Device Type
QB
e
Military grade device with
environmental and burn-in
Package Code
processing shipped in tubes
SP
e
Slim Plastic DIP
SD
e
Slim Ceramic DIP
Temperature Range
F
e
Flatpak
C
e
Commercial (
b
40 C to
a
85 C)
L
e
Leadless Ceramic Chip Carrier (LCC)
M
e
Military (
b
55 C to
a
125 C)
S
e
Small Outline (SOIC)
Physical Dimensions
inches (millimeters)
28 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E28A
5
Physical Dimensions
inches (millimeters) (Continued)
24 Lead Slim (0 300 Wide) Ceramic Dual-In-Line (SD)
NS Package Number J24F
24 Lead Small Outline Integrated Circuit (S)
NS Package Number M24B
6
Physical Dimensions
inches (millimeters) (Continued)
24 Lead Slim (0 300 Wide) Plastic Dual-In-Line (SP)
NS Package Number N24C
7
54ACT74ACT823
9-Bit
D
Flip-Flop
Physical Dimensions
inches (millimeters) (Continued)
Lit
114635
24 Lead Ceramic Flatpak (F)
NS Package Number W24C
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION As used herein
1 Life support devices or systems are devices or
2 A critical component is any component of a life
systems which (a) are intended for surgical implant
support device or system whose failure to perform can
into the body or (b) support or sustain life and whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system or to affect its safety or
with instructions for use provided in the labeling can
effectiveness
be reasonably expected to result in a significant injury
to the user
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