TL F 9800
74AC843
74ACT843
9-Bit
Transparent
Latch
April 1993
74AC843
74ACT843
9-Bit Transparent Latch
General Description
The 'AC 'ACT843 bus interface latch is designed to elimi-
nate the extra packages required to buffer existing latches
and provide extra data width for wider address data paths
The 'AC 'ACT843 is functionally and pin compatible with
AMD's Am29843
Features
Y
'ACT843 has TTL-compatible inputs
Y
TRI-STATE
outputs for bus interfacing
Logic Symbols
Connection Diagram
TL F 9800 1
IEEE IEC
TL F 9800 3
Pin Names
Description
D
0
D
8
Data Inputs
O
0
O
8
Data Outputs
OE
Output Enable
LE
Latch Enable
CLR
Clear
PRE
Preset
Pin Assignment
for DIP and SOIC
TL F 9800 2
TRI-STATE
is a registered trademark of National Semiconductor Corporation
FACT
TM
is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M75 Printed in U S A
Functional Description
The 'AC 'ACT843 consists of nine D-type latches with
TRI-STATE outputs The flip-flops appear transparent to the
data when Latch Enable (LE) is HIGH This allows asyn-
chronous operation as the output transition follows the data
in transition On the LE HIGH-to-LOW transition the data
that meets the setup times is latched Data appears on the
bus when the Output Enable (OE) is LOW When OE is
HIGH the bus output is in the high impedance state In
addition to the LE and OE pins the 'AC 'ACT843 has a
Clear (CLR) pin and a Preset (PRE) pin These pins are ideal
for parity bus interfacing in high performance systems
When CLR is LOW the outputs are LOW if OE is LOW
When CLR is HIGH data can be entered into the latch
When PRE is LOW the outputs are HIGH if OE is LOW
Preset overrides CLR
Function Tables
Inputs
Internal
Outputs
Function
CLR
PRE
OE
LE
D
Q
O
H
H
H
H
L
L
Z
High Z
H
H
H
H
H
H
Z
High Z
H
H
H
L
X
NC
Z
Latched
H
H
L
H
L
L
L
Transparent
H
H
L
H
H
H
H
Transparent
H
H
L
L
X
NC
NC
Latched
H
L
L
X
X
H
H
Preset
L
H
L
X
X
L
L
Clear
L
L
L
X
X
H
H
Preset
L
H
H
L
X
L
Z
Clear High Z
H
L
H
L
X
H
Z
Preset High Z
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Z
e
High Impedance
NC
e
No Change
Logic Diagram
TL F 9800 5
2
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
CC
)
b
0 5V to
a
7 0V
DC Input Diode Current (I
IK
)
V
I
e b
0 5V
b
20 mA
V
I
e
V
CC
a
0 5V
a
20 mA
DC Input Voltage (V
I
)
b
0 5V to V
CC
a
0 5V
DC Output Diode Current (I
OK
)
V
O
e b
0 5V
b
20 mA
V
O
e
V
CC
a
0 5V
a
20 mA
DC Output Voltage (V
O
)
b
0 5V to V
CC
a
0 5V
DC Output Source
or Sink Current (I
O
)
g
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
g
50 mA
Storage Temperature (T
STG
)
b
65 C to
a
150 C
Junction Temperature (T
J
)
PDIP
140 C
Note 1
Absolute maximum ratings are those values beyond which damage
to the device may occur The databook specifications should be met without
exception to ensure that the system design is reliable over its power supply
temperature and output input loading variables National does not recom-
mend operation of FACT
TM
circuits outside databook specifications
Recommended Operating
Conditions
Supply Voltage (V
CC
)
'AC
2 0V to 6 0V
'ACT
4 5V to 5 5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
74AC ACT
b
40 C to
a
85 C
Minimum Input Edge Rate (DV Dt)
'AC Devices
V
IN
from 30% to 70% of V
CC
V
CC
3 3V 4 5V 5 5V
125 mV ns
Minimum Input Edge Rate (DV Dt)
'ACT Devices
V
IN
from 0 8V to 2 0V
V
CC
4 5V 5 5V
125 mV ns
DC Electrical Characteristics for 'AC Family Devices
74AC
74AC
Symbol
Parameter
V
CC
T
A
e a
25 C
T
A
e
Units
Conditions
(V)
b
40 C to
a
85 C
Typ
Guaranteed Limits
V
IH
Minimum High Level
3 0
1 5
2 1
2 1
V
OUT
e
0 1V
Input Voltage
4 5
2 25
3 15
3 15
V
or V
CC
b
0 1V
5 5
2 75
3 85
3 85
V
IL
Maximum Low Level
3 0
1 5
0 9
0 9
V
OUT
e
0 1V
Input Voltage
4 5
2 25
1 35
1 35
V
or V
CC
b
0 1V
5 5
2 75
1 65
1 65
V
OH
Minimum High Level
3 0
2 99
2 9
2 9
I
OUT
e b
50 mA
Output Voltage
4 5
4 49
4 4
4 4
V
5 5
5 49
5 4
5 4
V
IN
e
V
IL
or V
IH
3 0
2 56
2 46
b
12 mA
4 5
3 86
3 76
V
I
OH
b
24 mA
5 5
4 86
4 76
b
24 mA
V
OL
Maximum Low Level
3 0
0 002
0 1
0 1
I
OUT
e
50 mA
Output Voltage
4 5
0 001
0 1
0 1
V
5 5
0 001
0 1
0 1
V
IN
e
V
IL
or V
IH
3 0
0 36
0 44
12 mA
4 5
0 36
0 44
V
I
OL
24 mA
5 5
0 36
0 44
24 mA
I
IN
Maximum Input
5 5
g
0 1
g
1 0
m
A
V
I
e
V
CC
GND
Leakage Current
All outputs loaded thresholds on input associated with output under test
3
DC Electrical Characteristics for 'AC Family Devices
(Continued)
74AC
74AC
Symbol
Parameter
V
CC
T
A
e a
25 C
T
A
e
Units
Conditions
(V)
b
40 C to
a
85 C
Typ
Guaranteed Limits
I
OZ
Maximum TRI-STATE
V
I
(OE)
e
V
IL
V
IH
Leakage Current
5 5
g
0 5
g
5 0
m
A
V
I
e
V
CC
GND
V
O
e
V
CC
GND
I
OLD
Minimum Dynamic
5 5
75
mA
V
OLD
e
1 65V Max
I
OHD
Output Current
5 5
b
75
mA
V
OHD
e
3 85V Min
I
CC
Maximum Quiescent
5 5
8 0
80 0
m
A
V
IN
e
V
CC
Supply Current
or GND
Maximum test duration 2 0 ms one output loaded at a time
Note
I
IN
and I
CC
3 0V are guaranteed to be less than or equal to the respective limit
5 5V V
CC
DC Electrical Characteristics for 'ACT Family Devices
74ACT
74ACT
Symbol
Parameter
V
CC
T
A
e a
25 C
T
A
e
Units
Conditions
(V)
b
40 C to
a
85 C
Typ
Guaranteed Limits
V
IH
Minimum High Level
4 5
1 5
2 0
2 0
V
V
OUT
e
0 1V
Input Voltage
5 5
1 5
2 0
2 0
or V
CC
b
0 1V
V
IL
Maximum Low Level
4 5
1 5
0 8
0 8
V
V
OUT
e
0 1V
Input Voltage
5 5
1 5
0 8
0 8
or V
CC
b
0 1V
V
OH
Minimum High Level
4 5
4 49
4 4
4 4
V
I
OUT
e b
50 mA
Output Voltage
5 5
5 49
5 4
5 4
V
IN
e
V
IL
or V
IH
4 5
3 86
3 76
V
I
OH
b
24 mA
5 5
4 86
4 76
b
24 mA
V
OL
Maximum Low Level
4 5
0 001
0 1
0 1
V
I
OUT
e
50 mA
Output Voltage
5 5
0 001
0 1
0 1
V
IN
e
V
IL
or V
IH
4 5
0 36
0 44
V
I
OL
24 mA
5 5
0 36
0 44
24 mA
I
IN
Maximum Input
5 5
g
0 1
g
1 0
m
A
V
I
e
V
CC
GND
Leakage Current
I
OZ
Maximum TRI-STATE
5 5
g
0 5
g
5 0
m
A
V
I
e
V
IL
V
IH
Leakage Current
V
O
e
V
CC
GND
I
CCT
Maximum
5 5
0 6
1 5
mA
V
I
e
V
CC
b
2 1V
I
CC
Input
I
OLD
Minimum Dynamic
5 5
75
mA
V
OLD
e
1 65V Max
I
OHD
Output Current
5 5
b
75
mA
V
OHD
e
3 85V Min
I
CC
Maximum Quiescent
5 5
8 0
80 0
m
A
V
IN
e
V
CC
Supply Current
or GND
All outputs loaded thresholds on input associated with output under test
Maximum test duration 2 0 ms one output loaded at a time
4
AC Electrical Characteristics
74AC
74AC
V
CC
T
A
e a
25 C
T
A
e b
40 C
Symbol
Parameter
(V)
C
L
e
50 pF
to
a
85 C
Units
C
L
e
50 pF
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
3 3
3 5
6 5
12 0
2 5
13 0
ns
D
n
to O
n
5 0
2 0
4 5
8 5
1 5
9 0
t
PHL
Propagation Delay
3 3
4 0
7 0
12 0
3 0
13 0
ns
D
n
to O
n
5 0
2 5
5 0
8 5
1 5
9 0
t
PLH
Propagation Delay
3 3
3 5
6 5
12 0
13 0
2 5
ns
LE to O
n
5 0
2 0
4 5
8 5
1 5
9 0
t
PHL
Propagation Delay
3 3
4 0
7 0
12 0
3 0
13 0
ns
LE to O
n
5 0
2 5
5 0
8 5
1 5
9 0
t
PLH
Propagation Delay
3 3
5 5
8 5
19 0
4 5
21 5
ns
PRE to O
n
5 0
3 5
6 0
13 0
2 5
14 5
t
PHL
Propagation Delay
3 3
7 5
11 0
21 5
6 0
24 0
ns
CLR to O
n
5 0
5 0
7 5
15 0
4 0
17 0
t
PZH
Output Enable Time
3 3
3 5
6 0
11 0
3 0
12 0
ns
OE to O
n
5 0
2 0
4 5
8 0
1 5
9 0
t
PZL
Output Enable Time
3 3
4 0
6 5
11 0
2 5
12 0
ns
OE to O
n
5 0
2 0
5 0
8 0
1 5
9 0
t
PHZ
Output Disable Time
3 3
4 0
6 5
10 5
3 5
11 0
ns
OE to O
n
5 0
3 0
5 0
8 0
2 5
8 5
t
PLZ
Output Disable Time
3 3
3 0
6 0
10 5
2 5
11 0
ns
OE to O
n
5 0
2 0
4 5
8 0
1 5
8 5
t
PHL
Propagation Delay
3 3
4 5
7 0
12 5
3 5
13 5
ns
PRE to O
n
5 0
3 0
5 0
9 0
2 0
9 5
t
PLH
Propagation Delay
3 3
4 5
7 0
12 5
3 5
13 5
ns
CLR to O
n
5 0
3 0
5 0
9 0
2 0
9 5
Voltage Range 3 3 is 3 3V
g
0 3V
Voltage Range 5 0 is 5 0V
g
0 5V
5
AC Operating Requirements
Symbol
Parameter
V
CC
(V)
74AC
74AC
Units
T
A
e a
25 C
T
A
e b
40 C
C
L
e
50 pF
to
a
85 C
C
L
e
50 pF
Typ
Guaranteed Minimum
t
s
Setup Time HIGH or LOW
3 3
0
3 0
3 5
ns
D
n
to LE
5 0
b
0 5
1 5
2 0
t
h
Hold Time HIGH or LOW
3 3
2 0
2 0
ns
D
n
to LE
5 0
b
0 5
2 5
2 5
t
w
LE Pulse Width HIGH
3 3
1 5
3 0
3 0
ns
5 0
1 5
3 0
3 0
t
w
PRE Pulse Width LOW
3 3
5 0
12 0
14 5
ns
5 0
3 0
8 5
10 0
t
w
CLR Pulse Width LOW
3 3
5 5
14 0
16 5
ns
5 0
4 0
10 0
12 0
t
rec
PRE Recovery Time
3 3
1 0
3 0
3 0
ns
5 0
0
1 5
1 5
t
rec
CLR Recovery Time
3 3
0
1 5
1 5
ns
5 0
b
0 5
0 5
0 5
Voltage Range 3 3 is 3 3V
g
0 3V
Voltage Range 5 0 is 5 0V
g
0 5V
6
AC Electrical Characteristics
74ACT
74ACT
V
CC
T
A
e a
25 C
T
A
e b
40 C
Symbol
Parameter
(V)
C
L
e
50 pF
to
a
85 C
Units
C
L
e
50 pF
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
5 0
2 5
5 5
9 5
2 0
10 0
ns
D
n
to O
n
t
PHL
Propagation Delay
5 0
2 5
5 5
9 5
2 0
10 0
ns
D
n
to O
n
t
PLH
Propagation Delay
5 0
2 5
5 5
9 0
2 0
10 0
ns
LE to O
n
t
PHL
Propagation Delay
5 0
2 5
5 5
9 0
2 0
10 0
ns
LE to O
n
t
PLH
Propagation Delay
5 0
2 5
6 5
14 0
2 0
16 0
ns
PRE to O
n
t
PHL
Propagation Delay
5 0
2 5
7 5
15 5
2 0
17 5
ns
CLR to O
n
t
PZH
Output Enable Time
5 0
2 5
5 5
9 5
2 0
10 5
ns
OE to O
n
t
PZL
Output Enable Time
5 0
2 5
5 5
9 5
2 0
10 5
ns
OE to O
n
t
PHZ
Output Disable Time
5 0
2 5
6 0
10 5
2 0
11 0
ns
OE to O
n
t
PLZ
Output Disable Time
5 0
2 5
6 0
10 5
2 0
11 0
ns
OE to O
n
t
PHL
Propagation Delay
5 0
2 5
6 0
10 5
2 0
11 0
ns
PRE to O
n
t
PLH
Propagation Delay
5 0
2 5
5 5
9 5
2 0
10 5
ns
CLR to O
n
Voltage Range 5 0 is 5 0V
g
0 5V
AC Operating Requirements
Symbol
Parameter
V
CC
(V)
74AC
74AC
Units
T
A
e a
25 C
T
A
e b
40 C
C
L
e
50 pF
to
a
85 C
C
L
e
50 pF
Typ
Guaranteed Minimum
t
s
Setup Time HIGH or LOW
5 0
b
0 5
0 5
1 0
ns
D
n
to LE
t
h
Hold Time HIGH or LOW
5 0
0 5
2 0
2 0
ns
D
n
to LE
t
w
LE Pulse Width HIGH
5 0
2 0
3 5
3 5
ns
t
w
PRE Pulse Width LOW
5 0
5 0
8 5
10 0
ns
t
w
CLR Pulse Width LOW
5 0
5 5
9 5
11 0
ns
t
rec
PRE Recovery Time
5 0
0 5
2 0
2 0
ns
t
rec
CLR Recovery Time
5 0
b
0 5
1 0
1 0
ns
Voltage Range 5 0 is 5 0V
g
0 5V
7
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4 5
pF
V
CC
e
OPEN
C
PD
Power Dissipation Capacitance
44
pF
V
CC
e
5 0V
Ordering Information
The device number is used to form part of a simplified purchasing code where a package type and temperature range are
defined as follows
74AC
843
P
C
QR
Temperature Range Family
Special Variations
74AC
e
Commercial
X
e
Devices shipped in
74ACT
e
Commercial TTL-Compatible
13 reels
QR
e
Commercial grade device
Device Type
with burn-in
Package Code
Temperature Range
SP
e
Slim Plastic DIP
C
e
Commercial (
b
40 C to
a
85 C)
S
e
Small Outline (SOIC)
8
Physical Dimensions
inches (millimeters)
24-Lead Small Outline Integrated Circuit (S)
NS Package Number M24B
9
74AC843
74ACT843
9-Bit
Transparent
Latch
Physical Dimensions
inches (millimeters) (Continued)
Lit
114638
24-Lead Slim (0 300 Wide) Plastic Dual-In-Line Package (SP)
NS Package Number N24C
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION As used herein
1 Life support devices or systems are devices or
2 A critical component is any component of a life
systems which (a) are intended for surgical implant
support device or system whose failure to perform can
into the body or (b) support or sustain life and whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system or to affect its safety or
with instructions for use provided in the labeling can
effectiveness
be reasonably expected to result in a significant injury
to the user
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