TL F 10637
74AC899
54ACT74ACT899
9-Bit
Latchable
Transceiver
with
Parity
GeneratorChecker
August 1994
74AC899
54ACT 74ACT899
9-Bit Latchable Transceiver
with Parity Generator Checker
General Description
The 'AC 'ACT899 is a 9-bit to 9-bit parity transceiver with
transparent latches The device can operate as a feed-
through transceiver or it can generate check parity from the
8-bit data busses in either direction The 'AC 'ACT899 fea-
tures independent latch enables for the A-to-B direction and
the B-to-A direction a select pin for ODD EVEN parity and
separate error signal output pins for checking parity
Features
Y
Latchable transceiver with output sink of 24 mA
Y
Option to select generate parity and check or ``feed-
through'' data parity in directions A-to-B or B-to-A
Y
Independent latch enable for A-to-B and B-to-A direc-
tions
Y
Select pin for ODD EVEN parity
Y
ERRA and ERRB output pins for parity checking
Y
Ability to simultaneously generate and check parity
Y
May be used in system applications in place of the '280
Y
May be used in system applications in place of the '657
and '373 (no need to change T R to check parity)
Y
4 kV minimum ESD immunity
Logic Symbol
TL F 10637 1
Connection Diagram
Pin Assignment for PCC and LCC
TL F 10637 2
TRI-STATE
is a registered trademark of National Semiconductor Corporation
FACT
TM
is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M75 Printed in U S A
Pin Names
Description
A
0
A
7
A Bus Data Inputs Data Outputs
B
0
B
7
B Bus Data Inputs Data Outputs
APAR BPAR
A and B Bus Parity Inputs
ODD EVEN
ODD EVEN Parity Select Active
LOW for EVEN Parity
GBA GAB
Output Enables for A or B Bus
Active LOW
SEL
Select Pin for Feed-Through or
Generate Mode LOW for Generate
Mode
LEA LEB
Latch Enables for A and B Latches
HIGH for Transparent Mode
ERRA ERRB
Error Signals for Checking
Generated Parity with Parity In
LOW if Error Occurs
Functional Description
The 'AC 'ACT899 has three principal modes of operation
which are outlined below These modes apply to both the A-
to-B and B-to-A directions
Bus A (B) communicates to Bus B (A) parity is generat-
ed and passed on to the B (A) Bus as BPAR (APAR) If
LEB (LEA) is HIGH and the Mode Select (SEL) is LOW
the parity generated from B 0 7
(A 0 7 ) can be
checked and monitored by ERRB (ERRA)
Bus A (B) communicates to Bus B (A) in a feed-through
mode if SEL is HIGH Parity is still generated and
checked as ERRA and ERRB in the feed-through mode
(can be used as an interrupt to signal a data parity bit
error to the CPU)
Independent Latch Enables (LEA and LEB) allow other
permutations of generating checking (see Function Ta-
ble below)
Function Table
Inputs
Operation
GAB
GBA
SEL
LEA
LEB
H
H
X
X
X
Busses A and B are TRI-STATE
H
L
L
L
H
Generates parity from B 0 7 based on O E (Note 1) Generated parity
x
APAR Generated parity checked against BPAR and output as
ERRB
H
L
L
H
H
Generates parity from B 0 7 based on O E Generated parity
x
APAR Generated parity checked against BPAR and output as ERRB
Generated parity also fed back through the A latch for generate check
as ERRA
H
L
L
X
L
Generates parity from B latch data based on O E Generated parity
x
APAR Generated parity checked against latched BPAR and
output as ERRB
H
L
H
X
H
BPAR B 0 7
x
APAR A0 7 Feed-through mode Generated parity
checked against BPAR and output as ERRB
H
L
H
H
H
BPAR B 0 7
x
APAR A 0 7
Feed-through mode Generated parity checked against BPAR and
output as ERRB Generated parity also fed back through the A latch for
generate check as ERRA
L
H
L
H
L
Generates parity for A 0 7 based on O E Generated parity
x
BPAR Generated parity checked against APAR and output as ERRA
L
H
L
H
H
Generates parity from A 0 7 based on O E Generated parity
x
BPAR Generated parity checked against APAR and output as ERRA
Generated parity also fed back through the B latch for generate check
as ERRB
L
H
L
L
X
Generates parity from A latch data based on O E Generated parity
x
BPAR Generated parity checked against latched APAR and
output as ERRA
L
H
H
H
L
APAR A 0 7
x
BPAR B 0 7
Feed-through mode Generated parity checked against APAR and
output as ERRA
L
H
H
H
H
APAR A 0 7
x
BPAR B 0 7
Feed-through mode Generated parity checked against APAR and
output as ERRA Generated parity also fed back through the B latch for
generate check as ERRB
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Note 1
O E
e
ODD EVEN
2
Functional Block Diagram
TL F 10637 3
AC Path
TL F 10637 4
A
n
APAR
x
B
n
BPAR
(B
n
BPAR
x
A
n
APAR)
FIGURE 1
3
AC Path
(Continued)
A
n
x
BPAR
(B
n
x
APAR)
TL F 10637 5
FIGURE 2
A
n
x
ERRA
(B
n
x
ERRB)
TL F 10637 6
FIGURE 3
O E
x
ERRA
O E
x
ERRB
TL F 10637 7
FIGURE 4
4
AC Path
(Continued)
O E
x
BPAR
(O E
x
APAR)
TL F 10637 8
FIGURE 5
APAR
x
ERRA
(BPAR
x
ERRB)
TL F 10637 9
FIGURE 6
TL F 10637 10
ZH HZ
FIGURE 7
5
AC Path
(Continued)
TL F 10637 11
ZL LZ
FIGURE 8
TL F 10637 12
SEL
x
BPAR
(SEL
x
APAR)
FIGURE 9
TL F 10637 13
LEA
x
BPAR B 0 7
(LEB
x
APAR A 0 7 )
FIGURE 10
6
AC Path
(Continued)
TS(H) TH(H)
TL F 10637 14
LEA
x
APAR A 0 7
(LEB
x
BPAR B 0 7 )
FIGURE 11
TS(L) TH(L)
TL F 10637 15
LEA
x
APAR A 0 7
(LEB
x
BPAR B 0 7 )
FIGURE 12
TL F 10637 16
FIGURE 13
7
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
CC
)
b
0 5V to
a
7 0V
DC Input Diode Current (I
IK
)
V
I
e b
0 5V
b
20 mA
V
I
e
V
CC
a
0 5V
a
20 mA
DC Input Voltage (V
I
)
b
0 5V to V
CC
a
0 5V
DC Output Diode Current (I
OK
)
V
O
e b
0 5V
b
20 mA
V
O
e
V
CC
a
0 5V
a
20 mA
DC Output Voltage (V
O
)
b
0 5V to V
CC
a
0 5V
DC Output Source
or Sink Current (I
O
)
g
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
g
50 mA
Storage Temperature (T
STG
)
b
65 C to
a
150 C
DC Latch-Up Source or
Sink Current
g
300 mA
Junction Temperature (T
J
)
CDIP
175 C
PDIP
140 C
Note 1
Absolute maximum ratings are those values beyond which damage
to the device may occur The databook specifications should be met without
exception to ensure that the system design is reliable over its power supply
temperature and output input loading variables National does not recom-
mend operation of FACT
TM
circuits outside databook specifications
Recommended Operating
Conditions
Supply Voltage (V
CC
)
'AC
2 0V to 6 0V
'ACT
4 5V to 5 5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
74AC ACT
b
40 C to
a
85 C
54ACT
b
55 C to
a
125 C
Minimum Input Edge Rate DV Dt
'AC Devices
V
IN
from 30% to 70% of V
CC
V
CC
3 0V 4 5V 5 5V
125 mV ns
Minimum Input Edge Rate DV Dt
'ACT Devices
V
IN
from 0 8V to 2 0V
V
CC
4 5V 5 5V
125 mV ns
Note
PLCC packaging is not recommended for applications requiring great-
er than 2000 temperature cycles from
b
40 C to
a
125 C
DC Electrical Characteristics for 'AC Family Devices
74AC
74AC
Symbol
Parameter
V
CC
T
A
e a
25 C
T
A
e
Units
Conditions
(V)
b
40 C to
a
85 C
Typ
Guaranteed Limits
V
IH
Minimum High Level
3 0
1 5
2 1
2 1
V
OUT
e
0 1V
Input Voltage
4 5
2 25
3 15
3 15
V
or V
CC
b
0 1V
5 5
2 75
3 85
3 85
V
IL
Maximum Low Level
3 0
1 5
0 9
0 9
V
OUT
e
0 1V
Input Voltage
4 5
2 25
1 35
1 35
V
or V
CC
b
0 1V
5 5
2 75
1 65
1 65
V
OH
Minimum High Level
3 0
2 99
2 9
2 9
I
OUT
e b
50 mA
Output Voltage
4 5
4 49
4 4
4 4
V
5 5
5 49
5 4
5 4
V
IN
e
V
IL
or V
IH
3 0
2 56
2 46
V
b
12 mA
4 5
3 86
3 76
I
OH
b
24 mA
5 5
4 86
4 76
b
24 mA
V
OL
Maximum Low Level
3 0
0 002
0 1
0 1
I
OUT
e
50 mA
Output Voltage
4 5
0 001
0 1
0 1
V
5 5
0 001
0 1
0 1
V
IN
e
V
IL
or V
IH
3 0
0 36
0 44
12 mA
4 5
0 36
0 44
V
I
OL
24 mA
5 5
0 36
0 44
24 mA
I
IN
Maximum Input
5 5
g
0 1
g
1 0
m
A
V
I
e
V
CC
GND
Leakage Current
(Note)
Maximum of 9 outputs loaded thresholds on input associated with output under test
8
DC Electrical Characteristics for 'AC Family Devices
(Continued)
74AC
74AC
Symbol
Parameter
V
CC
T
A
e a
25 C
T
A
e
Units
Conditions
(V)
b
40 C to
a
85 C
Typ
Guaranteed Limits
I
OLD
Minimum Dynamic
5 5
75
mA
V
OLD
e
1 65V Max
I
OHD
Output Current
5 5
b
75
mA
V
OHD
e
3 85V Min
I
CC
Maximum Quiescent
5 5
8 0
80 0
m
A
V
IN
e
V
CC
Supply Current
or GND (Note)
I
OZ
Maximum TRI-STATE
V
I
(OE)
e
V
IL
V
IH
Leakage Current
5 5
g
0 5
g
5 0
m
A
V
I
e
V
CC
GND
V
O
e
V
CC
GND
Maximum test duration 2 0 ms one output loaded at a time
Note
I
IN
and I
CC
3 0V are guaranteed to be less than or equal to the respective limit
5 5V V
CC
I
CC
for 54AC
25 C is identical to 74AC
25 C
DC Electrical Characteristics for 'ACT Family Devices
74ACT
54ACT
74ACT
Symbol
Parameter
V
CC
T
A
e a
25 C
T
A
e
T
A
e
Units
Conditions
(V)
b
55 C to
a
125 C
b
40 C to
a
85 C
Typ
Guaranteed Limits
V
IH
Minimum High Level
4 5
1 5
2 0
2 0
2 0
V
V
OUT
e
0 1V
Input Voltage
5 5
1 5
2 0
2 0
2 0
or V
CC
b
0 1V
V
IL
Maximum Low Level
4 5
1 5
0 8
0 8
0 8
V
V
OUT
e
0 1V
Input Voltage
5 5
1 5
0 8
0 8
0 8
or V
CC
b
0 1V
V
OH
Minimum High Level
4 5
4 49
4 4
4 4
4 4
V
I
OUT
e b
50 mA
Output Voltage
5 5
5 49
5 4
5 4
5 4
V
IN
e
V
IL
or V
IH
4 5
3 86
3 70
3 76
V
I
OH
b
24 mA
5 5
4 86
4 70
4 76
b
24 mA
V
OL
Maximum Low Level
4 5
0 001
0 1
0 1
0 1
V
I
OUT
e
50 mA
Output Voltage
5 5
0 001
0 1
0 1
0 1
V
IN
e
V
IL
or V
IH
4 5
0 36
0 50
0 44
V
I
OL
24 mA
5 5
0 36
0 50
0 44
24 mA
I
IN
Maximum Input
5 5
g
0 1
g
1 0
g
1 0
m
A
V
I
e
V
CC
GND
Leakage Current
I
OZ
Maximum TRI-STATE
5 5
g
0 5
g
10 0
g
5 0
m
A
V
I
e
V
IL
V
IH
Leakage Current
V
O
e
V
CC
GND
I
CCT
Maximum I
CC
Input
5 5
0 6
1 6
1 5
mA
V
I
e
V
CC
b
2 1V
I
OLD
Minimum Dynamic
5 5
50
75
mA
V
OLD
e
1 65V Max
I
OHD
Output Current
5 5
b
50
b
75
mA
V
OHD
e
3 85V Min
I
CC
Maximum Quiescent
5 5
8 0
160 0
80 0
m
A
V
IN
e
V
CC
Supply Current
or GND (Note)
Maximum of 9 outputs loaded thresholds on input associated with output under test
Maximum test duration 2 0 ms one output loaded at a time
Note
I
CC
for 54ACT
25 C is identical to 74ACT
25 C
9
AC Electrical Characteristics
74AC
74AC
V
CC
T
A
e a
25 C
T
A
e b
40 C
Fig
Symbol
Parameter
(V)
C
L
e
50 pF
to
a
85 C
Units
No
C
L
e
50 pF
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
3 3
2 5
12 0
15 0
2 5
15 5
ns
1
t
PHL
A
n
B
n
to B
n
A
n
5 0
1 5
7 0
10 0
1 5
10 5
t
PLH
Propagation Delay
3 3
2 5
9 5
12 0
2 5
12 5
ns
1
t
PHL
APAR BPAR to BPAR APAR
5 0
1 5
5 5
8 0
1 5
8 5
t
PLH
Propagation Delay
3 3
3 0
13 5
16 5
3 0
17 0
ns
2
t
PHL
A
n
B
n
to BPAR APAR
5 0
2 0
8 0
11 0
2 0
11 5
t
PLH
Propagation Delay
3 3
2 5
12 5
15 5
2 5
16 5
ns
3
t
PHL
A
n
B
n
to ERRA ERRB
5 0
1 5
7 5
10 5
1 5
11 0
t
PLH
Propagation Delay
3 3
2 5
12 5
15 5
2 5
16 5
ns
4
t
PHL
ODD EVEN to ERRA ERRB
5 0
1 5
7 5
10 5
1 5
11 0
t
PLH
Propagation Delay
3 3
3 0
12 5
15 5
3 0
16 5
ns
5
t
PHL
ODD EVEN to APAR BPAR
5 0
2 0
7 5
10 5
2 0
11 0
t
PLH
Propagation Delay
3 3
2 0
12 5
15 5
2 0
16 5
ns
6
t
PHL
APAR BPAR to ERRA ERRB
5 0
1 5
7 5
10 5
1 5
11 0
t
PLH
Propagation Delay
3 3
2 0
10 0
12 5
2 0
13 5
ns
9
t
PHL
SEL to APAR BPAR
5 0
1 5
6 0
8 5
1 5
9 0
t
PLH
Propagation Delay
3 3
4 0
12 0
15 5
4 0
16 5
ns
10 11
t
PHL
LEB LEA to A
n
B
n
5 0
2 5
7 0
10 5
2 5
11 0
t
PLH
Propagation Delay
3 3
3 0
13 5
17 0
3 0
18 0
ns
10 11
t
PHL
LEB LEA to APAR BPAR
5 0
2 0
8 0
11 5
2 0
12 0
t
PLH
Propagation Delay
3 3
4 0
13 5
17 0
4 0
18 0
ns
12
t
PHL
LEB LEA to ERRA ERRB
5 0
2 5
8 0
11 5
2 5
12 0
t
PZH
Output Enable Time
3 3
3 0
12 5
15 5
3 0
16 5
ns
7 8
t
PZL
GBA GAB to A
n
B
n
5 0
2 0
7 5
10 5
2 0
11 0
t
PZH
Output Enable Time
3 3
2 5
10 5
13 5
2 5
14 0
ns
7 8
t
PZL
GBA GAB to APAR BPAR
5 0
1 5
6 0
9 0
1 5
9 5
t
PHZ
Output Disable Time
3 3
1 5
11 0
14 0
1 5
14 0
ns
7 8
t
PLZ
GBA GAB to A
n
B
n
5 0
1 0
6 5
9 5
1 0
9 5
t
PHZ
Output Disable Time
3 3
1 5
11 0
14 0
1 5
14 0
ns
7 8
t
PHL
GBA GAB to APAR BPAR
5 0
1 0
6 5
9 5
1 0
9 5
Voltage Range 5 0 is 5 0V
g
0 5V
Voltage Range 3 3 is 3 3V
g
0 3V
10
AC Operating Requirements
74AC
74AC
V
CC
T
A
e a
25 C
T
A
e b
40 C
Fig
Symbol
Parameter
(V)
C
L
e
50 pF
to
a
85 C
Units
No
C
L
e
50 pF
Guaranteed Minimum
t
s
Setup Time HIGH or LOW
3 3
3 0
3 0
ns
11 12
A
n
B
n
PAR to LEA LEB
5 0
3 0
3 0
t
h
Hold Time HIGH or LOW
3 3
2 0
2 0
ns
11 12
A
n
B
n
PAR to LEA LEB
5 0
1 5
1 5
t
w
Pulse Width for LEA LEB
3 3
4 0
4 0
ns
13
5 0
4 0
4 0
Voltage Range 5 0 is 5 0V
g
0 5V
Voltage Range 3 3 is 3 3V
g
0 3V
AC Electrical Characteristics
74ACT
54ACT
74ACT
V
CC
T
A
e a
25 C
T
A
e b
55 C
T
A
e b
40 C
Fig
Symbol
Parameter
(V)
C
L
e
50 pF
to
a
125 C
to
a
85 C
Units
No
C
L
e
50 pF
C
L
e
50 pF
Min
Typ
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
5 0
2 5
7 5
11 5
1 5
13 5
2 5
12 0
ns
1
t
PHL
A
n
B
n
to B
n
A
n
t
PLH
Propagation Delay
5 0
1 5
6 0
8 5
1 5
11 0
1 5
9 0
ns
1
t
PHL
APAR BPAR to BPAR APAR
t
PLH
Propagation Delay
5 0
2 5
8 5
12 0
1 5
16 0
2 5
12 5
ns
2
t
PHL
A
n
B
n
to BPAR APAR
t
PLH
Propagation Delay
5 0
2 0
8 0
11 5
1 5
16 0
2 0
12 0
ns
3
t
PHL
A
n
B
n
to ERRA ERRB
t
PLH
Propagation Delay
5 0
2 0
8 0
11 5
1 5
16 0
2 0
12 0
ns
4
t
PHL
ODD EVEN to ERRA ERRB
t
PLH
Propagation Delay
5 0
2 5
8 0
11 5
1 5
14 5
2 5
12 0
ns
5
t
PHL
ODD EVEN to APAR BPAR
t
PLH
Propagation Delay
5 0
1 5
7 5
10 5
1 5
11 5
1 5
11 5
ns
6
t
PHL
APAR BPAR to ERRA ERRB
t
PLH
Propagation Delay
5 0
1 5
6 5
9 0
1 5
12 5
1 5
9 5
ns
9
t
PHL
SEL to APAR BPAR
t
PLH
Propagation Delay
5 0
2 5
7 0
10 5
1 5
13 5
2 5
11 0
ns
10 11
t
PHL
LEB to A
n
B
n
t
PLH
Propagation Delay
5 0
2 0
8 0
11 5
1 5
16 0
2 0
12 0
ns
10 11
t
PHL
LEA to APAR BPAR
t
PLH
Propagation Delay
5 0
2 5
8 0
11 5
1 5
16 0
2 5
12 0
ns
12
t
PHL
LEA LEB to ERRA ERRB
t
PZH
Output Enable Time
5 0
2 5
7 0
10 5
1 5
16 0
2 5
11 0
ns
7 8
t
PZL
GBA or GAB to A
n
B
n
t
PZH
Output Enable Time
5 0
1 5
6 0
9 0
1 5
11 0
1 5
9 5
ns
7 8
t
PZL
GBA or GAB to BPAR or APAR
t
PHZ
Output Disable Time
5 0
1 5
6 5
9 5
1 5
11 0
1 5
9 5
ns
7 8
t
PHL
GBA or GAB to A
n
B
n
t
PHZ
Output Disable Time
5 0
1 5
6 5
9 5
1 5
11 0
1 5
9 5
ns
7 8
t
PLZ
GBA or GAB to BPAR APAR
Voltage Range 5 0 is 5 0V
g
0 5V
11
AC Operating Requirements
74ACT
54ACT
74ACT
V
CC
T
A
e a
25 C
T
A
e b
55 C
T
A
e b
40 C
Fig
Symbol
Parameter
(V)
C
L
e
50 pF
to
a
125 C
to
a
85 C
Units
No
C
L
e
50 pF
C
L
e
50 pF
Guaranteed Minimum
t
s
Setup Time HIGH or LOW
5 0
3 0
3 0
3 0
ns
11 12
A
n
B
n
PAR to LEA LEB
t
h
Hold Time HIGH or LOW
5 0
1 5
3 0
1 5
ns
11 12
A
n
B
n
PAR to LEA LEB
t
w
Pulse Width for LEB LEA
5 0
4 0
4 0
4 0
ns
13
Voltage Range 5 0
e
5 0V
g
0 5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4 5
pF
V
CC
e
5 0V
C
PD
Power Dissipation
210
pF
V
CC
e
5 0V
Capacitance
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows
74ACT
899
Q
C
X
Temperature Range Family
Special Variations
74AC
e
Commercial
X
e
Devices shipped in 13 reels
74ACT
e
Commercial TTL-Compatible
QB
e
Military grade with environmental
54ACT
e
Military TTL-Compatible
and burn-in processing shipped
in tubes
Device Type
Temperature Range
Package Code
C
e
Commercial (
b
40 C to
a
85 C)
Q
e
Plastic Leaded Chip Carrier (PCC)
M
e
Military (
b
55 C to
a
125 C)
12
13
74AC899
54ACT74ACT899
9-Bit
Latchable
Transceiver
with
Parity
GeneratorChecker
Physical Dimensions
inches (millimeters)
Lit
115200
28-Lead Plastic Chip Carrier (Q)
NS Package Number V28A
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION As used herein
1 Life support devices or systems are devices or
2 A critical component is any component of a life
systems which (a) are intended for surgical implant
support device or system whose failure to perform can
into the body or (b) support or sustain life and whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system or to affect its safety or
with instructions for use provided in the labeling can
effectiveness
be reasonably expected to result in a significant injury
to the user
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