TL F 9594
93L08
Dual
4-Bit
Latch
June 1989
93L08
Dual 4-Bit Latch
General Description
The 93L08 is a dual 4-bit D-type latch designed for general
purpose storage applications in digital systems Each latch
contains both an active LOW Master Reset input and active
LOW Enable inputs
Connection Diagram
Dual-In-Line Package
TL F 9594 1
Order Number 93L08DMQB or 93L08FMQB
See NS Package Number J24A or W24C
Logic Symbol
TL F 9594 2
V
CC
e
Pin 24
GND
e
Pin 12
Pin Names
Description
D0a D3a
Parallel Latch Inputs
D0b D3b
(
E0a E1a E0b E1b
AND Enable Inputs (Active LOW)
MRa MRb
Master Reset Inputs (Active LOW)
Q0a Q3a
Parallel Latch Outputs
Q0b Q3b
(
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
5 5V
Operating Free Air Temperature Range
MIL
b
55 C to
a
125 C
Storage Temperature Range
b
65 C to
a
150 C
Note
The ``Absolute Maximum Ratings'' are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ``Electrical Characteristics''
table are not guaranteed at the absolute maximum ratings
The ``Recommended Operating Conditions'' table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4 5
5
5 5
V
V
IH
High Level Input Voltage
2
V
V
IL
Low Level Input Voltage
0 7
V
I
OH
High Level Output Current
b
400
m
A
I
OL
Low Level Output Current
4 8
mA
T
A
Free Air Operating Temperature
b
55
125
C
t
s
(H)
Setup Time HIGH D
n
to E
n
8
ns
t
h
(H)
Hold Time HIGH D
n
to E
n
1
ns
t
s
(L)
Setup Time LOW D
n
to E
n
18
ns
t
h
(L)
Hold Time LOW D
n
to E
n
4
ns
t
w
(L)
E
n
Pulse Width LOW
32
ns
t
w
(L)
MR Pulse Width LOW
30
ns
t
rec
Recovery Time MR to E
n
10
ns
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 1)
V
I
Input Clamp Voltage
V
CC
e
Min I
I
e b
10 mA
b
1 5
V
V
OH
High Level Output Voltage
V
CC
e
Min I
OH
e
Max
2 4
V
V
IL
e
Max V
IH
e
Min
V
OL
Low Level Output Voltage
V
CC
e
Min I
OL
e
Max
0 3
V
V
IH
e
Min V
IL
e
Max
I
I
Input Current
Max
V
CC
e
Max V
I
e
5 5V
1
mA
Input Voltage
I
IH
High Level Input Current
V
CC
e
Max V
I
e
2 4V
Inputs
20
m
A
D
n
30
I
IL
Low Level Input Current
V
CC
e
Max V
I
e
0 3V
Inputs
b
400
m
A
D
n
b
640
I
OS
Short Circuit
V
CC
e
Max (Note 2)
b
2 5
b
25
mA
Output Current
I
CC
Supply Current
V
CC
e
Max (Note 3)
29
mA
Note 1
All typicals are at V
CC
e
5V T
A
e
25 C
Note 2
Not more than one output should be shorted at a time and the duration should not exceed one second
Note 3
I
CC
is measured with all outputs open and all inputs grounded
2
Switching Characteristics
V
CC
e a
5 0V T
A
e a
25 C (See Section 3 for waveforms and load configurations)
Symbol
Parameter
C
L
e
15 pF
Units
Min
Max
t
PLH
Propagation Delay
45
ns
t
PHL
En to Qn
38
t
PLH
Propagation Delay
27
ns
t
PHL
Dn to Qn
29
t
PHL
Propagation Delay
30
ns
MR to Qn
Functional Description
Data can be entered into the latch when both of the enable
inputs are LOW As long as this logic condition exists the
output of the latch will follow the input If either of the enable
inputs goes HIGH the data present in the latch at that time
is held in the latch and is no longer affected by data input
The master reset overrides all other input conditions and
forces the outputs of all the latches LOW when a LOW sig-
nal is applied to the Master Reset input
Truth Table
MR
E0
E1
D
Qn
Operation
H
L
L
L
L
Data Entry
H
L
L
H
L
Data Entry
H
L
H
X
Qn
b
1
Hold
H
H
L
X
Qn
b
1
Hold
H
H
H
X
Qn
b
1
Hold
L
X
X
X
L
Reset
Q
n
b
1
e
Previous Output State
Q
n
e
Present Output State
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Logic Diagram
TL F 9594 3
3
93L08
Dual
4-Bit
Latch
Physical Dimensions
inches (millimeters)
24-Lead Ceramic Dual-In-Line Package (J)
Order Number 93L08DMQB
NS Package Number J24A
24-Lead Ceramic Flat Package (W)
Order Number 93L08FMQB
NS Package Number W24C
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SEMICONDUCTOR CORPORATION As used herein
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be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system or to affect its safety or
with instructions for use provided in the labeling can
effectiveness
be reasonably expected to result in a significant injury
to the user
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