TL F 10202
93L38
8-Bit
Multiple
Port
Register
July 1989
93L38
8-Bit Multiple Port Register
General Description
The 93L38 is an 8-bit multiple port register designed for high
speed random access memory applications where the abili-
ty to simultaneously read and write is desirable A common
use would be as a register bank in a three address comput-
er Data can be written into any one of the eight bits and
read from any two of the eight bits simultaneously The cir-
cuit uses TTL technology and is compatible with all TTL
families
Features
Y
Master slave operation permitting simultaneous write
read without race problems
Y
Simultaneously read two bits and write one bit in any
one of eight bit positions
Y
Readily expandable to allow for larger word sizes
Connection Diagram
Dual-In-Line Package
TL F 10202 1
Order Number 93L38DMQB or 93L38FMQB
See NS Package Number J16A or W16A
Logic Symbol
TL F 10202 2
V
CC
e
Pin 16
GND
e
Pin 8
Pin Names
Description
A0 A2
Write Address Inputs
DA
Data Input
B0 B2
B Read Address Inputs
C0 C2
C Read Address Inputs
CP
Clock Pulse Input (Active Rising Edge)
SLE
Slave Enable Input (Active LOW)
ZB
B Output
ZC
C Output
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
5 5V
Operating Free Air Temperature Range
Military
b
55 C to
a
125 C
Storage Temperature Range
b
65 C to
a
150 C
Note
The ``Absolute Maximum Ratings'' are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ``Electrical Characteristics''
table are not guaranteed at the absolute maximum ratings
The ``Recommended Operating Conditions'' table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
Parameter
93L38 (MIL)
Units
Min
Nom
Max
V
CC
Supply Voltage
4 5
5
5 5
V
V
IH
High Level Input Voltage
2
V
V
IL
Low Level Input Voltage
0 7
V
I
OH
High Level Output Current
b
400
m
A
I
OL
Low Level Output Current
4 8
mA
T
A
Free Air Operating
b
55
125
C
Temperature
t
s
(H)
Setup Time HIGH or LOW
30
ns
t
s
(L)
D
A
to CP
22
t
h
(H)
Hold Time HIGH or LOW
0
ns
t
h
(L)
D
A
to CP
b
4 0
t
s
(H)
Setup Time HIGH or LOW
0
ns
t
s
(L)
A
n
to CP
0
t
h
(H)
Hold Time HIGH or LOW
0
ns
t
h
(L)
A
n
to CP
0
t
w
(H)
CP Pulse Width HIGH or LOW
40
ns
t
w
(L)
30
Electrical Characteristics
over recommended operating free air temperature (unless othewise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 1)
V
I
Input Clamp Voltage
V
CC
e
Min I
I
e b
10 mA
b
1 5
V
V
OH
High Level Output
V
CC
e
Min I
OH
e
Max
2 4
V
Voltage
V
IL
e
Max V
IH
e
Min
V
OL
Low Level Output
V
CC
e
Min I
OL
e
Max
0 3
V
Voltage
V
IH
e
Min V
IL
e
Max
I
I
Input Current
Max
V
CC
e
Max V
I
e
5 5V
1
mA
Input Voltage
I
IH
High Level Input Current
V
CC
e
Max V
I
e
2 4V
50
m
A
I
IL
Low Level Input Current
V
CC
e
Max V
I
e
0 3V
b
2
mA
I
OS
Short Circuit
V
CC
e
Max
b
2 5
b
25
mA
Output Current
(Note 2)
I
CC
Supply Current
V
CC
e
Max (Note 3)
70
mA
Note 1
All typicals are at V
CC
e
5V T
A
e
25 C
Note 2
Not more than one output should be shorted at a time and the duration should not exceed one second
Note 3
I
CC
is measured with all outputs open and all input grounded
2
Switching Characteristics
V
CC
e a
5 0V T
A
e a
25 C (See Section 1 for Test Waveforms and Output Load
Symbol
Parameter
C
L
e
15 pF
Units
Min
Max
t
PLH
Propagation Delay
68
ns
t
PHL
B
n
or C
n
or Z
n
95
t
PLH
Propagation Delay
70
ns
t
PHL
D
A
to Z
n
92
t
PLH
Propagation Delay
65
ns
t
PHL
CP to Z
n
57
Functional Description
The 93L38 8-bit multiple port register can be considered a
1-bit slice of eight high speed working registers Data can be
written into any one and read from any two of the eight
locations simultaneously Master slave operation eliminates
all race problems associated with simultaneous read write
activity from the same location When the clock input (CP) is
LOW data applied to the data input line (D
A
) enters the
selected master This selection is accomplished by coding
the three write input select lines (A0 A2) appropriately
Data is stored synchronously with the rising edge of the
clock pulse
The information for each of the two slaved (output) latches
is selected by two sets of read address inputs (B0 B2 and
C0 C2) The information enters the slave while the clock is
HIGH and is stored while the clock is LOW If Slave Enable
is LOW (SLE) the slave latches are continuously enabled
The signals are available on the output pins (Z
B
and Z
C
)
The input bit selection and the two output bit selections can
be accomplished independently or simultaneously The data
flows into the device is demultiplexed according to the state
of the write address lines and is clocked into the selected
latch The eight latches function as masters and store the
input data The two output latches are slaves and hold the
data during the read operation The state of each slave is
determined by the state of the master selected by its associ-
ated set of read address inputs
The method of parallel expansion is shown in
Figure A One
93L38 is needed for each bit of the required word length
The read and write input lines should be connected in com-
mon on all of the devices This register configuration pro-
vides two words of n-bits each at one time where n devices
are connected in parallel
TL F 10202 4
FIGURE A Parallel Expansion
3
Logic Diagram
TLF10202
3
4
Physical Dimensions
inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 93L38DMQB
NS Package Number J16A
5
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