ADC12DL080
Dual 12-Bit, 80 MSPS, A/D Converter for IF Sampling
General Description
The ADC12DL080 is a dual, low power monolithic CMOS
analog-to-digital converter capable of converting analog in-
put signals into 12-bit digital words at 80 Megasamples per
second (MSPS). This converter uses a differential, pipeline
architecture with digital error correction and an on-chip
sample-and-hold circuit to minimize power consumption
while providing excellent dynamic performance and a 600
MHz Full Power Bandwidth. Operating on a single +3.3V
power supply, the ADC12DL080 achieves 11.0 effective bits
at Nyquist and consumes just 447mW at 80 MSPS. The
Power Down feature reduces power consumption to 50 mW.
The differential inputs provide a full scale differential input
swing equal to 2 times V
REF
with the possibility of a single-
ended input. Full use of the differential input is recom-
mended for optimum performance. Duty cycle stabilization
and output data format are selectable. The output data can
be set for offset binary or two's complement.
To ease interfacing to lower voltage systems, the digital
output driver power pins of the ADC12DL080 can be con-
nected to a separate supply voltage in the range of 2.4V to
the analog supply voltage. This device is available in the
64-lead TQFP package and will operate over the industrial
temperature range of -40C to +85C. An evaluation board is
available to ease the evaluation process.
Features
n
Single +3.3V supply operation
n
Internal sample-and-hold
n
Internal or External reference
n
Outputs 2.4V to 3.6V compatible
n
Power down mode
n
Duty Cycle Stabilizer
n
Pin compatible with ADC12DL040, ADC12DL065,
ADC12DL066
Key Specifications
n
Resolution
12 Bits
n
Max Conversion Rate
80 MSPS
n
DNL
0.4 LSB (typ)
n
SNR (f
IN
=40MHz)
69 dB (typ)
n
SNR (f
IN
=200MHz)
67 dB (typ)
n
SFDR (f
IN
=40MHz)
82 dB (typ)
n
SFDR (f
IN
=200MHz)
81 dB (typ)
n
Power Consumption
-- Operating
447 mW (typ)
-- Power Down Mode
50 mW (typ)
Applications
n
Instrumentation
n
Communications Receivers
n
Sonar/Radar
n
xDSL, Cable Modems
Connection Diagram
20169401
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
February 2006
ADC12DL080
Dual
12-Bit,
80
MSPS,
A/D
Converter
for
IF
Sampling
2006 National Semiconductor Corporation
DS201694
www.national.com
Ordering Information
Industrial (-40C
T
A
+85C)
Package
ADC12DL080CIVS
64 Pin TQFP
ADC12DL080EVAL
Evaluation Board
Block Diagram
20169402
ADC12DL080
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2
Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
15
2
V
IN
A+
V
IN
B+
Differential analog input pins. With a 1.0V reference voltage the
differential full-scale input signal level is 2.0 V
P-P
with each
input pin voltage centered on a common mode voltage, V
CM
.
The negative input pins may be connected to V
CM
for
single-ended operation, but a differential input signal is
required for best performance.
16
1
V
IN
A-
V
IN
B-
7
V
REF
This pin is used in conjunction with REFSEL/DCS (pin 11) to
select the internal 1.0V reference, or as the external reference
input.
If V
REF
is tied HIGH, the internal 1.0V reference is selected.
REFSEL/DCS must be LOW or tied to V
RM
A or V
RM
B.
If a voltage in the range of 0.8V to 1.2V is applied to this pin,
that voltage is used as the reference. V
REF
should be
bypassed to AGND with a 0.1 F low ESL capacitor when an
external reference is used. The nominal external reference
voltage is 1.0V but values in the range of 0.8V to 1.2V may be
used. REFSEL/DCS must be HIGH or tied to V
RM
A or V
RM
B.
See Table 3 in Section 2.2 for more information.
11
REFSEL/DCS
This pin is used in conjunction with V
REF
(pin 7) to select the
reference source and turn the Duty Cycle Stabilizer (DCS) on
or off.
When REFSEL/DCS is LOW and V
REF
is HIGH, the internal
1.0V reference is selected and DCS is On.
When REFSEL/DCS is HIGH, an external reference voltage in
the range of 0.8V to 1.2V should be applied to the V
REF
input.
DCS is On.
With this pin connected to V
RM
A or V
RM
B, DCS is Off.
See Table 3 in Section 2.2 for more information.
13
5
V
RP
A
V
RP
B
These are reference bypass pins. These pins should each be
bypassed to ground with a 0.1 F capacitor. A 10 F capacitor
should be placed between the V
RP
A and V
RN
A pins and
between the V
RP
B and V
RN
B pins.
These pins should not be loaded.
14
4
V
RM
A
V
RM
B
12
6
V
RN
A
V
RN
B
DIGITAL I/O
60
CLK
Digital clock input. The range of frequencies for this input is as
specified in the electrical tables with guaranteed performance
at 80 MHz. The inputs are sampled on the rising edge.
ADC12DL080
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3
Pin Descriptions and Equivalent Circuits
(Continued)
Pin No.
Symbol
Equivalent Circuit
Description
21
OF/DOEN
OF/DOEN selects the output format (OF) or enables the DRDY
output (DOEN). The state of this pin also controls the function
of pins 22 and 41.
When OF/DOEN is tied to V
RM
A or V
RM
B, DRDY is enabled.
Pin 41 is used as the DRDY output strobe, and pin 22 is used
to select the output format. Output Enable for channels A and
B are not available in this mode.
When OF/DOEN is LOW, the output data format is offset
binary.
With OF/DOEN tied HIGH, the output format is 2's
complement.
See Table 4 in Section 2.3 for more information.
22
OEA/OF
Output Enable for Channel A (OEA ) or Output format (OF).
The function of this pin is controlled by the state of pin 21.
When DRDY is enabled (pin 21 tied to V
RM
A or V
RM
B) this pin
sets the output format. When LOW, the output data format is
offset binary. When HIGH, the output format is 2's
complement.
When DRDY is not enabled (pin 21 is LOW or HIGH) this pin
is the Output Enable for Channel A. When LOW the outputs for
Channel A are active. When HIGH, the outputs for Channel A
are in a high impedance state.
See Table 4 in Section 2.3 for more information.
41
OEB/DRDY
Output Enable for Channel B (OEB ) or Data Ready Output
strobe (DRDY). The function of this pin is controlled by the
state of pin 21.
When DRDY is enabled (pin 21 tied to V
RM
A or V
RM
B) this pin
is the DRDY output. The data outputs are synchronized with
the falling edge of this signal. This signal switches at the same
rate as the input clock.
When DRDY is not enabled (pin 21 is LOW or HIGH) this pin
is the Output Enable for Channel B. When LOW the outputs for
Channel B are active. When HIGH, the outputs for Channel B
are in a high impedance state.
See Table 4 in Section 2.3 for more information.
59
PD
PD is the Power Down input pin. When high, this input puts the
converter into the power down mode. When this pin is low, the
converter is in the active mode.
2429
3439
DA0DA5
DA6-DA11
Digital data output pins that make up the 12-bit conversion
results of their respective converters. DA0 and DB0 are the
LSBs, while DA11 and DB11 are the MSBs of the output word.
Output levels are TTL/CMOS compatible. Optimum loading is
<
10pF.
4247
5257
DB0DB5
DB6-DB11
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4
Pin Descriptions and Equivalent Circuits
(Continued)
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG POWER
9, 18, 19,
62, 63
V
A
Positive analog supply pins. These pins should be connected
to a quiet +3.3V source and bypassed to AGND with 0.1 F
capacitors located near the power pins, and with a 10 F
capacitor.
3, 8, 10, 17,
20, 61, 64
AGND
The ground return for the analog supply.
DIGITAL POWER
33, 48
V
D
Positive digital supply pin. This pin should be connected to the
same quiet +3.3V source as is V
A
and be bypassed to DGND
with a 0.1 F capacitor located near the power pins, and with a
10 F capacitor.
32, 49
DGND
The ground return for the digital supply.
30, 51
V
DR
Positive driver supply pin for the ADC12DL080's output drivers.
This pin should be connected to a voltage source of +2.4V to
V
D
and be bypassed to DRGND with a 0.1 F capacitor. This
supply should also be bypassed with a 10 F capacitor. V
DR
should never exceed the voltage on V
D
. All 0.1 F bypass
capacitors should be located near the supply pin.
23, 31, 40,
50, 58
DRGND
The ground return for the digital supply for the ADC12DL080's
output drivers. These pins should be connected to the system
digital ground, but not be connected in close proximity to the
ADC12DL080's DGND or AGND pins. See Section 5 (Layout
and Grounding) for more details.
ADC12DL080
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