TL H 11025
ADC12451
Dynamically-Tested
Self-Calibrating
12-Bit
Plus
Sign
AD
Converter
with
Sample-and-Hold
December 1994
ADC12451 Dynamically-Tested Self-Calibrating
12-Bit Plus Sign A D Converter with Sample-and-Hold
General Description
The ADC12451 is a CMOS 12-bit plus sign successive ap-
proximation analog-to-digital converter whose dynamic
specifications (S N THD etc ) are tested and guaranteed
On request the ADC12451 goes through a self-calibration
cycle that adjusts linearity zero and full-scale errors The
ADC12451 also has the ability to go through an Auto-Zero
cycle that corrects the zero error during every conversion
The analog input to the ADC12451 is tracked and held by
the internal circuitry so an external sample-and-hold is not
required The ADC12451 has a S H control input which di-
rectly controls the track-and-hold state of the A D A unipo-
lar analog input voltage range (0V to
a
5V) or a bipolar
range (
b
5V to
a
5V) can be accommodated with
g
5V sup-
plies
The 13-bit data result is available on the eight outputs of the
ADC12451 in two bytes high-byte first and sign extended
The digital inputs and outputs are compatible with TTL or
CMOS logic levels
Applications
Y
Digital Signal Processing
Y
Audio
Y
Telecommunications
Y
High Resolution Process Control
Y
Instrumentation
Features
Y
Self-calibration provides excellent temperature stability
Y
Internal sample-and-hold
Y
8-bit mP DSP interface
Y
Bipolar input range with a single
a
5V reference
Key Specifications
Y
Resolution
12 bits plus sign
Y
Conversion Time
7 7 ms (max)
Y
Sampling Rate
83 kHz (max)
Y
Bipolar Signal Noise
73 5 dB (min)
Y
Total Harmonic Distortion
b
78 0 dB (max)
Y
Aperture Time
100 ns
Y
Aperture Jitter
100 ps
rms
Y
Zero Error
g
2 LSB (max)
Y
Positive Full-Scale Error
g
1 5 LSB (max)
Y
Power Consumption
g
5V
113 mW (max)
Simplified Block Diagram
TL H 11025 1
Connection Diagram
Dual-In-Line Package
TL H 11025 2
Top View
Ordering Information
Industrial
Package
(
b
40 C
s
T
A
s
85 C)
ADC12451CIJ
J24A
Military
Package
(
b
55 C
s
T
A
s
125 C)
ADC12451CMJ
J24A
ADC12451CMJ 883
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M115 Printed in U S A
Absolute Maximum Ratings
(Notes 1
2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
CC
e
DV
CC
e
AV
CC
)
6 5V
Negative Supply Voltage (V
b
)
b
6 5V
Voltage at Logic Control Inputs
b
0 3V to (V
CC
a
0 3V)
Voltage at Analog Inputs
(V
IN
V
REF
)
(V
b
b
0 3V) to (V
CC
a
0 3V)
AV
CC
-DV
CC
(Note 7)
0 3V
Input Current at any Pin (Note 3)
g
5 mA
Package Input Current (Note 3)
g
20 mA
Power Dissipation at 25 C (Note 4)
875 mW
Storage Temperature Range
b
65 C to
a
150 C
ESD Susceptability (Note 5)
2000V
Soldering Information
J Package (10 Seconds)
300 C
Operating Ratings
(Notes 1
2)
Temperature Range
T
MIN
s
T
A
s
T
MAX
ADC12451CIJ
b
40 C
s
T
A
s
a
85 C
ADC12451CMJ
ADC12451CMJ 883
b
55 C
s
T
A
s
a
125 C
DV
CC
and AV
CC
Voltage
(Notes 6
7)
4 5V to 5 5V
Negative Supply Voltage (V
b
)
b
4 5V to
b
5 5V
Reference Voltage
(V
REF
Notes 6
7)
3 5V to AV
CC
a
50 mV
Converter Electrical Characteristics
The following specifications apply for V
CC
e
DV
CC
e
AV
CC
e a
5 0V V
b
e b
5 0V V
REF
e a
5 0V using S H input for
conversion control and f
CLK
e
3 5 MHz unless otherwise specified Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
all
other limits T
A
e
T
J
e
25 C (Notes 6 7 and 8)
Symbol
Parameter
Conditions
Typical
Limit
Units
(Note 9)
(Note 10 19)
(Limit)
STATIC CHARACTERISTICS
Positive Integral Linearity Error
After Auto-Cal (Notes 11
12)
g
LSB
Negative Integral Linearity Error
After Auto-Cal (Notes 11
12)
g
LSB
Positive or Negative Differential Linearity
After Auto-Cal (Notes 11
12)
12
Bits
Zero Error (Notes 12
13)
AZ
e
``0'' f
CLK
e
1 75 MHz
g
1
LSB
After Auto-Cal Only
g
2
g
3 0
LSB(max)
Positive Full-Scale Error (Note 12)
AZ
e
``0'' f
CLK
e
1 75 MHz
g
1
LSB
Auto-Cal Only
g
1 5
g
2 5
LSB(max)
Negative Full-Scale Error (Note 12)
AZ
e
``0'' f
CLK
e
1 75 MHz
g
1
LSB
Auto-Cal Only
g
1 5
g
3 0
LSB(max)
V
IN
Analog Input Voltage
V
b
b
0 05
V(min)
V
CC
a
0 05
V(max)
Power Supply Sensitivity
Zero Error (Note 14) AV
CC
e
DV
CC
e
5V
g
5%
g
LSB
Full-Scale Error
V
REF
e
4 75V V
b
e b
5V
g
5%
g
LSB
Linearity Error
g
LSB
C
REF
V
REF
Input Capacitance
80
pF
C
IN
Analog Input Capacitance
65
pF
DYNAMIC CHARACTERISTICS
Bipolar Effective Bits (Note 17)
f
IN
e
1 kHz V
IN
e
g
4 85V
12 6
Bits
f
IN
e
20 67 kHz V
IN
e
g
4 85V
12 6
11 9
Bits(min)
Unipolar Effective Bits (Note 17)
f
IN
e
1 kHz V
IN
e
4 85 V
p-p
11 8
Bits
f
IN
e
20 67 kHz V
IN
e
4 85 V
p-p
11 8
11 1
Bits(min)
S N
Bipolar Signal to Noise Ratio (Note 17)
f
IN
e
1 kHz V
IN
e
g
4 85V
78
dB
f
IN
e
10 kHz V
IN
e
g
4 85V
78
dB
f
IN
e
20 67 kHz V
IN
e
g
4 85V
78
73 5
dB(min)
2
Converter Electrical Characteristics
(Continued)
The following specifications apply for V
CC
e
DV
CC
e
AV
CC
e a
5 0V V
b
e b
5 0V V
REF
e a
5 0V using S H input for
conversion control and f
CLK
e
3 5 MHz unless otherwise specified Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
all
other limits T
A
e
T
J
e
25 C (Notes 6 7 and 8)
Symbol
Parameter
Conditions
Typical
Limit
Units
(Note 9) (Note 10 19)
(Limit)
DYNAMIC CHARACTERISTICS
(Continued)
S N
Unipolar Signal to Noise Ratio (Note 17)
f
IN
e
1 kHz V
IN
e
4 85 V
p-p
73
dB
f
IN
e
10 kHz V
IN
e
4 85 V
p-p
73
dB
f
IN
e
20 67 kHz V
IN
e
4 85 V
p-p
73
68 7
dB(min)
THD
Bipolar Total Harmonic Distortion (Note 17)
f
IN
e
1 kHz V
IN
e
g
4 85V
b
82
dB
f
IN
e
20 67 kHz V
IN
e
g
4 85V
b
80
b
78 0
dB(max)
THD
Unipolar Total Harmonic Distortion (Note 17)
f
IN
e
1 kHz V
IN
e
4 85 V
p-p
b
82
dB
f
IN
e
20 67 kHz V
IN
e
4 85 V
p-p
b
80
b
73 1
dB(max)
Bipolar Peak Harmonic or Spurious Noise
f
IN
e
1 kHz V
IN
e
g
4 85V
b
88
dB
(Note 17)
f
IN
e
10 kHz V
IN
e
g
4 85V
b
84
dB
f
IN
e
20 kHz V
IN
e
g
4 85V
b
80
dB
Unipolar Peak Harmonic or Spurious Noise
f
IN
e
1 kHz V
IN
e
4 85 V
p-p
b
90
dB
(Note 17)
f
IN
e
10 kHz V
IN
e
4 85 V
p-p
b
86
dB
f
IN
e
20 kHz V
IN
e
4 85 V
p-p
b
82
dB
Bipolar Two Tone Intermodulation Distortion
V
IN
e
g
4 85V f
IN1
e
19 375 kHz
b
78
dB(max)
(Note 17)
f
IN2
e
20 kHz
Unipolar Two Tone Intermodulation Distortion
V
IN
e
4 85 V
p-p
f
IN1
e
19 375 kHz
b
78
dB(max)
(Note 17)
f
IN2
e
20 kHz
b
3 dB Bipolar Full Power Bandwidth
V
IN
e
g
4 85V (Note 17)
25
20 67
kHz(min)
b
3 dB Unipolar Full Power Bandwidth
V
IN
e
4 85 V
p-p
(Note 17)
32
20 67
kHz(min)
Aperture Time
100
ns
Aperture Jitter
100
ps
rms
3
Digital and DC Electrical Characteristics
The following specifications apply for DV
CC
e
AV
CC
e a
5 0V V
b
e b
5 0V V
REF
e a
5 0V and f
CLK
e
3 5 MHz unless
otherwise specified Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
all other limits T
A
e
T
J
e
25 C (Notes 6 and 7)
Symbol
Parameter
Condition
Typical
Limit
Units
(Note 9)
(Note 10 19)
(Limit)
V
IN(1)
Logical ``1'' Input Voltage for
V
CC
e
5 25V
2 0
V(min)
All Inputs except CLK IN
V
IN(0)
Logical ``0'' Input Voltage for
V
CC
e
4 75V
0 8
V(max)
All Inputs except CLK IN
I
IN(1)
Logical ``1'' Input Current
V
IN
e
5V
0 005
1
m
A(max)
I
IN(0)
Logical ``0'' Input Current
V
IN
e
0V
b
0 005
b
1
m
A(max)
V
T
a
CLK IN Positive-Going
2 8
2 7
V(min)
Threshold Voltage
V
T
b
CLK IN Negative-Going
2 1
2 3
V(max)
Threshold Voltage
V
H
CLK IN Hysteresis
0 7
0 4
V(min)
V
T
a
(min)
b
V
T
b
(max)
V
OUT(1)
Logical ``1'' Output Voltage
V
CC
e
4 75V
I
OUT
e b
360 mA
2 4
V(min)
I
OUT
e b
10 mA
4 5
V(min)
V
OUT(0)
Logical ``0'' Output Voltage
V
CC
e
4 75V
0 4
V(max)
I
OUT
e
1 6 mA
I
OUT
TRI-STATE Output Leakage
V
OUT
e
0V
b
0 01
b
3
m
A(max)
Current
V
OUT
e
5V
0 01
3
m
A(max)
I
SOURCE
Output Source Current
V
OUT
e
0V
b
20
b
6 0
mA(min)
I
SINK
Output Sink Current
V
OUT
e
5V
20
8 0
mA(min)
DI
CC
DV
CC
Supply Current
CS
e
``1''
1
2 5
mA(max)
AI
CC
AV
CC
Supply Current
CS
e
``1''
2 8
10
mA(max)
I
b
V
b
Supply Current
CS
e
``1''
2 8
10
mA(max)
AC Electrical Characteristics
The following specifications apply for DV
CC
e
AV
CC
e
a
5 0V V
b
e
b
5 0V t
r
e
t
f
e
20 ns unless otherwise specified
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
all other limits T
A
e
T
J
e
25 C (Notes 6 and 7)
Symbol
Parameter
Conditions
Typical
Limit
Units
(Note 9)
(Note 10 19)
(Limit)
f
CLK
Clock Frequency
MHz
0 5
MHz(min)
6 0
3 5
MHz(max)
Clock Duty Cycle
50
%
40
%(min)
60
%(max)
t
C
Conversion Time using WR
27(1 f
CLK
)
27(1 f
CLK
)
a
250 ns
(max)
to start a Conversion
f
CLK
e
3 5 MHz AZ
e
``1''
7 7
7 95
m
s(max)
f
CLK
e
1 75 MHz AZ
e
``0''
15 4
15 65
m
s(max)
t
C
Conversion Time using S H
AZ
e
``1''
34(1 f
CLK
)
34(1 f
CLK
)
a
250 ns
(max)
to start a Conversion
f
CLK
e
3 5 MHz AZ
e
``1''
9 7
9 95
m
s(max)
4
AC Electrical Characteristics
(Continued)
The following specifications apply for DV
CC
e
AV
CC
e
a
5 0V V
b
e
b
5 0V t
r
e
t
f
e
20 ns unless otherwise specified
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
all other limits T
A
e
T
J
e
25 C (Notes 6 and 7)
Symbol
Parameter
Conditions
Typical
Limit
Units
(Note 9)
(Note 10 19)
(Limit)
t
A
Acquisition Time
R
SOURCE
e
50X
3 5
3 5
m
s(min)
(Note 15)
t
IA
Internal Acquisition Time
7(1 f
CLK
)
7(1 f
CLK)
(max)
(when using WR Control Only)
t
ZA
Auto Zero Time
a
33(1 f
CLK
)
33(1 f
CLK
)
a
250 ns
(max)
Acquisition Time
f
CLK
e
1 75 MHz
18 8
19 05
m
s(max)
t
D(EOC)L
Delay from Hold Command
Using WR Control
200
350
ns(max)
to Falling Edge of EOC
Using S H Control
100
150
ns(max)
t
CAL
Calibration Time
1399 (1 f
CLK
)
1399 (1 f
CLK
)
(max)
f
CLK
e
3 5 MHz
399
400
m
s(max)
t
W(CAL)L
Calibration Pulse Width
(Note 16)
60
200
ns(min)
t
W(WR)L
minimum WR Pulse Width
60
200
ns(min)
t
ACC
maximum Access Time
C
L
e
100 pF
(Delay from Falling Edge of
50
95
ns(max)
RD to Output Data Valid)
t
0H
t
1H
TRI-STATE Control (Delay
R
L
e
1 kX
from Rising Edge of RD
C
L
e
100 pF
30
70
ns(max)
to Hi-Z State)
t
PD(INT)
maximum Delay from Falling Edge
100
175
ns(max)
of RD or WR to Reset of INT
t
RR
Delay between Successive RD Pulses
30
60
ns(min)
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is
functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed
specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test
conditions
Note 2
All voltages are measured with respect to AGND and DGND unless otherwise specified
Note 3
When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
k
V
b
or V
IN
l
(AV
CC
or DV
CC
) the current at that pin should be limited to
5 mA The 20 mA maximum package input current rating allows the voltage at any four pins with an input current limit of 5 mA to simultaneously exceed the power
supply voltages
Note 4
The power dissipation of this device under normal operation should never exceed 191 mW (Quiescent Power Dissipation
a
1 TTL Load on each digital
output) Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (ex when any inputs or
outputs exceed the power supply) The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMax
(maximum junction
temperature) i
JA
(package junction to ambient thermal resistance) and T
A
(ambient temperature) The maximum allowable power dissipation at any temperature
is P
DMax
e
(T
JMax
b
T
A
) i
JA
or the number given in the Absolute Maximum Ratings whichever is lower For this device T
JMax
e
150 C and the typical thermal
resistance (i
JA
) of the ADC12451 with CMJ and CIJ suffixes when board mounted is 51 C W
Note 5
Human body model 100 pF discharged through a 1 5 kX resistor
Note 6
Two on-chip diodes are tied to the analog input as shown below Errors in the A D conversion can occur if these diodes are forward biased more than
50 mV This means that if AV
CC
and DV
CC
are minimum (4 75 V
DC
) and V
b
is maximum (
b
4 75 V
DC
) the analog input full-scale voltage must be
s g
4 8 V
DC
TL H 11025 4
5
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