TL F 5963
CD4034BMCD4034BC
8-Stage
TRI-STATE
Bidirectional
ParallelSerial
InputOutput
Bus
Register
February 1988
CD4034BM CD4034BC 8-Stage TRI-STATE
Bidirectional
Parallel Serial Input Output Bus Register
General Description
The CD4034BM CD4034BC is an 8-bit CMOS static shift
register with two parallel bidirectional data ports (A and B)
which when combined with serial shifting operations can
be used to (1) bidirectionally transfer parallel data between
two buses (2) convert serial data to parallel form and direct
them to either of two buses (3) store (recirculate) parallel
data or (4) accept parallel data from either of two buses
and convert them to serial form These operations are con-
trolled by five control inputs
A ENABLE (AE)
``A'' data port is enabled only when AE
is at logical ``1'' This allows the use of a common bus
for multiple packages
A-BUS-TO-B-BUS B-BUS-TO-A-BUS (A B)
This input
controls the direction of data flow When at logical `'1''
data flows from port A to B (A is input B is output)
When at logical ``0'' the data flow direction is reversed
ASYNCHRONOUS SYNCHRONOUS (A S)
When A S
is at logical ``0'' data transfer occurs at positive tran-
sition of the CLOCK When A S is at logical ``1'' data
transfer is independent of the CLOCK for parallel opera-
tion In serial mode A S input is internally disabled such
that operation is always synchronous (Asynchronous
serial operation is not possible )
PARALLEL SERIAL (P S)
A logical ``1'' P S input al-
lows data transfer into the registers via A or B port (syn-
chronous if A S
e
logical ``0'' asynchronous if A S
e
logical ``1'') A logical ``0'' P S allows serial data to
transfer into the register synchronously with the positive
transition of the CLOCK independent of the A S input
CLOCK
Single phase enabled only in synchronous
mode (Either P S
e
logical ``1'' and A S
e
logical ``0''
or P S
e
logical ``0''
All register stages are D-type master-slave flip-flops with
separate master and slave clock inputs generated internally
to allow synchronous or asynchronous data transfer from
master to slave
All inputs are protected against damage due to static dis-
charge by diode clamps to V
DD
and V
SS
Features
Y
Wide supply voltage range
3 0V to 18V
Y
High noise immunity
0 45 V
DD
(typ )
Y
Low power TTL
Fan out of 2 driving 74L
compatibility
or 1 driving 74LS
Y
RCA CD4034B second source
Applications
Y
Parallel Input Parallel Output
Parallel Input Serial Output
Serial Input Parallel Output
Serial Input Serial Output register
Y
Shift right shift left register
Y
Shift right shift left with parallel loading
Y
Address register
Y
Buffer register
Y
Bus system register with enable parallel lines at bus
side
Y
Double bus register system
Y
Up-down Johnson or ring counter
Y
Pseudo-random code generators
Y
Sample and hold register (storage counting display)
Y
Frequency and phase comparator
Connection Diagram
Dual-In-Line Package
TL F 5963 1
Top View
Order Number CD4034B
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Notes 1
2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
DC Supply Voltage (V
DD
)
b
0 5 V
DC
to
a
18 V
DC
Input Voltage (V
IN
)
b
0 5 V
DC
to V
DD
a
0 5 V
DC
Storage Temp Range (T
S
)
b
65 C to
a
150 C
Power Dissipation (P
D
)
Dual-In-Line
700 mW
Small Outline
500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds)
260 C
Recommended Operating
Conditions
(Note 2)
DC Supply Voltage (V
DD
)
a
3 V
DC
to
a
15 V
DC
Input Voltage (V
IN
)
0 V
DC
to V
DD
V
DC
Operating Temperature Range (T
A
)
CD4034BM
b
55 C to
a
125 C
CD4034BC
b
40 C to
a
85 C
DC Electrical Characteristics
CD4034BM (Note 2)
Symbol
Parameter
Conditions
b
55 C
a
25 C
a
125 C
Units
Min
Max
Min
Typ
Max
Min
Max
I
DD
Quiescent Device Current
V
DD
e
5V V
IN
e
V
DD
or V
SS
5
5
150
m
A
V
DD
e
10V V
IN
e
V
DD
or V
SS
10
10
300
m
A
V
DD
e
15V V
IN
e
V
DD
or V
SS
20
20
600
m
A
V
OL
Low Level Output Voltage
V
DD
e
5V
0 05
0 05
0 05
V
V
DD
e
10V
0 05
0 05
0 05
V
V
DD
e
15V
0 05
0 05
0 05
V
V
OH
High Level Output Voltage V
DD
e
5V
4 95
4 95
4 95
V
V
DD
e
10V
9 95
9 95
9 95
V
V
DD
e
15V
14 95
14 95
14 95
V
V
IL
Low Level Input Voltage
V
DD
e
5V V
O
e
0 5V or 4 5V
1 5
1 5
1 5
V
V
DD
e
10V V
O
e
1 0V or 9 0V
3 0
3 0
3 0
V
V
DD
e
15V V
O
e
1 5V or 13 5V
4 0
4 0
4 0
V
V
IH
High Level Input Voltage
V
DD
e
5V V
O
e
0 5V or 4 5V
3 5
3 5
3 5
V
V
DD
e
10V V
O
e
1 0V or 9 0V
7 0
7 0
7 0
V
V
DD
e
15V V
O
e
1 5V or 13 5V
11 0
11 0
11 0
V
I
OL
Low Level Output Current
V
DD
e
5V V
O
e
0 4V
0 64
0 51
0 36
mA
(Note 3)
V
DD
e
10V V
O
e
0 5V
1 6
1 3
0 9
mA
V
DD
e
15V V
O
e
1 5V
4 2
3 4
2 4
mA
I
OH
High Level Output Current
V
DD
e
5V V
O
e
4 6V
b
0 64
b
0 51
b
0 36
mA
(Note 3)
V
DD
e
10V V
O
e
9 5V
b
1 6
b
1 3
b
0 9
mA
V
DD
e
15V V
O
e
13 5V
b
4 2
b
3 4
b
2 4
mA
I
IN
Input Curent
V
DD
e
15V V
IN
e
0V
b
0 1
b
0 1
b
10
-5
b
1 0
m
A
V
DD
e
15V V
IN
e
15V
0 1
10
-5
0 1
1 0
m
A
I
OZ
TRI-STATE Leakage
V
DD
e
15V V
O
e
0V
b
0 1
b
0 1
b
10
-5
b
1 0
m
A
Current
V
DD
e
15V V
O
e
15V
0 1
10
-5
0 1
1 0
m
A
Note 1
``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed Except for ``Operating Temperature Range''
they are not meant to imply that the devices should be operated at these limits The table of ``Electrical Characteristics'' provides conditions for actual device
operation
Note 2
V
SS
e
0V unless otherwise specified
Note 3
I
OH
and I
OL
are tested one output at a time
2
DC Electrical Characteristics
CD4034BC (Note 2)
Symbol
Parameter
Conditions
b
40 C
a
25 C
a
85 C
Units
Min
Max
Min
Typ
Max
Min
Max
I
DD
Quiescent Device Current
V
DD
e
5V V
IN
e
V
DD
or V
SS
20
20
150
m
A
V
DD
e
10V V
IN
e
V
DD
or V
SS
40
40
300
m
A
V
DD
e
15V V
IN
e
V
DD
or V
SS
80
80
600
m
A
V
OL
Low Level Output Voltage
V
DD
e
5V
0 05
0 05
0 05
V
V
DD
e
10V
0 05
0 05
0 05
V
V
DD
e
15V
0 05
0 05
0 05
V
V
OH
High Level Output Voltage V
DD
e
5V
4 95
4 95
4 95
V
V
DD
e
10V
9 95
9 95
9 95
V
V
DD
e
15V
14 95
14 95
14 95
V
V
IL
Low Level Input Voltage
V
DD
e
5V V
O
e
0 5V or 4 5V
1 5
1 5
1 5
V
V
DD
e
10V V
O
e
1 0V or 9 0V
3 0
3 0
3 0
V
V
DD
e
15V V
O
e
1 5V or 13 5V
4 0
4 0
4 0
V
V
IH
High Level Input Voltage
V
DD
e
5V V
O
e
0 5V or 4 5V
3 5
3 5
3 5
V
V
DD
e
10V V
O
e
1 0V or 9 0V
7 0
7 0
7 0
V
V
DD
e
15V V
O
e
1 5V or 13 5V
11 0
11 0
11 0
V
I
OL
Low Level Output Current
V
DD
e
5V V
O
e
0 4V
0 52
0 44
0 36
mA
(Note 3)
V
DD
e
10V V
O
e
0 5V
1 3
1 1
0 9
mA
V
DD
e
15V V
O
e
1 5V
3 6
3 0
2 4
mA
I
OH
High Level Output Current
V
DD
e
5V V
O
e
4 6V
b
0 52
b
0 44
b
0 36
mA
(Note 3)
V
DD
e
10V V
O
e
9 5V
b
1 3
b
1 1
b
0 9
mA
V
DD
e
15V V
O
e
13 5V
b
3 6
b
3 0
b
2 4
mA
I
IN
Input Current
V
DD
e
15V V
IN
e
0V
b
0 3
b
0 3
b
10
-5
b
1 0
m
A
V
DD
e
15V V
IN
e
15V
0 3
10
-5
0 3
1 0
m
A
I
OZ
TRI-STATE Leakage
V
DD
e
15V V
O
e
0V
b
0 3
b
0 3
b
10
-5
b
1 0
m
A
Current
V
DD
e
15V V
O
e
15V
0 3
10
-5
0 3
1 0
m
A
AC Electrical Characteristics
T
A
e
25 C C
L
e
50 pF R
L
e
200k input t
r
e
t
f
e
20 ns unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
PHL
t
PLH
Propagation Delay Time A (B)
V
DD
e
5V
280
700
ns
Synchronous Parallel Data or Serial
V
DD
e
10V
120
270
ns
Data Input B (A) Parallel Data
V
DD
e
15V
85
190
ns
Output
t
PHL
t
PLH
Propagation Delay Time A (B)
V
DD
e
5V
280
700
ns
A (B) Asynchronous Parallel Data
V
DD
e
10V
120
270
ns
Input B (A) Parallel Data Output
V
DD
e
15V
85
190
ns
t
PHZ
t
PLZ
Propagation Delay Time from A B
V
DD
e
5V
R
L
e
1 0 kX
95
220
ns
or AE to High Impedance State at A
V
DD
e
10V R
L
e
1 0 kX
60
130
ns
Outputs or from A B to High
V
DD
e
15V R
L
e
1 0 kX
45
100
ns
Impedance State at B Outputs
t
PZH
t
PZL
Propagation Delay Time from A B
V
DD
e
5V
R
L
e
1 0 kX
180
480
ns
or AE to Logical ``1'' or Logical ``0''
V
DD
e
10V R
L
e
1 0 kX
75
190
ns
State at A Outputs or from A B to
V
DD
e
15V R
L
e
1 0 kX
55
140
ns
Logical ``1'' or Logical ``0'' State at
B Outputs
3
AC Electrical Characteristics
T
A
e
25 C C
L
e
50 pF R
L
e
200k input t
r
e
t
f
e
20 ns unless otherwise specified (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
THL
t
TLH
Output Transition Time
V
DD
e
5V
100
200
ns
V
DD
e
10V
50
100
ns
V
DD
e
15V
40
80
ns
f
CL
Maximum Clock Input Frequency
V
DD
e
5V
2
4
MHz
V
DD
e
10V
5
10
MHz
V
DD
e
15V
7
14
MHz
t
WL
t
WH
Minimum Clock Pulse Width
V
DD
e
5V
125
250
ns
V
DD
e
10V
50
100
ns
V
DD
e
15V
35
70
ns
t
RCL
t
FCL
Maximum Clock Rise
Fall Time
V
DD
e
5V
15
m
s
V
DD
e
10V
15
m
s
V
DD
e
15V
15
m
s
t
SU
Parallel (A or B) and Serial Data
V
DD
e
5V
25
70
ns
Setup Time
V
DD
e
10V
10
30
ns
V
DD
e
15V
7
20
ns
t
SU
Control Inputs AE A B P S
V
DD
e
5V
110
280
ns
A S Setup Time
V
DD
e
10V
35
100
ns
V
DD
e
15V
60
60
ns
t
WH
Minimum High Level AE A B P S
V
DD
e
5V
160
400
ns
A S Pulse Width
V
DD
e
10V
70
160
ns
V
DD
e
15V
40
90
ns
C
IN
Average Input Capacitance
A and B Data I O and A B Control
7
15
pF
Input
Any Other Input
5
7 5
pF
C
PD
Power Dissipation Capacitance
(Note 4)
155
pF
AC Parameters are guaranteed by DC correlated testing
Note 4
C
PD
determines the no-load power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics application note
AN-90
Logic Diagram
TL F 5963 2
4
Schematic Diagram
TL F 5963 3
5
PDF 
ZIP