TL F 11920
CGS701AV
Commercial
Low
Skew
PLL
1
t
o
8
CMOS
Clock
Driver
CGS701ATV
Industrial
Low
Skew
PLL
1
t
o
8
CMOS
Clock
Driver
December 1995
CGS701AV
Commercial Low Skew PLL 1 to 8 CMOS Clock Driver
CGS701ATV
Industrial Low Skew PLL 1 to 8 CMOS Clock Driver
General Description
CGS701A is an off the shelf clock driver specifically de-
signed for today's high speed designs It provides low skew
outputs which are produced at different frequencies from
three fixed input references The XTALIN input pin is de-
signed to be driven from a 25 MHz 40 MHz crystal oscilla-
tor
The PLL using a charge pump and an internal loop filter
multiplies this input frequency to create a maximum output
frequency of four times the input
The device includes a TRI-STATE
control pin to disable
the outputs This feature allows for low frequency functional
testing and debugging
Also included is an EXTSEL pin to allow testing the chip via
an external source The EXTSEL pin once set to high caus-
es the External-Clock
MUX to change its input from the
output of the VCO and Counter to the external clock signal
provided via SKWTST input pin
(continued)
Features
Y
Guaranteed
400 ps pin-to-pin skew (t
OSHL
and t
OSLH
) on 1X
outputs
Y
Pentium
and PowerPC
TM
compatible
Y
g
300 ps propagation delay
Y
Output buffer of eight drivers for large fanout
Y
25 MHz 160 MHz output frequency range
Y
Outputs operating at 4X 2X 1X of the reference fre-
quency for multifrequency bus applications
Y
Selectable output frequency
Y
Internal loop filter to reduce noise and jitter
Y
Separate analog and digital V
CC
and ground pins
Y
Low frequency test mode by disabling the PLL
Y
Implemented on National's Core CMOS process
Y
Symmetric output current drive
a
30
b
30 mA I
OL
I
OH
Y
Industrial temperature of
b
40 C to
a
85 C
Y
28-pin PLCC for optimum skew performance
Y
Guaranteed 2k volts ESD protection
Connection Diagram
Pin Assignment for PLCC
TL F 11920 1
Pin Description
PLCC Package
Pin
Name
Description
1
V
CC
Digital V
CC
2
FBK IN
Feedback Input Pin
3
CLK4
4X Clock Output
4
V
CC
Digital V
CC
5
XTALIN
Crystal Oscillator Input
6
GND
Digital Ground
7
FBK OUT
Feedback Output Pin
8
V
CC
Digital V
CC
9
CLK1
l
1X Clock Output
10
GND
Digital Ground
11
CLK1
2
1X Clock Output
12
TRI-STATE
Output TRI-STATE Control
13
SKWTST
Skew Testing Pin
14
CLK1
3
1X Clock Output
15
GND
Digital Ground
16
CLK1
4
1X Clock Output
17
V
CC
Digital V
CC
18
SKWSEL
Skew Test Selector Pin
19
GNDA
Analog Ground
20
V
CCA
Analog V
CC
21
EXTSEL
External Clock MUX Selector
22
GND
Digital Ground
23
CLK1
5
1X Clock Output
24
V
CC
Digital V
CC
25
CLK1
0
1X Clock Output
26
CLK1SEL
CLK1 Multiplier Selector
27
GND
Digital Ground
28
CLK2
2X Clock Output
Pentium
is a registered trademark of Intel Corporation
PowerPC
TM
is a trademark of International Business Machines Corporation
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1996 National Semiconductor Corporation
RRD-B30M106 Printed in U S A
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CGS701A
General Description
(Continued)
CLK1SEL pin changes the output frequency of the
CLK1
0 thru CLK1
5 outputs During normal operation
when CLK1SEL pin is high these outputs are at the same
frequency as the input crystal oscillator while CLK2 and
CLK4 outputs are at twice and four times the input frequen-
cy respectively
Once CLK1SEL pin is set to a low logic level the CLK1
outputs will be at twice the input frequency the same as the
CLK2 output with CLK4 output still being at four times the
input frequency
In addition another pin is added for increasing the test ca-
pability SKWSEL pin allows testing of the counter's output
and skew of the output drivers by bypassing the VCO In this
test mode CLK4 frequency is the same as SKWTST input
frequency while CLK2 is 1 2 and CLK1 frequencies are 1 4
respectively (refer to the Truth Table) In addition CLK1SEL
functionality is also true under this test condition
Block Diagram
TL F 11920 2
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CGS701A
Truth Table
Input
Output
CLK1
EXT
EXT
SKW
SKW
TRI-STATE
CLK4
CLK2
CLK1
SEL
SEL
CLK
SEL
TST
H
L
X
L
X
H
4 x f in
2 x f in
f in
L
L
X
L
X
H
4 x f in
2 x f in
2 x f in
X
H
X
X
H
H
L
X
H
H
1 x f tst
x f tst
x f tst
L
L
X
H
H
1 x f tst
x f tst
x f tst
X
X
X
X
X
L
Z
Z
Z
Steady state phase frequency lock
Typical Application
TL F 11920 3
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CGS701A
Absolute Maximum Ratings
(Note A)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
CC
)
b
0 5V to
a
7 0V
DC Input Voltage Diode Current (I
IK
)
V
e b
0 5V
b
20 mA
V
e
V
CC
a
0 5V
a
20 mA
DC Input Voltage (V
I
)
b
0 5V to V
CC
a
0 5V
DC Output Diode Current (I
O
)
V
e b
0 5V
b
20 mA
V
e
V
CC
a
0 5V
a
20 mA
DC Output Voltage (V
O
)
b
0 5V to V
CC
a
0 5V
DC Output Source
or Sink Current (I
O
)
g
60 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
g
60 mA
Storage Temperature (T
STG
)
b
65 C to
a
150 C
Junction Temperature
150 C
Power Dissipation
(Static and Dynamic) (Note B)
1400 mW
Recommended Operating
Conditions
Supply Voltage (V
CC
)
4 5V to 5 5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Input Frequency
25 MHz 40 MHz
Operating Temperature (T
A
) SKWTST
0 C to
a
70 C
External Clock Frequency (Pin)
1 MHz 10 MHz
XTALIN Duty Cycle Range
25 75 (75 25)%
Input Rise and Fall Times (0 8V to 2 0V)
XTALIN (Pin 5)
5 ns max
All Other Inputs
10 ns max
Typical i
JA
LFM
C W
0
54
225
45
500
38
900
34
Note A
The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at
these limits The parametric values defined in the DC and AC Electrical Characteristics tables are not guaranteed at the absolute maximum ratings The
Recommended Operating Conditions will define the conditions for actual device operation
Note B
Power dissipation is calculated using 49 C W as the thermal coefficient for the PCC package at 225 LFM airflow The input frequency is assumed at 33
MHz with CLK4 at 132 MHz and CLK2 and CLK1 being at 66 MHz In addition the ambient temperature is assumed 70 C
DC Electrical Characteristics
Over recommended operating free air temperature range All typical values are measured at V
CC
e
5V T
A
e
25 C
Symbol
Parameter
V
CC
e
4 5V 5 5V
Units
Conditions
T
e
0 C to 70 C
Min
Typ
Max
V
IH
Minimum Input High Level
2 0
V
Voltage
V
IL
Maximum Input Low Level
0 8
V
Voltage
V
OH
Minimum Output High Level
V
CC
b
0 1
V
I
OUT
e b
50 mA
Voltage
V
CC
b
0 6
I
OH
e b
30 mA
V
OL
Maximum Output Low Level
0 1
V
I
OUT
e
50 mA
Voltage
0 6
I
OL
e
30 mA
I
OHD
High Level Output Current
b
50
b
110
b
170
mA
V
OH
e
V
CC
b
1 0V
I
OLD
Low Level Output Current
50
110
170
mA
V
OL
e
1 0V
I
IN
Leakage Current
b
50
50
m
A
V
IN
e
0 4V or 4 6V
I
OZL H
Output Leakage Current
C
IN
Input Capacitance
10 0
pF
I
CC
Quiescent digital
a
analog
3 0
5 0
mA
V
IN
e
V
CC
GND
Current (No Load)
I
CCT
I
CC
per TTL Input
2 5
V
IN
e
V
CC
b
2 1 GND
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CGS701A
AC Electrical Characteristics
Over recommended operating free air temperature range All typical values are measured at V
CC
e
5V T
A
e
25 C
Symbol
Parameter
V
CC
e
4 5V 5 5V
Units
Notes
F
IN
e
25 to 40 MHz
T
e
0 C to
a
70 C
C
L
e
Circuit 1
R
L
e
Circuit 1
Min
Typ
Max
t
rise
Output Rise
CLK4
0 8V to 2 6V
(Note 1 7)
CLK2
1 0V to V
CC
b
1 0V
2 0
ns
CLK1
1 0V to V
CC
b
1 0V
All
0 8V to 2 0V
1 5
t
fall
Output Fall
CLK4
2 6V to 0 8V
(Note 1 7)
CLK2
V
CC
b
1 0V to 1 0V
2 0
ns
CLK1
V
CC
b
1 0V to 1 0V
All
0 8V to 2 0V
1 5
t
SKEW
Maximum Edge-to-
a
to
a
Edges
CLK1
CLK1
400
(Note 2 7)
Edge Output Skew
a
to
a
Edges
CLK1
CLK4
1000
ps
a
to
a
Edges
CLK2
CLK4
1000
t
LOCK
Time to Lock the Output to the Synch Input
20
100
m
s
t
CYCLE
Output Duty Cycle
CLK1 Outputs
49
51
(Note 3 7)
CLK2 Output
49
51
%
CLK4 Output
35
65
J
LT
Output Jitter (Long Term)
0 3
ns
(Note 4 7)
t
PD
Propogation Delay from XTALIN to FBKOUT
b
0 3
a
0 3
ns
(Notes 2 4 5 6 7)
F
MIN
Minimum XTALIN Frequency
15
MHz
F
MAX
Maximum XTALIN Frequency
43
MHz
Note 1
t
rise
and t
fall
parameters are measured at the pin of the device
Note 2
Skew is measured at 50% of V
CC
for CLK1 and CLK2 while it is being measured at 1 4V for CLK4 Limits are guaranteed by design
Note 3
Output duty cycle is measured at V
DD
2 for CLK1 and CLK2 while it is being measured at 1 4V for CLK4 Limits are guaranteed by design
Note 4
Jitter parameter is characterized and is guaranteed by design only It measures the uncertainty of either the positive or the negative edge over 1000 cycles
It is also measured at output levels of V
CC
2 Refer to
Figure 3 for further explanation
Note 5
Measured from the ref input to any output pin The length of the feedback and XTALIN traces will impact this delay time
Note 6
This parameter includes pin-to-pin skew longterm jitter over 1000 cycles part-to-part variation as well as propagation delay thru the device
Note 7
The GNDA pins of the 701 must be as free of noise as possible for minimum jitter Separate analog ground plane is recommended for the PCB
Also the V
CCA
pin requires extra filtering to further reduce noise Ferrite beads for filtering and bypass capacitors are suggested for the V
CCA
pin
Circuit 1 Test Circuit
TL F 11920 4
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