CLC006
Serial Digital Cable Driver with Adjustable Outputs
General Description
National's Comlinear CLC006 is a monolithic, high-speed
cable driver designed for the SMPTE 259M serial digital
video data transmission standard. The CLC006 drives 75
transmission lines (Belden 8281 or equivalent) at data rates
up to 400 Mbps. Controlled output rise and fall times (650 ps
typical) minimize transition-induced jitter. The output voltage
swing, typically 1.65V, set by an accurate, low-drift internal
bandgap reference, delivers an 800 mV swing to back-
matched and terminated 75
cable. Output swing is adjust-
able from 0.7 V
p-p
to 2 V
p-p
using external resistors.
The CLC006's class AB output stage consumes less power
than other designs, 185 mW with both outputs terminated,
and requires no external bias resistors. The differential in-
puts accept a wide range of digital signals from 200 mV
p-p
to
ECL levels within the specified common-mode limits. All this
make the CLC006 an excellent general purpose high speed
driver for digital applications.
The CLC006 is powered from a single +5V or -5.2V supply
and comes in an 8-pin SOIC package.
Key Specifications
n
650 ps rise and fall times
n
Data rates to 400 Mbps
n
200 mV differential input
n
Low residual jitter (25 ps
pp
)
Features
n
No external pull-down resistors
n
Adjustable output amplitude
n
Differential input and output
n
Low power dissipation
n
Single +5V or -5.2V supply
n
Replaces GS9008 in most applications
Applications
n
Digital routers and distribution amplifiers
n
Coaxial cable driver for digital transmission line
n
Twisted pair driver
n
Serial digital video interfaces for the commercial and
broadcast industry
n
SMPTE, Sonet/SDH, and ATM compatible driver
n
Buffer applications
Connection Diagram (8-Pin SOIC)
Typical Application
DS100084-1
DS100084-3
Order Number CLC006AJE
See NS Package Number M08A
DS100084-2
August 1998
CLC006
Serial
Digital
Cable
Driver
with
Adjustable
Outputs
1998 National Semiconductor Corporation
DS100084
www.national.com
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
6V
Output Current
30 mA
Maximum Junction Temperature
+125C
Storage Temperature Range
-65C to +150C
Lead Temperature
(Soldering 10 seconds)
+300C
ESD Rating (Human Body Model)
1000V
Package Thermal Resistance
JA
Surface Mount AJE
125C/W
JC
Surface Mount AJE
105C/W
Reliability Information
Transistor count
72
MTTF
254 Mhr
Recommended Operating
Conditions
Supply Voltage Range (V
CC
V
EE
)
+4.5V to +5.5V
Electrical Characteristics
(V
CC
= 0V, V
EE
= -5V; unless otherwise specified).
Parameter
Condition
Typ
+25C
Min/Max
+25C
Min/Max
0C to
+70C
Min/Max
-40C to
+85C
Units
STATIC DC PERFORMANCE
Supply Current, Loaded
150
@
270 Mbps
(Notes 5, 7)
37
-
-
-
mA
Supply Current, Unloaded
(Note 3)
34
28/37
26/39
26/39
mA
Output HIGH Voltage (V
OH
)
(Note 3)
-1.7
-2.0/1.4
-2.0/1.4
-2.0/1.4
V
Output LOW Voltage (V
OL
)
(Note 3)
-3.3
-3.6/3.0
-3.6/3.0
-3.6/3.0
V
Input Bias Current
(Note 4)
10
30
50
50
A
Output Swing
R
EXT
=
(Note 3)
1.65
1.55/1.75
1.53/1.77
1.51/1.79
V
Output Swing
R
EXT
= 10 k
(Note 5)
1.30
-
-
-
V
Common Mode Input Range Upper Limit
-0.7
-0.8
-0.8
-0.8
V
Common Mode Input Range Lower Limit
-2.6
-2.5
-2.5
2.5
V
Minimum Differential Input Swing (Note 5)
200
200
200
200
mV
Power Supply Rejection Ratio (Note 3)
26
20
20
20
dB
AC PERFORMANCE
Output Rise and Fall Time
(Notes 3, 6, 7)
650
425/825
400/850
400/850
ps
Overshoot
(Note 5)
5
%
Propagation Delay
(Note 5)
1.0
ns
Duty Cycle Distortion
(Note 5)
50
ps
Residual Jitter
(Note 5)
25
-
-
-
ps
pp
MISCELLANEOUS PERFORMANCE
Input Capacitance
(Note 5)
1.0
pF
Output Resistance
(Note 5)
10
Output Inductance
(Note 5)
6
nH
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation.
Note 2: Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: Spec is 100% tested at +25C, sample tested at +85C.
Note 4: Spec is 100% tested at +35C at wafer probe.
Note 5: Spec is guaranteed by design.
Note 6: Measured between the 20% and 80% levels of the waveform.
Note 7: Measured with both outputs driving 150
, AC coupled at 270 Mbps.
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2
Operation
INPUT INTERFACING
The CLC006 has high impedance, emitter-follower buffered,
differential inputs. Single-ended signals may also be input.
Transmission lines supplying input signals must be properly
terminated close to the CLC006. Either A.C. or D.C. coupling
as in
Figure 2 or Figure 3 may be used. Figures 2, 4 and Fig-
ure 5 show how Thevenin-equivalent resistor networks are
used to provide input termination and biasing. The input D.C.
common-mode voltage range is 0.8V to 2.5V below the posi-
tive power supply (V
CC
). Input signals plus bias should be
kept within the specified common-mode range. For an 800
mV
P-P
input signal, typical input bias levels range from 1.2V
to 2.1V below the positive supply.
Load Type
Resistor to V
CC
(R1)
Resistor to V
EE
(R2)
ECL, 50
, 5V, V
T
=2V
82.5
124
ECL, 50
, 5.2V, V
T
=2V
80.6
133
ECL, 75
, 5V, V
T
=2V
124
187
ECL, 75
, 5.2V, V
T
=2V
121
196
800mV
P-P
, 50
, 5V, V
T
=1.6V
75.0
154
800mV
P-P
, 75
, 5V, V
T
=1.6V
110
232
800mV
P-P
, 2.2K
, 5V, V
T
=1.6V
3240
6810
DS100084-4
FIGURE 1. Input Stage
DS100084-5
FIGURE 2. AC Coupled Input
3
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Operation
(Continued)
OUTPUT INTERFACING
The CLC006's class AB output stage,
Figure 6, requires no
standing current in the output transistors and therefore re-
quires no biasing or pull-down resistors. Advantages of this
arrangement are lower power dissipation and fewer external
components. The output may be either D.C. or A.C. coupled
to the load. A bandgap voltage reference sets output voltage
levels which are compatible with F100K and 10K ECL when
correctly terminated. The outputs do not have the same out-
put voltage temperature coefficient as 10K. Therefore, noise
margins will be reduced over the full temperature range
when driving 10K ECL. Noise margins will not be affected
when interfacing to F100K since F100K is fully voltage and
temperature compensated.
DS100084-6
FIGURE 3. DC Coupled Input
DS100084-7
FIGURE 4. Single Ended 50
ECL Input
DS100084-8
FIGURE 5. Differential 50
ECL Input
DS100084-9
FIGURE 6. Output Stage
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4
Operation
(Continued)
OUTPUT AMPLITUDE ADJUSTMENT
The high and low output levels of the CLC006 are set by a
circuit shown simplified in
Figure 8. Output high and low lev-
els may be set independently with external resistor networks
connected between R
EXT-H
(pin 3), R
EXT-L
(pin 4) and the
power supplies. The resistor networks affect the high and
low output levels by changing the internally generated bias
voltages, V
H
and V
L
. The nominal high and low output levels
are V
CC
-1.7V and V
CC
-3.3V, respectively, when the pins
R
EXT-H
and R
EXT-L
are left unconnected. Though the internal
components which determine output voltage levels have ac-
curate ratios, their absolute values may be controlled only
within about
15% of nominal. Even so, without external ad-
justment, output voltages are well controlled. A final design
should accommodate the variation in externally set output
voltages due to the CLC006's part-to-part and external com-
ponent tolerances.
Output voltage swing may be reduced with the circuit shown
in
Figure 9. A single resistance chosen with the aid of the
graph,
Figure 10, is connected between pins 3 and 4. Output
voltage swing may be increased with the circuit of
Figure 11.
Figure 12 is used to estimate a value for resistor R. Note that
both of these circuits and the accompanying graphs assume
that the CLC006 is loaded with the standard 150
. Be aware
that output loading will affect the output swing and the high
and low levels. It may be necessary to empirically select re-
sistances used to set output levels when the D.C. loading on
the CLC006 differs appreciably from 150
.
DS100084-10
FIGURE 7. Differential Input DC Coupled Output
DS100084-11
FIGURE 8. Equivalent Bias Generation Circuit
5
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