CLC018
8 x 8 Digital Crosspoint Switch, 1.485 Gbps
General Description
National's Comlinear CLC018 is a fully differential 8x8 digital
crosspoint switch capable of operating at data rates exceed-
ing 1.485 Gbps per channel. Its non-blocking architecture
utilizes eight independent 8:1 multiplexers to allow each
output to be independently connected to any input and any
input to be connected to any or all outputs. Additionally, each
output can be individually disabled and set to a high-
impedance state. This TRI-STATE feature allows flexible
expansion to larger switch array sizes.
Low channel-to-channel crosstalk allows the CLC018 to pro-
vide superior all-hostile jitter of 50 ps
PP
. This excellent signal
fidelity along with low power consumption of 850 mW make
the CLC018 ideal for digital video switching plus a variety of
data communication and telecommunication applications.
The fully differential signal path provides excellent noise
immunity, and the I/Os support ECL and PECL logic levels.
In addition, the inputs may be driven single-ended or differ-
entially and accept a wide range of common mode levels
including the positive supply. Single +5V or -5V supplies or
dual +5V supplies are supported. Dual supply mode allows
the control signals to be referenced to the positive supply
(+5V) while the high-speed I/O remains ECL compatible.
The double row latch architecture utilized in the CLC018
allows switch reprogramming to occur in the background
during operation. Activation of the new configuration occurs
with a single "configure" pulse. Data integrity and jitter per-
formance on unchanged outputs are maintained during re-
configuration. Two reset modes are provided. Broadcast
reset results in all outputs being connected to input port DI0.
TRI-STATE Reset results in all outputs being disabled.
The CLC018 is fabricated on a high-performance BiCMOS
process and is available in a 64-lead plastic quad flat pack
(PQFP).
Features
n
Fully differential signal path
n
Non-Blocking
n
Flexible expansion to larger array sizes with very low
power
n
Single +5/-5V or dual
5V operation
n
TRI-STATE outputs
n
Double row latch architecture
n
64-lead PQFP package
Applications
n
Serial digital video routing:
SMPTE 259M for SD rates
SMPTE 292M for HD rates
n
Telecom/datacom switching
n
ATM SONET
Key Specifications
n
High speed:
>
1.485 Gbps
n
Low jitter:
<
50 ps
PP
for rates
<
500 Mbps
<
100 ps
PP
for rates
<
1.485 Gbps
n
Low power; 850 mW with all outputs active
n
Fast output edge speeds: 250 ps
CLC018 Block Diagram
DS100088-2
DS100088-1
July 2001
CLC01
88x8
Digital
Crosspoint
Switch,
1.485
Gbps
2001 National Semiconductor Corporation
DS100088
www.national.com
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
V
EE)
-0.3V to +6.0V
V
LL
Maximum
V
CC
+6V
V
LL
Minimum
V
CC
-0.5V
Storage Temperature Range
-65C to +150C
Lead Temp. (Soldering 4 sec.)
+260C
ESD Rating
TBD
Package Thermal Resistance
JA
64-Pin PQFP
75C/W
JC
64-Pin PQFP
15C/W
Reliability Information
Transistor Count
3000
Recommended Operating
Conditions
Supply Voltage (V
CC
V
EE
)
4.5V to 5.5V
Operating Temperature
-40C to +85C
V
LL
V
CC
or V
CC
+5V
Electrical Characteristics
(V
CC
= 0V, V
EE
= -5V, V
LL
= 0V; unless otherwise specified) (Note 4).
Parameter
Conditions
Typ
+25C
Min/Max
+25C
Min/Max
-40C to
+85C
Units
DYNAMIC PERFORMANCE
Max. Data Rate/Channel (NRZ)
(Note 5)
1.485
Gbps
Channel Jitter
Data Rate
<
500 Mbps
(Note 6)
50
ps
PP
Data Rate
<
1.485 Gbps
(Note 6)
100
ps
PP
Propagation Delay (input to output)
0.75
ns
Propagation Delay Match
(Note 7)
200
ps
Output Rise/Fall Time
(Note 8)
250
ps
Duty Cycle Distortion
(Note 9)
10
ps
CONTROL TIMING: CONFIGURATION
OA Bus to LOAD
Setup Time (T
1
)
15
ns
LOAD
to OA Bus Hold Time (T
2
)
0
ns
IA Bus, TRI to LOAD
Setup Time (T
3
)
5
ns
LOAD
to IA Bus, TRI Hold Time (T
4
)
5
ns
Min Pulse Width: (T
5
)
LOAD
10
ns
CNFG
10
ns
LOAD
to CNFG
Delay (T
6
)
0
ns
CNFG
to Valid Delay (T
7
)
20
ns
CNFG
to Output TRI-STATE
Delay (T
8
)
20
ns
CNFG
to Output Active Delay (T
9
)
70
ns
CONTROL TIMING: RESET (Note 11)
TRI to RES
Setup Time (T
10
)
5
ns
RES
to TRI Hold Time (T
11
)
5
ns
Min Pulse Width: RES (T
12
)
10
ns
RES
to TRI-STATE Mode Delay (T
13
)
20
ns
RES
to Broadcast Mode Delay (T
14
)
70
ns
STATIC PERFORMANCE
Signal I/O:
Min Input Swing, Differential
(Note 3)
150
200
200
mV
PP
Input Voltage Range Lower Limit
-2
V
Input Voltage Range Upper Limit
0.4
V
Input Bias Current
(Notes 3, 12)
1.5
0.4/3.1
0.3/3.8
A/output
Output Current
(Note 3)
10.7
8.53/12.80
7.20/14.3
mA
Output Voltage Swing
R
LOAD
= 75
800
640/960
540/1060
mV
CLC018
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2
Electrical Characteristics
(Continued)
(V
CC
= 0V, V
EE
= -5V, V
LL
= 0V; unless otherwise specified) (Note 4).
Parameter
Conditions
Typ
+25C
Min/Max
+25C
Min/Max
-40C to
+85C
Units
STATIC PERFORMANCE
Output Voltage Range Lower Limit
-2.5
V
Output Voltage Range Upper Limit
0
V
Control Inputs:
Input Voltage - HIGH
V
IH min
(Note 3)
-1
-0.5
-0.5
V
Input Voltage - LOW
V
IL max
(Note 3)
-4
-4.5
-4.5
V
Input Voltage - HIGH
V
IH min
V
LL
= +5V (Note 3)
4
4.5
4.5
V
Input Voltage - LOW
V
IL max
V
LL
= +5V (Note 3)
1
0.5
0.5
V
Input Current - HIGH
V
IH
= V
LL
(Note 3)
1
0.2/2.0
0.1/2.5
A
Input Current - LOW
V
IL
= V
LL
-5V (Note 3)
-100
-200/10
-250/15
A
MISCELLANEOUS PERFORMANCE
V
CC
Supply Current
All Outputs Active
(Notes 3, 13, 14)
157
127/202
119/217
mA
V
CC
Supply Current
All Outputs TRI-STATE
(Note 3)
7
3/11
2/12
mA
V
LL
Supply Current
V
LL
= 0V (Note 3)
2.5
1.7/3.3
1.5/3.5
mA
V
LL
Supply Current
V
LL
= +5V (Note 3)
7
mA
Input Capacitance
1.5
pF
Output Capacitance
2
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation.
Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: J-level spec. is 100% tested at +25C.
Note 4: V
LL
and all V
EE
supply pins are bypassed with 0.01 F ceramic capacitor.
Note 5: Bit error rate less than 10
-9
over 50% of the bit cell interval.
Note 6: Measured using a pseudo-random (2
23
-1 pattern) binary sequence with all other channels active with an uncorrelated signal.
Note 7: Spread in propagation delays for all input/output combinations.
Note 8: Measured between the 20% and 80% levels of the waveform.
Note 9: Difference in propagation delay for output low-to-high vs. output high-to-low transition.
Note 10: Refer to the
Configuration Timing Diagram
.
Note 11: Refer to the
Reset Timing Diagram
.
Note 12: The bias current for high speed data input depends on the number of data outputs that are selecting that input.
Note 13: The V
CC
supply current is a function of the number of active data outputs. I
VCC
18*N + 7 mA where N is an integer from 0 to 8.
Note 14: I
VEE
= I
VCC
+ I
VLL
.
CLC018
www.national.com
3
Typical Performance Characteristics
DS100088-3
DS100088-4
DS100088-5
DS100088-6
DS100088-7
DS100088-8
CLC018
www.national.com
4
Connection Diagram
Pin Descriptions
POWER PINS
V
CC
is the most positive rail for the data path. When the data
levels are ECL compatible, then V
CC
should be connected to
GND. For PECL data (+5V referenced ECL), V
CC
is con-
nected to the +5V supply. Please refer to the device opera-
tion section in this datasheet for recommendations on the
bypassing and ground/power plane requirements of this de-
vice.
V
EE
is the most negative rail for the data path. When the data
levels are ECL compatible, then V
EE
is connected to a -5.2V
power supply. For PECL data (+5V referenced ECL), V
EE
is
connected to GND.
V
LL
is the logic-level power supply. If the control signals are
referenced to +5V, V
LL
is connected to a +5V supply. If
control signals are ECL compatible, V
LL
is connected to
GND.
DATA INPUT PINS
DI0 and DI0 through DI7 and D17 are the data input pins to
the CLC018. Depending upon how the Power pins are con-
nected (please refer to the Power Pin section above) the
data may be either differential ECL, or differential PECL. To
drive the CLC018 inputs with a single-ended signal, please
refer to the section "Using Single-Ended Data" in the OP-
ERATION section of this datasheet.
DATA OUTPUT PINS
DO0 and DO0 through DO7 and DO7 are the data output
pins of the CLC018. The CLC018 outputs are differential
current outputs which can be converted to ECL or PECL
compatible outputs through the use of load resistors. Please
refer to the "Output Interfacing" paragraph in the OPERA-
TION section of this datasheet for more details.
CONTROL PINS
IA2, IA1 and IA0 are the three bit input selection address
bus. The input port to be addressed is placed on this bus.
IA2 is the Most Significant Bit (MSB). If input port 6 is to be
addressed, IA2, IA1, IA0 should have 1, 1, 0 asserted on
them. The IA bus should be driven with CMOS levels, if V
LL
is +5V. These levels are thus +5V referenced (standard
CMOS). If V
LL
is connected to GND, the input levels are
referenced to the -5V and GND supplies.
OA2, OA1 and OA0 are the output selection address bus.
The output port selected by the OA bus is connected to the
input port selected on the IA bus when the data is loaded into
the configuration registers. OA2 is the MSB. If OA2, OA1,
OA0 are set to 0, 0, 1; then output port 1 will be selected.
CS is an active-high chip select input. When CS is high, the
RES, LOAD, and CNFG pins will be enabled.
LOAD is the latch control for the LOAD register. When LOAD
is high, the load register is transparent. Outputs follow the
state of the IA bus, and are presented to the inputs of the
Configuration register selected by the OA bus. When LOAD
is low, the outputs of the Load register are latched.
RES is the reset control of the configuration and load regis-
ters. A high-going pulse on the RES pin programs the switch
matrix to one of two possible states: with TRI low, all outputs
are connected to input #0; with TRI high, all outputs are put
in TRI-STATE condition.
TRI will program the selected output to be in a high imped-
ance or TRI-STATE condition. To place an output in
TRI-STATE, assert a logic-high level on the TRI input when
the desired input and output addresses are asserted on the
respective address inputs and strobe the LOAD input as
depicted in the "Configuration Truth Table". To enable an
output, assert a logic-low level on the TRI input together with
the appropriate addresses and strobe the LOAD input as
previously described.
CNFG is the configuration register latch control. When
CNFG is high the Configuration register is made transparent,
and the switch matrix is set to the state loaded into the Load
registers. When CNFG is low, the state of the switch matrix
is latched.
DS100088-9
Order Number CLC018AJVJQ
See NS Package Number VJQ64A
CLC018
www.national.com
5
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