CLC020
SMPTE 259M Digital Video Serializer with Integrated
Cable Driver
General Description
The CLC020 SMPTE 259M Digital Video Serializer with
Integrated Cable Driver is a monolithic integrated circuit that
encodes, serializes and transmits bit-parallel digital data
conforming to SMPTE 125M and SMPTE 267M component
video and SMPTE 244M composite video standards. The
CLC020 can also serialize other 8 or 10-bit parallel data. The
CLC020 operates at data rates from below 100 Mbps to over
400 Mbps. The serial data clock frequency is internally gen-
erated and requires no external frequency setting compo-
nents, trimming or filtering
*
. Functions performed by the
CLC020 include: parallel-to-serial data conversion, data en-
coding using the polynomial (X
9
+X
4
+1), data format conver-
sion from NRZ to NRZI, parallel data clock frequency multi-
plication and encoding with the serial data, and coaxial cable
driving. Input for sync (TRS) detection disabling and a PLL
lock detect output are provided. The CLC020 has an exclu-
sive built-in self-test (BIST) and video test pattern generator
(TPG) with 4 component video test patterns, reference
black, PLL and EQ pathologicals and modified colour bars, in
4:3 and 16:9 raster and both NTSC and PAL formats
*
.
Separate power pins for the output driver, VCO and the
digital logic improve power supply rejection, output jitter and
noise performance.
The CLC020 is the ideal complement to the CLC011B
SMPTE 259M Serial Digital Video Decoder, CLC014 Active
Cable Equalizer, CLC016 Data Retiming PLL (clock-data
separator), CLC018 8X8 Digital Crosspoint Switch and
CLC006 or CLC007 Cable Drivers, for a complete parallel-
serial-parallel, high-speed data processing and transmission
system.
The CLC020 is powered from a single 5V supply. Power
dissipation is typically 235 mW including two 75
back-
matched output loads. The device is packaged in a JEDEC
28-lead PLCC.
Features
n
SMPTE 259M serial digital video standard compliant
n
No external serial data rate setting or VCO filtering
components required
*
n
Built-in self-test (BIST) and video test pattern generator
(TPG) with 16 internal patterns
*
n
Supports all NTSC and PAL standard component and
composite serial video data rates
n
HCMOS/TTL-compatible data and control inputs and
outputs
n
75
ECL-compatible, differential, serial cable-driver
outputs
n
Fast VCO lock time:
<
75 s
n
Single +5V TTL or -5V ECL supply operation
n
Low power: 235 mW typical
n
28-lead PLCC package
n
Commercial temperature range 0C to +70C
Applications
n
SMPTE 259M parallel-to-serial digital video interfaces
for:
-- Video cameras
-- VTRs
-- Telecines
-- Video test pattern generators and digital video test
equipment
n
Non-SMPTE video applications
n
Other high data rate parallel/serial video and data
systems
*
Patents applications made or pending.
Typical Application
10091712
July 2003
CLC020
SMPTE
259M
Digital
V
ideo
Serializer
with
Integrated
Cable
Driver
2003 National Semiconductor Corporation
DS100917
www.national.com
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
DD
-V
SS
)
6.0V
CMOS/TTL Input Voltage (V
I
)
-0.5V to (V
DD
+ 0.5V)
CMOS/TTL Output Voltage (V
O
)
-0.5V to (V
DD
+ 0.5V)
CMOS/TTL Input Current (single input)
V
I
= V
SS
-0.5V
-5 mA
V
I
= V
DD
+0.5V
+5 mA
Input Current, Other Inputs
1 mA
CMOS/TTL Output Source/Sink Current
10 mA
SDO Output Source Current
20 mA
Package Thermal Resistance
JA
28-lead PLCC
85C/W
JC
28-lead PLCC
35C/W
Storage Temp. Range
-65C to +150C
Junction Temperature
+150C
Lead Temperature (Soldering 4 Sec)
+260C
ESD Rating (HBM)
>
2.5 kV
ESD Rating (MM)
>
200 V
Transistor Count
33,400
Recommended Operating
Conditions
Supply Voltage (V
DD
-V
SS
)
5.0V
10%
CMOS/TTL Input Voltage
V
SS
to V
DD
P
CLK
Frequency Range
10 to 40MHz
P
CLK
Duty Cycle
45 to 55%
D
N
and P
CLK
Rise/Fall Time
1.0 to 3.0 ns
Maximum DC Bias on SDO pins
3.0V
10%
Operating Free Air Temperature (T
A
)
0C to +70C
DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3).
Symbol
Parameter
Conditions
Reference
Min
Typ
Max
Units
V
IH
Input Voltage High Level
D0 through D9,
P
CLK
, TPG_EN
and Sync.
Detect Enable
2.0
V
DD
V
V
IL
Input Voltage Low Level
V
SS
0.8
V
I
IH
Input Current High Level
V
IH
= V
DD
+40
+60
A
I
IL
Input Current Low Level
V
IL
= V
SS
-1
-20
A
V
OH
CMOS Output Voltage
High Level
I
OH
= -10 mA
Lock Detect,
Test Out
2.4
4.7
V
DD
V
V
OL
CMOS Output Voltage
Low Level
I
OL
= +10 mA
0.0
0.3
V
SS
+ 0.5V
V
V
SDO
Serial Driver Output
Voltage
R
L
= 75
1%,
R
REF
= 1.69 k
1%,
Figure 2
SDO, SDO
700
800
900
mV
P-P
I
DD
Power Supply Current,
Total
R
L
= 75
1%,
R
REF
= 1.69 k
1%,
P
CLK
= 27 MHz, Figure 2,
NTSC Colour Bar Pattern
47
60
mA
AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).
Symbol
Parameter
Conditions
Reference
Min
Typ
Max
Units
BR
SDO
Serial data rate
R
L
= 75
, AC coupled, (Note 5)
SDO, SDO
100
400
Mbps
F
PCLK
Reference Clock
Input Frequency
P
CLK
10
40
MHz
Reference Clock Duty
Cycle
P
CLK
45
50
55
%
t
r
, t
f
Rise time, Fall time
10%90%
D
N
, P
CLK
1.0
1.5
3.0
ns
t
j
Serial output jitter
270 Mbps,Figure 2, (Note 6)
SDO, SDO
220
ps
P-P
t
jit
Serial output jitter
(Notes 4, 5)
100
200
ps
P-P
t
r
, t
f
Rise time, Fall time
20%80%, (Notes 4, 5)
500
800
1500
ps
Output overshoot
1
%
t
LOCK
Lock time
270 Mbps, (Notes 5, 7)
75
s
t
SU
Setup time
Figure 3
D
N
to P
CLK
3
2
ns
CLC020
www.national.com
3
AC Electrical Characteristics
(Continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).
Symbol
Parameter
Conditions
Reference
Min
Typ
Max
Units
t
HLD
Hold time
Figure 3
D
N
from P
CLK
1.5
1
ns
L
GEN
Output inductance
(Note 4)
SDO, SDO
6
nH
R
GEN
Output resistance
(Note 4)
25k
Note 1: "Absolute Maximum Ratings" are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of
these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of "Electrical Characteristics"
specifies acceptable device operating conditions.
Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated referenced to V
SS
= 0V.
Note 3: Typical values are stated for V
DD
= +5.0V and T
A
= +25C.
Note 4: Specification is guaranteed by design.
Note 5: R
L
= 75
, AC-coupled @ 270 M
bps
, R
REF
= 1.69 k
1%, See Test Loads and Figure 2.
Note 6: CLC020 mounted in the SD020EVK board, configured in BIST mode (NTSC color bars) with P
CLK
= 27MHz derived from Tektronix TG2000 black-burst
reference. Timing jitter measured with Tektronix VM700T using jitter measurement FFT mode, frame rate, 1kHz filter bandwidth, Hanning window.
Note 7: Measured from rising-edge of first P
CLK
cycle until Lock Detect output goes high (true).
Test Loads
10091703
All resistors in Ohms, 1% tolerance.
FIGURE 1. Test Loads
CLC020
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4
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