TL DD12532
COP87L88GG
8-Bit
One-Time
Programmable
(OTP)
Microcontroller
with
UART
and
Three
Multi-Function
Timers
PRELIMINARY
August 1996
COP87L88GG
8-Bit One-Time Programmable (OTP) Microcontroller
with UART and Three Multi-Function Timers
General Description
The COP87L88GG OTP microcontroller is a member of the
COP8
TM
feature family using an 8-bit core architecture It is
pin and software compatible to the mask ROM COP888GG
product family
(Continued)
Features
Y
Full duplex UART
Y
Three 16-bit timers
each with two 16-bit registers
supporting
Processor independent PWM mode
External event counter mode
Input capture mode
Y
16 kbytes on-board OTP EPROM with security feature
Y
512 bytes on-board RAM
Additional Peripheral Features
Y
Idle Timer
Y
Multi-Input Wakeup (MIWU) with optional interrupts (8)
Y
WATCHDOG
TM
and clock monitor logic
Y
Two analog comparators
Y
MICROWIRE PLUS
TM
serial I O
I O Features
Y
Memory mapped I O
Y
Software selectable I O options (TRI-STATE
output
push-pull output weak pull-up input high impedance in-
put)
Y
Schmitt trigger inputs on ports G and L
Y
Packages
40 DIP with 36 I O pins
44 PLCC with 40 I O pins
CPU Instruction Set Features
Y
1 ms instruction cycle time
Y
Fourteen multi-source vectored interrupts servicing
External interrupt with selectable edge
Idle Timer T0
Three Timers (each with 2 interrupts)
MICROWIRE PLUS
Multi-Input Wakeup
Software trap
UART (2)
Default VIS (default interrupt)
Y
Versatile and easy to use instruction set
Y
8-bit Stack Pointer SP
(stack in RAM)
Y
Two 8-bit register indirect data memory pointers
(B and X)
Fully Static CMOS
Y
Two power saving modes HALT and IDLE
Y
Single supply operation 2 7V 5 5V
Y
Temperature ranges
b
40 C to
a
85 C
Development Support
Y
Emulation device for the COP888GG and COP888HG
Y
Real time emulation and full program debug offered by
MetaLink Development System
Block Diagram
TL DD 12532 1
FIGURE 1 Block Diagram
TRI-STATE
is a registered trademark of National Semiconductor Corporation
MICROWIRE PLUS
TM
COP8
TM
and WATCHDOG
TM
are trademarks of National Semiconductor Corporation
PC
is a registered trademark of International Business Machines Corporation
iceMASTER
TM
is a trademark of MetaLink Corporation
C1996 National Semiconductor Corporation
RRD-B30M96 Printed in U S A
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General Description
(Continued)
It is a fully static part fabricated using double-metal silicon
gate microCMOS technology Features include an 8-bit
memory mapped architecture MICROWIRE PLUS serial
I O three 16-bit timer counters supporting three modes
(Processor Independent PWM generation External Event
counter and Input Capture mode capabilities) full duplex
UART two comparators and two power saving modes
(HALT and IDLE) both with a multi-sourced wakeup inter-
rupt capability This multi-sourced interrupt capability may
also be used independent of the HALT or IDLE modes
Each I O pin has software selectable configurations The
devices operate over a voltage range of 2 7V to 5 5V High
throughput is achieved with an efficient regular instruction
set operating at a maximum rate of 1 ms per instruction
Connection Diagrams
Plastic Chip Carrier
TL DD 12532 2
Top View
Order Number COP87L88GGV-XE
See NS Package Number V44A
Dual-In-Line Package
TL DD 12532 3
Top View
Order Number COP87L88GGN-XE
See NS Package Number N40A
Note
-X Crystal Oscillator
-E Halt Enable
FIGURE 2 Connection Diagrams
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2
Connection Diagrams
(Continued)
Pinouts for 40- and 44-Pin Packages
Port
Type
Alt Fun
Alt Fun
40-Pin
44-Pin
Pack
Pack
L0
I O
MIWU
17
17
L1
I O
MIWU
CKX
18
18
L2
I O
MIWU
TDX
19
19
L3
I O
MIWU
RDX
20
20
L4
I O
MIWU
T2A
21
25
L5
I O
MIWU
T2B
22
26
L6
I O
MIWU
T3A
23
27
L7
I O
MIWU
T3B
24
28
G0
I O
INT
35
39
G1
WDOUT
36
40
G2
I O
T1B
37
41
G3
I O
T1A
38
42
G4
I O
SO
3
3
G5
I O
SK
4
4
G6
I
SI
5
5
G7
I CKO
HALT Restart
6
6
D0
O
25
29
D1
O
26
30
D2
O
27
31
D3
O
28
32
I0
I
9
9
I1
I
COMP1IN
b
10
10
I2
I
COMP1IN
a
11
11
I3
I
COMP1OUT
12
12
I4
I
COMP2IN
b
13
13
I5
I
COMP2IN
a
14
14
I6
I
COMP2OUT
15
15
I7
I
16
16
D4
O
29
33
D5
O
30
34
D6
O
31
35
D7
O
32
36
C0
I O
39
43
C1
I O
40
44
C2
I O
1
1
C3
I O
2
2
C4
I O
21
C5
I O
22
C6
I O
23
C7
I O
24
V
CC
8
8
GND
33
37
CKI
7
7
RESET
34
38
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Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
CC
)
7V
Voltage at Any Pin
b
0 3V to V
CC
a
0 3V
Total Current into V
CC
Pin (Source)
100 mA
Total Current out of GND Pin (Sink)
110 mA
Storage Temperature Range
b
65 C to
a
140 C
Note
Absolute maximum ratings indicate limits beyond
which damage to the device may occur DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings
DC Electrical Characteristics
b
40 C
s
T
A
s
a
85 C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Operating Voltage
2 7
5 5
V
Power Supply Ripple (Note 1)
Peak-to-Peak
0 1 V
CC
V
Supply Current (Note 2)
CKI
e
10 MHz
V
CC
e
5 5V t
c
e
1 ms
14
mA
CKI
e
4 MHz
V
CC
e
4 0V t
c
e
2 5 ms
4 5
mA
HALT Current (Note 3)
V
CC
e
5 5V CKI
e
0 MHz
12
m
A
V
CC
e
4 0V CKI
e
0 MHz
8
m
A
IDLE Current (Note 2)
CKI
e
10 MHz
V
CC
e
5 5V t
c
e
1 ms
3 5
mA
CKI
e
1 MHz
V
CC
e
4 0V t
c
e
10 ms
0 7
mA
Input Levels
RESET
Logic High
0 8 V
CC
V
Logic Low
0 2 V
CC
V
CKI (External and Crystal Osc Modes)
Logic High
0 7 V
CC
V
Logic Low
0 2 V
CC
V
All Other Inputs
Logic High
0 7 V
CC
V
Logic Low
0 2 V
CC
V
Hi-Z Input Leakage
V
CC
e
5 5V
b
2
a
2
m
A
Input Pullup Current
V
CC
e
5 5V
40
250
m
A
G and L Port Input Hysteresis (Note 7)
0 35 V
CC
V
Output Current Levels
D Outputs
Source
V
CC
e
4 5V V
OH
e
3 3V
0 4
mA
V
CC
e
2 7V V
OH
e
1 8V
0 2
mA
Sink (Note 4)
V
CC
e
4 5V V
OL
e
1V
10
mA
V
CC
e
2 7V V
OL
e
0 4V
2 0
mA
All Others
Source (Weak Pull-Up Mode)
V
CC
e
4 5V V
OH
e
2 7V
10
100
m
A
V
CC
e
2 7V V
OH
e
1 8V
2 5
33
m
A
Source (Push-Pull Mode)
V
CC
e
4 5V V
OH
e
3 3V
0 4
mA
V
CC
e
2 7V V
OH
e
1 8V
0 2
mA
Sink (Push-Pull Mode)
V
CC
e
4 5V V
OL
e
0 4V
1 6
mA
V
CC
e
2 7V V
OL
e
0 4V
0 7
mA
TRI-STATE Leakage
V
CC
e
5 5V
b
2
a
2
m
A
Allowable Sink Source Current per Pin
(Note 6)
D Outputs (Sink)
15
mA
All others
3
mA
Maximum Input Current
g
200
mA
without Latchup (Note 5)
RAM Retention Voltage V
r
500 ns Rise
2
V
and Fall Time (min)
Input Capacitance
7
pF
Load Capacitance on D2
1000
pF
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AC Electrical Characteristics
b
40 C
s
T
A
s
a
85 C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (t
c
)
Crystal Resonator
2 7V
s
V
CC
s
4 5V
2 5
DC
m
s
4 5V
s
V
CC
s
5 5V
1
DC
m
s
R C Oscillator
2 7V
s
V
CC
s
4 5V
7 5
DC
m
s
4 5V
s
V
CC
s
5 5V
3
DC
m
s
Inputs
t
SETUP
4 5V
s
V
CC
s
5 5V
200
ns
2 7V
s
V
CC
s
4 5V
500
ns
t
HOLD
4 5V
s
V
CC
s
5 5V
60
ns
2 7V
s
V
CC
s
4 5V
150
ns
Output Propagation Delay (Note 6)
R
L
e
2 2k C
L
e
100 pF
t
PD1
t
PD0
SO SK
4 5V
s
V
CC
s
5 5V
0 7
m
s
2 7V
s
V
CC
s
4 5V
1 75
m
s
All Others
4 5V
s
V
CC
s
5 5V
1 0
m
s
2 7V
s
V
CC
s
4 5V
2 5
m
s
MICROWIRE Setup Time (t
UWS
)
V
CC
t
4 5V
20
ns
MICROWIRE Hold Time (t
UWH
)
V
CC
t
4 5V
56
ns
MICROWIRE Output Propagation Delay (t
UPD
)
V
CC
t
4 5V
220
ns
Input Pulse Width (Note 7)
Interrupt Input High Time
1 0
t
c
Interrupt Input Low Time
1 0
t
c
Timer 1 2 3 Input High Time
1 0
t
c
Timer 1 2 3 Input Low Time
1 0
t
c
Reset Pulse Width
1 0
m
s
t
c
e
Instruction Cycle Time
Note 1
Maximum rate of voltage change must be
k
0 5 V ms
Note 2
Supply and IDLE currents are measured with CKI driven with a square wave Oscillator CKO driven 180 out of phase with CKI inputs connected to V
CC
and outputs driven low but not connected to a load
Note 3
The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations by bringing CKI high Test Conditions All inputs tied to V
CC
L and G
ports in the TRI-STATE mode and tied to ground all outputs low and tied to ground The clock monitor is disabled
Note 4
The user must guarantee that D2 pin does not source more than 10 mA during RESET If D2 sources more than 10 mA during reset the device will go into
programming mode
Note 5
Pins G6 and RESET are designed with a high voltage input network These pins allow input voltages
l
V
CC
and the pins will have sink current to V
CC
when
biased at voltages
l
V
CC
(the pins do not have source current when biased at a voltage below V
CC
) The effective resistance to V
CC
is 750X (typical) These two
pins will not latch up The voltage at the pins must be limited to
k
14V WARNING Voltages in excess of 14V will cause damage to the pins This warning
excludes ESD transients
Note 6
The output propagation delay is referenced to the end of the instruction cycle where the output change occurs
Note 7
Parameter characterized but not tested
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