TL DD12065
COP888GW
8-Bit
Microcontroller
with
Pulse
Train
Generators
and
Capture
Modules
PRELIMINARY
September 1996
COP888GW
8-Bit Microcontroller with Pulse Train Generators
and Capture Modules
General Description
The COP888 family of microcontrollers uses an 8-bit single
chip core architecture fabricated with National Semiconduc-
tor's M
2
CMOS
TM
process technology The COP888GW is a
member of this expandable 8-bit core processor family of
microcontrollers It is a fully static part fabricated using dou-
ble-metal silicon gate microCMOS technology
Features include an 8-bit memory mapped architecture MI-
CROWIRE PLUS serial I O two 16-bit timer counters sup-
porting three modes (Processor Independent PWM genera-
tion External Event counter and Input Capture mode capa-
bilities) four independent 16-bit pulse train generators with
16-bit prescalers two independent 16-bit input capture
modules with 8-bit prescalers multiply and divide functions
full duplex UART and two power savings modes (HALT and
IDLE) both with a multi-sourced wake up interrupt capabili-
ty This multi-sourced interrupt capability may also be used
independent of the HALT or IDLE modes
Each I O pin has software selectable configurations The
devices operate over a voltage range of 2 5V 6V High
throughput is achieved with an efficient regular instruction
set operating at a maximum of 1 ms per instruction rate The
device has low EMI emissions Low radiated emissions are
achieved by gradual turn-on output drivers and internal I
CC
filters on the chip logic and crystal oscillator The device is
available in 68-pin PLCC package
Key Features
Y
Two 16-bit input capture modules with 8-bit prescalers
Y
Four Pulse Train Generators with 16-bit prescalers
Y
Full duplex UART
Y
Two 16-bit timers each with two 16-bit registers
supporting
Processor independent PWM mode
External event counter mode
Input capture mode
Y
Quiet design (low radiated emissions)
Y
16 kbytes on-board ROM
Y
512 bytes on-board RAM
Additional Peripheral Features
Y
Idle Timer
Y
Multi-Input Wake-Up (MIWU) with optional interrupts (8)
Y
MICROWIRE PLUS
TM
serial I O
I O Features
Y
Memory mapped I O
Y
Software selectable I O options (TRI-STATE
Output
Push-Pull Output Weak Pull-Up Input High Impedance
Input)
Y
Schmitt trigger inputs on port G
Y
Package
68-pin PLCC
CPU Instruction Set Features
Y
1 ms instruction cycle time
Y
Fourteen multi-source vectored interrupts servicing
External Interrupt with selectable edge
Idle Timer T0
Two Timers (each with 2 interrupts)
MICROWIRE PLUS
Multi-Input Wake-Up
Software Trap
UART (2)
Capture Timers
Counters (one vector for all four counters)
Default VIS (default interrupt)
Y
Versatile and easy-to-use instruction set
Y
8-bit Stack Pointer SP
(stack in RAM)
Y
Two 8-bit register indirect data memory pointers
(B and X)
Fully Static CMOS
Y
Two power saving modes HALT and IDLE
Y
Low current drain (typically
k
1 mA)
Y
Single supply operation 2 5V 5 5V
Y
Temperature range
b
40 C to
a
85 C
Development Support
Y
Emulation and OTP device
Y
Real time emulation and full program debug offered by
MetaLink's Development System
TRI-STATE
is a registered trademark of National Semiconductor Corporation
M
2
CMOS
TM
MICROWIRE PLUS
TM
COPS
TM
MICROWIRE
TM
and WATCHDOG
TM
are trademarks of National Semiconductor Corporation
IBM
PC
PC-AT
and PC XT
are registered trademarks of International Business Machines Corporation
iceMASTER
TM
is a trademark of MetaLink Corporation
C1996 National Semiconductor Corporation
RRD-B30M106 Printed in U S A
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Block Diagram
TL DD 12065 1
FIGURE 1 COP888GW Block Diagram
Connection Diagram
TL DD 12065 2
Top View
Order Number COP888GW-XXX V
See NS Package Number V68A
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2
Absolute Maximum Ratings
(Note)
SuppIy Voltage (V
CC
)
7V
Voltage at Any Pin
b
0 3V to V
CC
a
0 3V
Total Current into V
CC
Pin (Source)
100 mA
Total Current out of GND Pin (Sink)
110 mA
Storage Temperature Range
b
65 C to
a
150 C
Note
Absolute maximum ratings indicate limits beyond
which damage to the device may occur DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings
DC Electrical Characteristics
COP888GW
b
40 C
s
T
A
s
a
85 C unless otherwise specified
Parameter
ConditIons
Min
Typ
Max
UnIts
Operating Voltage
2 5
6 0
V
Power Supply Ripple (Note 1)
Peak-to-Peak
0 1 V
CC
V
Supply Current (Note 2)
CKI
e
10 MHz
V
CC
e
6V t
c
e
1 ms
10
mA
CKI
e
4 MHz
V
CC
e
2 5V t
c
e
2 5 ms
1 7
mA
HALT Current (Note 3)
V
CC
e
6V CKI
e
0 MHz
k
1
10
m
A
IDLE Current
CKI
e
10 MHz
V
CC
e
6V
1 7
mA
CKI
e
4 MHz
V
CC
e
2 5V
0 4
mA
Input Levels (V
IH
V
IL
)
RESET CKI
Logic High
0 8 V
CC
V
Logic Low
0 2 V
CC
V
All Other Inputs
Logic High
0 7 V
CC
V
Logic Low
0 2 V
CC
V
Hi-Z Input Leakage
V
CC
e
6V
b
2
a
2
m
A
Input Pullup Current
V
CC
e
6V V
IN
e
0V
b
40
b
250
m
A
G Port Input Hysteresis
(Note 6)
0 05 V
CC
0 35 V
CC
V
Output Current Levels
D Outputs
Source
V
CC
e
4V V
OH
e
3 3V
b
0 4
mA
V
CC
e
2 5V V
OH
e
1 8V
b
0 2
mA
Sink
V
CC
e
4V V
OL
e
1V
10
mA
V
CC
e
2 5V V
OL
e
0 4V
2 0
mA
All Others
Source (Weak Pull-Up Mode)
V
CC
e
4V V
OH
e
2 7V
b
10
b
100
m
A
V
CC
e
2 5V V
OH
e
1 8V
b
2 5
b
33
m
A
Source (Push-Pull Mode)
V
CC
e
4V V
OH
e
3 3V
b
0 4
mA
V
CC
e
2 5V V
OH
e
1 8V
b
0 2
mA
Sink (Push-Pull Mode)
V
CC
e
4V V
OL
e
0 4V
1 6
mA
V
CC
e
2 5V V
OL
e
0 4V
0 7
mA
TRI-STATE Leakage
V
CC
e
6 0V
b
2
a
2
m
A
Allowable Sink Source
Current per Pin
D Outputs (Sink)
15
mA
All others
3
mA
Maximum Input Current
Room Temp
g
200
mA
without Latchup (Note 4 6)
RAM Retention Voltage V
R
(Note 5)
500 ns Rise and Fall Time (min)
2
V
Input Capacitance
(Note 6)
7
pF
Load Capacitance on D2
(Note 6)
1000
pF
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3
AC Electrical Characteristics
COP888GW
b
40 C
s
T
A
s
a
85 C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (t
c
)
Crystal Resonator
2 5V
s
V
CC
k
4V
2 5
DC
m
s
Ceramic
V
CC
t
4V
1 0
DC
m
s
CKI Clock Duty Cycle (Note 5)
f
e
Max
40
60
%
Rise Time (Note 5)
f
e
10 MHz Ext Clock
5
m
s
Fall Time (Note 5)
f
e
10 MHz Ext Clock
5
m
s
Inputs
t
SETUP
V
CC
t
4V
200
ns
2 5V
s
V
CC
k
4V
500
ns
t
HOLD
V
CC
t
4V
60
ns
2 5V
s
V
CC
k
4V
150
ns
Output Propagation Delay (Note 8)
R
L
e
2 2k C
L
e
100 pF
t
PD1
t
PD0
SO SK
V
CC
t
4V
0 7
m
s
2 5V
s
V
CC
k
4V
1 8
m
s
All Others
V
CC
t
4V
1
m
s
2 5V
s
V
CC
k
4V
2 5
m
s
MICROWIRE
TM
Setup Time (t
UWS
) (Note 6)
V
CC
t
4V
20
ns
MICROWIRE Hold Time (t
UWH
) (Note 6)
V
CC
t
4V
56
ns
MICROWIRE Output Propagation Delay (t
UPD
)
V
CC
t
4V
220
ns
Input Pulse Width (Note 7)
Interrupt Input High Time
1
t
c
Interrupt Input Low Time
1
t
c
Timer 1 2 Input High Time
1
t
c
Timer 1 2 Input Low Time
1
t
c
Capture Timer High Time
1
CKI
Capture Timer Low Time
1
CKI
Reset Pause Width
1
t
c
Note 1
Maximum rate of voltage change to be defined
Note 2
Supply current is measured after running 2000 cydes with a square wave CKI input CKO open inputs at rails and outputs open
Note 3
The HALT mode will stop CKI from oscillatng Test conditions All inputs tied to V
CC
L C E F and G port I O's configured as outputs and programmed
low and not driving a load D outputs programmed low and not driving a load Parameter refers to HALT mode entered via setting bit 7 of the G Port data register
Part will pull up CKI during HALT in crystal clock mode
Note 4
Pins G6 and RESET are designed with a high voltage input network These pins allow input voltages greater than V
CC
and the pins will have sink current to
V
CC
when biased at voltages greater than V
CC
(the pins do not have source current when biased at a voltage below V
CC
) The effective resistance to V
CC
is 750X
(typical) These two pins will not latch up The voltage at the pins must be limited to less than 14 volts WARNING Voltages in excess of 14 volts will cause damage
to the pins This warning excludes ESD transients
Note 5
Condition and parameter valid only for part in HALT mode
Note 6
Parameter characterized but not tested
Note 7
t
c
e
Instruction Cycle Time
Note 8
The output propagation delay is referenced to the end of the instruction cycle where the output change occurs
TL DD 12065 3
FIGURE 2 MICROWIRE PLUS Timing
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4
Typical Performance Characteristics
b
40 C
s
T
A
s
a
85 C
Port D Source Current
TL DD 12065 23
Port D Sink Current
TL DD 12065 24
Ports C G L E F Source Current
TL DD 12065 25
Ports C G L E F Sink Current
TL DD 12065 26
Ports C G L E F Weak Pull-Up Source Current
TL DD 12065 27
Dynamic
I
DD
vs V
CC
TL DD 12065 28
Idle
I
DD
vs V
CC
TL DD 12065 29
HALT
I
DD
vs V
CC
TL DD 12065 30
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