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2000 National Semiconductor Corporation
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General Description
The National Semiconductor
GeodeTM CS4103 is a three
port 400 Mbit/sec IEEE 1394 Physical Layer (PHY) device.
The CS4103 complies to revision 2.0 of the P1394a specifi-
cation. The device is a three port implementation of a reus-
able cell design scalable from one to sixteen ports.
The CS4103 supports all of the P1394a enhancements
including connection debounce, arbitrated reset, ack-accel-
erated arbitration, fly-by concatenation, multi-speed packet
concatenation, PHY pinging, priority arbitration, and Sus-
pend/Resume operation. It also implements the standard
PHY-Link interface defined in IEEE specification 1394-1995
and updated in the P1394a specification for direct connec-
tion with the Geode CS4210 IEEE 1394 Open Host Con-
troller Interface (OHCI) device. The interface can operate in
either direct or isolated mode and supports single capacitor
isolation with bus hold inputs.
The CS4103 provides a complete PHY solution including
all bias generation, differential line drivers and receivers,
single ended comparators for speed signaling, speed sig-
naling current sources, bias detect, and connect detect cir-
cuitry per port. It includes data and strobe encoding/
decoding functions as well as a re-time FIFO to synchro-
nize the receive data to the local clock domain. The
CS4103 can receive and respond to all the PHY packet
types defined in revision 2.0 of the P1394a specification. It
also supports Suspend and Resume port states and con-
nect detect functions.
The CS4103 generates the internal clocks and the Link
SCLK (System Clock) based on a 24.576 MHz external
crystal or a 24.576 MHz clock input. The CS4103 operates
from a single 3.3V supply and supports transfers at 98.304,
196.608, and 393.216 Mbit/sec, (usually referred to as 100,
200, and 400 Mbit/sec respectively).
Features
IEEE 1394 Physical Layer Device (PHY) compliant with
revision 2.0 of P1394a including all enhancements
Scalable design from one to sixteen ports
Supports data rates of 100, 200, and 400 Mbit/sec
Single 3.3V supply operation
Internal PLL generates SCLK and all internal clocks
from a single 24.576 MHz crystal or clock
Includes Cable Power Sense comparator for cable
power monitoring
Compatible with the Geode CS4210 OHCI Controller
and other IEEE 1394 OHCI devices
Supports the isolated PHY-Link interface compliant with
1394-1995 and P1394a specifications
Single capacitor bus hold isolation\
Power saving modes
80-pin TQFP (Thin Quad Flat Pack)
System Block Diagram
GeodeTM CS4210
IEEE 1394
OHCI Controller
GeodeTM CS4103
P1394a
Physical Layer
EEPROM
I
2
C Interface
PCI Interface
PHY-Link Interface
PCI Bus
IEEE 1394
Cable
Connectors
July 2000
GeodeTM CS4103
IEEE P1394a Physical Layer Device
National Semiconductor is a registered trademark of National Semiconductor Corporation.
Geode is a trademark of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
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2
Revision 1.0
GeodeTM
C
S4103
Table of Contents
1.0
Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
LINK INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2
ARBITER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3
REGISTER SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4
PACKET PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5
PORT STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.6
RECEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.7
TRANSMITTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.8
TRANSCEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.9
PHASE-LOCKED LOOP (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.10
RELATED DOCUMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.0
Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
PIN ASSIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.1
PHY-Link Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.2
Transceiver/1394 Cable Connection Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.3
Clock/Crystal Connection and Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.4
Power to/from Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.5
Power Supplies, Ground, Reserved, and No Connections . . . . . . . . . . . . . . . . . . . . . 11
3.0
Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
REGISTER ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
BASE REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3
PORT STATUS: PAGE 0, PORTS[0:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4
VENDOR IDENTIFICATION: PAGE 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5
VENDOR SPECIFIC: PAGE 7, PORTS[0:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.0
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2
OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3
DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4
AC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.0
Physcial Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Revision 1.0
3
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GeodeTM
C
S
4103
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1.0
Architectural Overview
The Geode CS4301 can be described as providing the
functional blocks as shown in Figure 1-1 and described in
the following subsections.
1.1
LINK INTERFACE
The Link Interface implements the PHY-Link Interface as
specified in clause 5, revision 2.0 of the P1394a specifica-
tion. It handles both differentiated and undifferentiated
modes of operation. It decodes LREQ requests and com-
municates with the Arbiter and Register Set for bus
requests and register read/write commands, respectively.
In addition to receiving LREQ requests, the Link Interface
handles the bidirectional control and data buses for packet
transmission and reception as well as register reads. The
Link Interface uses the Link Power Status input (LPS) sig-
nal to determine the operational state of the Geode
CS4210 OHCI Controller and for resetting, disabling, and/
or restoring the PHY-Link Interface. The Link Interface also
controls the Link-On output (LNKON), used to signal the
CS4210 when the PHY-Link Interface is not active.
Figure 1-1. Functional Block Diagram
Link Interface
Register
Arbiter
Port State
Transceiver
Receiver
Transmitter
PLL
Set
Transceiver
Transceiver
LPS
SCLK
LREQ
DATA[0:7]
CTRL[0:1]
LNKON
DIRECT
Packet
Processor
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4
Revision 1.0
GeodeTM
C
S4103
Architectural Overview
(Continued)
1.2
ARBITER
The Arbiter includes the logic to implement all of the state
machines described in clause 7, revision 2.0 of the P1394a
specification except for the Port State machine. These
include the state machines for bus reset, Tree-ID, Self-ID,
and normal arbitration. The Arbiter monitors the received
line states and controls the transmitted and repeated line
states for the various types of arbitration processes. The
Arbiter maintains the arbitration timer responsible for timing
the various gaps and line state lengths required for P1394a
operation. It also receives bus requests from the CS4210
via the Link Interface and sends the appropriate handshake
signals to indicate won/lost status to the Link Interface.
1.3
REGISTER SET
The Register Set implements all of the registers defined in
the P1394a specification. The Register Set has interfaces
to the Link Interface module for register reads and writes as
well as to the Packet Processor for register reads. The
Register Set also contains several National Semiconductor
specific register bits implemented in the address page
which are set aside for vendor specific registers and inter-
faces with the Arbiter and Port State. For example, the
Root hold-off bit affects the Arbiter and the Port Disabled
bits affect the operation of the Port State.
1.4
PACKET PROCESSOR
The Packet Processor decodes all PHY packets received
by the CS4103, (from both the CS4210 and cable inter-
faces) and generates all PHY response packets that the
CS4103 must send autonomously. The Packet Processor
also provides validity checking on PHY packets, discarding
invalid packets. During bus initialization and configuration,
the Packet Processor signals the reception of Self-ID pack-
ets to the Arbiter. The Arbiter uses this information during
the Self-ID process to increment the Node ID count.
1.5
PORT STATE
The Port State contains the Port Connection State Machine
described in clause 7.10.4, revision 2.0 of the P1394a
specification. The Port State keeps track of the connect
status and state of each port, (Disconnect, Resuming,
Active, etc.). The Port State also implements the connec-
tion timer used for timing various transitions within the state
machine and reports certain state conditions to other mod-
ules. For example, the Port State signals the Arbiter with
the Active, Resume, and Suspend state of each port along
with other status information. It also reports connection
change information for waking the CS4103 from a low-
power mode.
1.6
RECEIVER
The Receiver consists of the logic responsible for the data/
strobe decoding, the serial-to-parallel converter, and the
re-time FIFO. During packet reception and repeating, the
re-time FIFO buffers the data to allow for frequency differ-
ences between the transmitting and receiving PHYs. The
CS4103 writes data into the FIFO using the recovered
clock from the incoming data stream. It removes data from
the FIFO using the local system clock. The size of the FIFO
is calculated to allow the successful reception of a maxi-
mum length packet with a maximum clock offset between
this PHY and the Transmitter.
1.7
TRANSMITTER
The Transmitter handles the parallel-to-serial conversion
and data/strobe encoding operations. It can transmit data
from one of three sources: the Link Interface, the on-chip
Packet Processor, and the repeat path. The Arbiter controls
which path is selected for each transmit operation.
1.8
TRANSCEIVER
The Transceiver handles the interface to the 1394 cable. It
has drivers and receivers for the cable wires, (TPA+, TPA,
TPB+, and TPB). In addition, each Transceiver provides a
TpBias output for its port. On transmit, the Transceiver gen-
erates the appropriate speed signaling for 100, 200, and
400 Mbit/sec operation. The Transceiver also transmits 1,
0, and Z values on each differential pair (TPA and TPB).
The Receiver detects speed signaling values and the Arbi-
tration line states (1, 0, and Z). It contains separate differ-
ential receivers used to interpret data and strobe during
packet reception.
The Transceiver logic contains TpBias detection circuitry as
well as a Connect Detect circuit. The Transceiver enables
the Connect Detect circuit when the Port State logic
instructs the Transceiver to turn off the TpBias generation,
(for example, when the port enters the Suspend state).
1.9
PHASE-LOCKED LOOP (PLL)
The PLL module uses a 24.576 MHz crystal or clock input
to generate all of the local clocks. These include the 49.152
MHz system clock (SCLK) as well as the 98.304 MHz,
196.698 MHz, and 393.216 MHz clocks necessary for
transmitting at 100, 200, and 400 Mbit/sec. This PLL
design requires no external filter components.
1.10 RELATED DOCUMENTS
The following documents may be useful in understanding
the terms and concepts used in this publication.
IEEE Standard 1394-1995 "IEEE Standard for a high
performance serial Bus"
P1394a Draft 2.0 "P1394a Draft Standard for a High
Performance Serial Bus" (supplement)
Revision 1.0
5
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GeodeTM
C
S
4103
2.0
Signal Definitions
This section defines the signals and external interface of
the CS4103. Figure 2-1 shows the pins organized by their
functional groupings (internal test and electrical pins are
not shown).
2.1
PIN ASSIGNMENT
The tables in this section use several common abbrevia-
tions. Table 2-1 lists the mnemonics and their meanings.
Figure 2-2 on page 6 shows the pin assignment for the
CS4103 with Tables 2-2 and 2-3, on pages 7 and 8, listing
the pin assignments sorted by pin number and alphabeti-
cally by signal name.
Section 2.2 "Signal Descriptions" starting on page 9 pro-
vides a description for each signal within its associated
functional group.
Figure 2-1. Signal Groups
Table 2-1. Pin Type Definitions
Mnemonic
Definition
I
Input Pin
I/O
Bidirectional Pin
O
Output
t/s
TRI-STATE Signal
VDD
2.5V Core Power Supply
VDDIO
3.3V I/O Power Supply
VSS
Ground Connection
TPA[0:2]+
TPA[0:2]
TBA[0:2]+
TPB[0:2]
TPBIAS[0:2]
DATA[0:7]
CTRL[0:1]
LREQ
SCLK
LPS
LOCKIND
PHY-Link
Interface
GeodeTM
CS4103
Transceiver/
DIRECT
XI
XO
Clock/Crystal
and
LNKON
PC0
PC1
PC2
Power to/from
Bus
CPS
1394 Cable
Connections
RESET#
Reset
Connection
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