Document Outline

• 1.0 Architecture Overview
  • 1.1 PCI Bus Interface
  • 1.2 ISA Bus Interface
  • 1.3 AT Compatibility Logic
    • 1.3.1 DMA Controller
    • 1.3.2 Programmable Interval Timer
    • 1.3.3 Programmable Interrupt Controller
  • 1.4 IDE Controllers
  • 1.5 Power Management
    • 1.5.1 GPIO Interface
  • 1.6 XpressAUDIO
    • 1.6.1 AC97 Codec Interface
    • 1.6.2 VSA Technology Support Hardware
  • 1.7 Display Subsystem Extensions
  • 1.8 Clock Generation
  • 1.9 Universal Serial Bus
  • 1.10 Processor Support
• 2.0 Signal Definitions
  • 2.1 Pin Assignments
  • 2.2 Signal Descriptions
    • 2.2.1 Reset Interface 
    • 2.2.2 Clock Interface 
    • 2.2.3 CPU Interface 
    • 2.2.4 PCI Interface 
    • 2.2.5 ISA Bus Interface 
    • 2.2.6 ROM Interface 
    • 2.2.7 IDE Interface
    • 2.2.8 USB Interface 
    • 2.2.9 Game Port and General Purpose I/O Interface 
    • 2.2.10 Audio Interface 
    • 2.2.11 Display Interface 
    • 2.2.12 DCLK PLL 
    • 2.2.13 Power, Ground, and Reserved
    • 2.2.14 Internal Test and Measurement
• 3.0 Functional Description
  • 3.1 Processor Interface
    • 3.1.1 Display Subsystem Connections
    • 3.1.2 PSERIAL Pin Interface
      • 3.1.2.1 Video Retrace Interrupt
  • 3.2 PCI Bus Interface
    • 3.2.1 PCI Initiator
    • 3.2.2 PCI Target
    • 3.2.3 Special Bus Cycles�Shutdown/Halt
    • 3.2.4 PCI Bus Parity
    • 3.2.5 PCI Interrupt Routing Support
    • 3.2.6 Delayed Transactions
  • 3.3 Resets and Clocks
    • 3.3.1 Resets
    • 3.3.2 ISA Clock
    • 3.3.3 DOT Clock
      • 3.3.3.1 DCLK Programming
  • 3.4 Power Management
    • 3.4.1 APM Support
    • 3.4.2 CPU Power Management
      • 3.4.2.1 Suspend Modulation
      • 3.4.2.2 3 Volt Suspend
      • 3.4.2.3 Save-To-Disk
    • 3.4.3 Peripheral Power Management
      • 3.4.3.1 Device Idle Timers and Traps
      • 3.4.3.2 General Purpose Timers
      • 3.4.3.3 ACPI Timer Register
      • 3.4.3.4 General Purpose I/O Pins
      • 3.4.3.5 Power Management SMI Status Reporting Registers
      • 3.4.3.6 Device Power Management Register Programming Summary
  • 3.5 PC/AT Compatibility Logic
    • 3.5.1 ISA Subtractive Decode
    • 3.5.2 ISA Bus Interface
      • 3.5.2.1 Delayed PCI Transactions
      • 3.5.2.2 Limited ISA and ISA Master Modes
      • 3.5.2.3 ISA Bus Data Steering
      • 3.5.2.4 I/O Recovery Delays
      • 3.5.2.5 ISA DMA
    • 3.5.3 ROM Interface
    • 3.5.4 Megacells
      • 3.5.4.1 Direct Memory Access (DMA)
      • 3.5.4.2 Programmable Interval Timer
      • 3.5.4.3 Programmable Interrupt Controller
      • 3.5.4.4 PCI Compatible Interrupts
    • 3.5.5 I/O Ports 092h and 061h System Control
      • 3.5.5.1 I/O Port 092h System Control
      • 3.5.5.2 I/O Port 061h System Control
      • 3.5.5.3 SMI Generation for NMI
    • 3.5.6 Keyboard Interface Function
      • 3.5.6.1 Fast Keyboard Gate Address 20 and CPU Reset
    • 3.5.7 External Real-Time Clock Interface
  • 3.6 IDE Controller
    • 3.6.1 IDE Interface Signals
    • 3.6.2 IDE Configuration Registers
      • 3.6.2.1 PIO Mode
      • 3.6.2.2 Bus Master Mode
      • 3.6.2.3 Ultra DMA/33 Mode
  • 3.7 XpressAUDIO
    • 3.7.1 Subsystem Data Transport Hardware
      • 3.7.1.1 Audio Bus Masters
      • 3.7.1.2 Physical Region Descriptor Table Address
      • 3.7.1.3 Physical Region Descriptor Format
      • 3.7.1.4 Programming Model
      • 3.7.1.5 AC97 Codec Interface
    • 3.7.2 VSA Technology Support Hardware
      • 3.7.2.1 VSA Technology
      • 3.7.2.2 Audio SMI Related Registers
      • 3.7.2.3 IRQ Configuration Registers
  • 3.8 Display Subsystem Extensions
    • 3.8.1 Video Interface Configuration Registers
    • 3.8.2 Video Accelerator
      • 3.8.2.1 Line Buffers
      • 3.8.2.2 Video Port Protocol
      • 3.8.2.3 Video Format
      • 3.8.2.4 X and Y Scaler / Filter
      • 3.8.2.5 Color-Space-Converter
    • 3.8.3 Video Overlay
    • 3.8.4 Gamma RAM
    • 3.8.5 Display Interface
      • 3.8.5.1 Video DACs
      • 3.8.5.2 VESA DDC2B / DPMS
      • 3.8.5.3 Flat Panel Support
  • 3.9 Universal Serial Bus Support
    • 3.9.1 USB PCI Controller
    • 3.9.2 USB Host Controller
    • 3.9.3 USB Power Management
• 4.0 Register Descriptions
  • 4.1 PCI Configuration Space and Access Methods
  • 4.2 Register Summary
  • 4.3 Chipset Register Space
    • 4.3.1 Bridge Configuration Registers - Function 0
    • 4.3.2 SMI Status and ACPI Timer Registers - Function 1
    • 4.3.3 IDE Controller Registers - Function 2
    • 4.3.4 XpressAUDIO Registers - Function 3
    • 4.3.5 Video Controller Registers - Function 4
  • 4.4 USB Controller Registers - PCIUSB
  • 4.5 ISA Legacy I/O Register Space
  • 4.6 V-ACPI I/O Register Space
• 5.0 Electrical Specifications
  • 5.1 Test Modes
    • 5.1.1 Nand Tree Mode
  • 5.2 Electrical Connections
    • 5.2.1 Pull-Up Resistors
    • 5.2.2 Unused Input Pins
    • 5.2.3 NC-Designated Pins
    • 5.2.4 Power/Ground Connections and Decoupling
  • 5.3 Absolute Maximum Ratings
  • 5.4 Recommended Operating Conditions
  • 5.5 DC Characteristics
  • 5.6 AC Characteristics
  • 5.7 Video Characteristics
• 6.0 Mechanical Specifications
• Appendix A Support Documentation
  • A.1 Revision History
• List of Figures
  • Figure 1-1. Internal Block Diagram
  • Figure 1-2. AC97 Codec Signal Connections
  • Figure 1-3. Display Subsystem Extensions, 8-Bit Interface
  • Figure 1-4. CS5530 Clock Generation
  • Figure 1-5. System Block Diagram
  • Figure 2-1. CS5530 Signal Groups
  • Figure 2-2. TBGA Pin Assignment Diagram Order Number: 25420-03
  • Figure 3-1. Processor Signal Connections
  • Figure 3-2. Portable/Desktop Display Subsystem Configurations
  • Figure 3-3. PIXEL Signal Connections
  • Figure 3-4. Subtractive Decoding Timing
  • Figure 3-5. CS5530 Reset
  • Figure 3-6. System Clock Distribution
  • Figure 3-7. General Purpose Timer and UDEF Trap SMI Tree Example
  • Figure 3-8. Non-Posted PCI-to-ISA Access
  • Figure 3-9. PCI to ISA Cycles with Delayed Transaction Enabled
  • Figure 3-10. Limited ISA Mode
  • Figure 3-11. ISA Master Mode
  • Figure 3-12. ISA DMA Read from PCI Memory
  • Figure 3-13. ISA DMA Write To PCI Memory
  • Figure 3-14. PIT Timer
  • Figure 3-15. PIC Interrupt Controllers
  • Figure 3-16. PCI and IRQ Interrupt Mapping
  • Figure 3-17. SMI Generation for NMI
  • Figure 3-18. External RTC interface
  • Figure 3-19. CS5530 and IDE Channel Connections
  • Figure 3-20. PRD Table Example
  • Figure 3-21. AC97 Signal Connections
  • Figure 3-22. Audio SMI Tree Example
  • Figure 3-23. 8-Bit Display Subsystem Extensions
  • Figure 3-24. Video Port Protocol
  • Figure 5-1. NAND Tree Output Waveform
  • Figure 5-2. Drive Level and Measurement Points for Switching Characteristics
  • Figure 5-3. 3.3V PCICLK Waveform
  • Figure 5-4. CPU Interface Timing
  • Figure 5-5. Audio Interface Timing
  • Figure 5-6. Display TFT/TV Outputs Delays
  • Figure 5-7. VID_RDY Delays
  • Figure 5-8. Typical Video Connection Diagram
  • Figure 6-1. 352-Terminal TBGA Mechanical Package Outline
• List of Tables
  • Table 2-1. Pin Type Definitions
  • Table 2-2. 352 TBGA Pin Assignments - Sorted by Pin Number
  • Table 2-3. 352 TBGA Pin Assignments - Sorted Alphabetically by Signal Name
  • Table 3-1. GXLV Processor Serial Packet Register
  • Table 3-2. PCI Command Register
  • Table 3-3. PCI Command Encoding
  • Table 3-4. Subtractive Decoding Related Bits
  • Table 3-5. PERR#/SERR# Associated Register Bits
  • Table 3-6. PCI Interrupt Steering Registers 
  • Table 3-7. Delay Transaction Programming Bits
  • Table 3-8. ISACLK Divider Bits
  • Table 3-9. DCLK Configuration Register
  • Table 3-10. F4BAR+Memory Offset 24h[22:12] Decode (Value of �N�)
  • Table 3-11. Base Address Register (F1BAR) for SMI Status and ACPI Timer Support
  • Table 3-12. APM Support Registers
  • Table 3-13. Suspend Modulation Related Registers 
  • Table 3-14. Clock Stop Control Register
  • Table 3-15. Power Management Shadow Registers 
  • Table 3-16. Power Management Global Enabling Bits
  • Table 3-17. Keyboard/Mouse Idle Timer and Trap Related Registers
  • Table 3-18. Parallel/Serial Idle Timer and Trap Related Registers
  • Table 3-19. Floppy Disk Idle Timer and Trap Related Registers
  • Table 3-20. Primary Hard Disk Idle Timer and Trap Related Registers
  • Table 3-21. Secondary Hard Disk Idle Timer and Trap Related Registers
  • Table 3-22. User Defined Device 1 (UDEF1) Idle Timer and Trap Related Registers
  • Table 3-23. User Defined Device 2 (UDEF2) Idle Timer and Trap Related Registers
  • Table 3-24. User Defined Device 3 (UDEF3) Idle Timer and Trap Related Registers
  • Table 3-25. Video Idle Timer and Trap Related Registers
  • Table 3-26. VGA Timer Related Registers
  • Table 3-27. General Purpose Timers and Control Registers 
  • Table 3-28. ACPI Timer Related Registers/Bits 
  • Table 3-29. V-ACPI I/O Register Space Summary
  • Table 3-30. GPIO Pin Function Selection
  • Table 3-31. GPIO Pin Configuration/Control Registers 
  • Table 3-32. Top Level SMI Status Register (Read to Clear)
  • Table 3-33. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear)
  • Table 3-34. Device Power Management Programming Summary 
  • Table 3-35. Cycle Configuration Bits 
  • Table 3-36. Signal Assignments
  • Table 3-37. I/O Recovery Programming Register
  • Table 3-38. ROM Interface Related Bits
  • Table 3-39. DMA Shadow Register
  • Table 3-40. PIT Control and I/O Port 061h Associated Register Bits
  • Table 3-41. PIT Shadow Register
  • Table 3-42. PIC Interrupt Mapping
  • Table 3-43. PCI INTA Cycle Disable/Enable Bit
  • Table 3-44. PIC Shadow Register
  • Table 3-45. PCI Interrupt Steering Registers 
  • Table 3-46. Interrupt Edge/Level Select Registers
  • Table 3-47. I/O Ports 061h and 092h
  • Table 3-48. I/O Port 092h Decode Enable Bit
  • Table 3-49. Decode Control Registers
  • Table 3-50. External Keyboard Controller Registers 
  • Table 3-51. A20 Associated Programming Bits
  • Table 3-52. Real-Time Clock Registers
  • Table 3-53. IDE Reset Bits
  • Table 3-54. Base Address Register (F2BAR) for IDE Support Registers
  • Table 3-55. PIO Programming Registers
  • Table 3-56. IDE Bus Master PRD Table Address Registers
  • Table 3-57. IDE Bus Master Command and Status Registers 
  • Table 3-58. Physical Region Descriptor Format
  • Table 3-59. Ultra DMA/33 Signal Definitions
  • Table 3-60. MDMA/UDMA Control Registers
  • Table 3-61. Base Address Register (F3BAR) for XpressAUDIO Registers
  • Table 3-62. Generic Bit Formats for Audio Bus Master Configuration Registers 
  • Table 3-63. Audio Bus Master Configuration Register Summary
  • Table 3-64. Physical Region Descriptor Format
  • Table 3-65. Codec Configuration/Control Registers 
  • Table 3-66. Second Level SMI Status Reporting Registers
  • Table 3-67. Third Level SMI Status Reporting Registers
  • Table 3-68. Sound Card I/O Trap and Fast Path Enable Registers
  • Table 3-69. IRQ Configuration Registers 
  • Table 3-70. Base Address Register (F4BAR) for Video Controller Support Registers
  • Table 3-71. Video Input Format Bits
  • Table 3-72. Video Scale Register
  • Table 3-73. Video X and Y Position Registers
  • Table 3-74. Video Color Registers
  • Table 3-75. Display Configuration Register 
  • Table 3-76. USB PCI Header Registers
  • Table 3-77. USB Host Controller Registers
  • Table 4-1. PCI Configuration Address Register (0CF8h)
  • Table 4-2. Function 0: PCI Header and Bridge Configuration Registers Summary 
  • Table 4-3. Function 1: PCI Header Registers for SMI Status and ACPI Timer Summary
  • Table 4-4. F1BAR: SMI Status and ACPI Timer Registers Summary
  • Table 4-5. Function 2: PCI Header Registers for IDE Controller Summary
  • Table 4-6. F2BAR: IDE Controller Configuration Registers Summary 
  • Table 4-7. Function 3: PCI Header Registers for XpressAUDIO Subsystem Summary
  • Table 4-8. F3BAR: XpressAUDIO Subsystem Configuration Registers Summary 
  • Table 4-9. Function 4: PCI Header Registers for Video Controller Summary
  • Table 4-10. F4BAR: Video Controller Configuration Registers Summary 
  • Table 4-11. PCIUSB 00h-FFh Register Summary
  • Table 4-12. ISA Legacy I/O Register Summary 
  • Table 4-13. V-ACPI I/O Register Space Summary
  • Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers 
  • Table 4-15. F1 Index xxh: PCI Header Registers for SMI Status and ACPI Timer 
  • Table 4-16. F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers 
  • Table 4-17. F2 Index xxh: PCI Header Registers for IDE Configuration 
  • Table 4-18. F2BAR+I/O Offset xxh: IDE Configuration Registers 
  • Table 4-19. F3 Index xxh: PCI Header Registers for XpressAUDIO 
  • Table 4-20. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers 
  • Table 4-21. F4 Index xxh: PCI Header Registers for Video Controller Configuration 
  • Table 4-22. F4BAR+Memory Offset xxh: Video Controller Configuration Registers 
  • Table 4-23. F4BAR+Memory Offset 24h[22:12] Decode (Value of �N�)
  • Table 4-24. PCIUSB Index xxh: USB Controller Registers 
  • Table 4-25. DMA Channel Control Registers 
  • Table 4-26. DMA Page Registers
  • Table 4-27. Programmable Interval Timer Registers
  • Table 4-28. Programmable Interrupt Controller Registers 
  • Table 4-29. Keyboard Controller Registers
  • Table 4-30. Real-Time Clock Registers
  • Table 4-31. Miscellaneous Registers 
  • Table 4-32. V-ACPI Registers 
  • Table 4-33. SETUP_IDX Values
  • Table 4-34. GPIO Mapping (0x10-0x17)
  • Table 4-35. IRQ Wakeup Status Mapping (0x30-0x3F)
  • Table 4-36. Commands (0x41-0x43, and 0x50)
  • Table 4-37. Signature/Length Block for 0x43
  • Table 4-38. I/O Block for 0x43
  • Table 4-39. Audio Soft SMI Emulation (0x60-0x63)
  • Table 4-40. Audio Power Control (0x64)
  • Table 5-1. Test Mode Selection
  • Table 5-2. NAND Tree Test Mode Pins
  • Table 5-3. Pins with Weak Internal Resistor
  • Table 5-4. Absolute Maximum Ratings
  • Table 5-5. Recommended Operating Conditions
  • Table 5-6. DC Characteristics (at Recommended Operating Conditions)
  • Table 5-7. Drive Level and Measurement Points for Switching Characteristics
  • Table 5-8. AC Characteristics of Specification Compliant Interface Signals
  • Table 5-9. Clock Characteristics
  • Table 5-10. CPU Interface Timings
  • Table 5-11. Audio Interface Timings
  • Table 5-12. Video Interface: Recommended Operating Conditions
  • Table 5-13. Video Interface: Miscellaneous Operating Characteristics
  • Table 5-14. Video Interface: Analog Output Rise/Settle Times
  • Table 5-15. Video Interface: Setup/Hold and Delay Times
  • Table 6-1. 352 TBGA Package Dimension