Электронный компонент: CS5530A

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� 2001 National Semiconductor Corporation

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General Description

The CS5530A I/O companion is designed to work in con-
junction with a GX-series processor (i.e., GX1, GXLV,
GXm); all members of the National Semiconductor

�

GeodeTM family of products. Together, the Geode proces-
sor and CS5530A provide a system-level solution well
suited for the high performance needs of a host of devices
which include digital set-top boxes and thin client devices.
Due to the low power consumption of the GX-series pro-
cessors, this solution satisfies the needs of battery pow-
ered devices such as National's WebPADTM system, and
thermal design is eased allowing for fanless system
design.

The CS5530A I/O companion is a PCI-to-ISA bridge (South
Bridge), ACPI-compliant chipset that provides AT/ISA style
functionality. The device contains state-of-the-art power
management that enables systems, especially battery
powered systems, to significantly reduce power consump-
tion.

Audio is supported through PCI bus master engines which
connect to an AC97 compatible codec such as the National
Semiconductor LM4548. If industry standard audio is
required, a combination of hardware and software called
Virtual System Architecture

�

(VSATM) technology is pro-

vided.

The Geode GX-series processors' graphics/video output is
connected to the CS5530A. The CS5530A graphics/video
support includes a PLL that generates the DOT clock for
the GX-series processors (where the graphics controller is
located), video acceleration hardware, gamma RAM plus
three DACs for RGB output to CRT, and digital RGB that
can be directly connected to TFT panels or NTSC/PAL
encoders. The digital RGB output can also be connected to
the National Semiconductor Geode CS9211 graphics com-
panion (a flat panel display controller) for DSTN panel sup-
port.

GeodeTM CS5530A Internal Block Diagram

X-Bus

ISA Bus

PCI Bus

USB

PCI to X-Bus / X-Bus to PCI Bridge

PCI to USB Macro

Active Decode

Address Mapper

Audio/Codec/MPU

Interface

Pwr Mgmt, Traps,

Events, and Timers

IDE

Interface

Display Interface

MPEG, DOT Clock

CSC and SCL

RGB/FP Interface

AT Compatibility Logic

ISA Bus Interface

AT Ports, ISA Megacells

Display

PCI Configuration

Registers

Graphics

and Video

from CPU

X-Bus Arbiter

CS5530A Support

GPIOs

IDE

AC97 Codec

Ultra DMA/33

(e.g., LM4548)

Joystick / Game Port

Joystick

PC97317 SIO

GPCS

GeodeTM CS9211

Graphics Companion

May 2001

Revision 1.1

GeodeTM CS5530A I/O Companion
Multi-Function South Bridge

National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation.
Geode, VSA and WebPAD are trademarks of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.

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Two bus mastering IDE controllers are included for support
of up to four ATA-compliant devices. A two-port Universal
Serial Bus (USB) provides high speed, Plug & Play expan-
sion for a variety of consumer peripheral devices such as a
keyboard, mouse, printer, and digital camera. If additional
functions are required like real-time clock, floppy disk, PS2
keyboard, and PS2 mouse, a SuperI/O such as the
National PC97317 can be easily connected to the
CS5530A.

Features

General Features

Designed for use with National's Geode GX-series
processors

352 PBGA (Plastic Ball Grid Array) package

3.3V or 5.0V PCI bus compatible

5.0V tolerant on all inputs

3.3V core

PCI-to-ISA Bridge

PCI 2.1 compliant

Supports PCI initiator-to-ISA and ISA master-to-PCI
cycle translations

PCI master for audio I/O and IDE controllers

Subtractive agent for unclaimed transactions

PCI-to-ISA interrupt mapper/translator

AT Compatibility

Two 8259A-equivalent interrupt controllers

8254-equivalent timer

Two 8237-equivalent DMA controllers

Boot ROM and keyboard chip select

Extended ROM to 16 MB

Bus Mastering IDE Controllers

Two controllers with support for up to four IDE devices

Independent timing for master and slave devices for
both channels

PCI bus master burst reads and writes

Ultra DMA/33 (ATA-4) support

Multiword DMA support

Programmed I/O (PIO) Modes 0-4 support

Power Management

Intelligent system controller supports multiple power
management standards:
-- Full ACPI and Legacy (APM) support
-- Directly manages all GX-series processors' power

states (including automatic Suspend modulation for
optimal performance/thermal balancing)

I/O traps and idle timers for peripheral power
management

Up to eight GPIOs for system control:
-- All eight are configurable as external wakeup events

Dedicated inputs for keyboard and mouse wakeup
events

XpressAUDIO

Provides "back-end" hardware support via six buffered
PCI bus masters

AC97 codec interface:
-- Specification Revision 1.3, 2.0, and 2.1 compliant

interface. Note that the codec (e.g., LM4548) must
have SRC (sample rate conversion) support

Display Subsystem Extensions

Complements the GX-series processors' graphics and
video capabilities:
-- Three independent line buffers for accelerating video

data streams

-- Handles asynchronous video and graphics data

streams concurrently from the processor

-- YUV to RGB conversion hardware
-- Arbitrary X & Y interpolative scaling
-- Color keying for graphics/video overlay

VDACs / Display interface:
-- Three integrated DACs
-- Gamma RAM:

� Provides gamma correction for graphics data

streams

� Provides brightness/contrast correction for video

data streams

-- Integrated DOT clock generator
-- Digital RGB interface drives TFT panels or standard

NTSC/PAL encoders

-- Up to 1280x1024 @ 85 Hz

Universal Serial Bus

Two independent USB interfaces:
-- Open Host Controller Interface (OpenHCI)

specification compliant

-- Second generation proven core design

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Table of Contents

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1.0

Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1

PCI BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2

ISA BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3

AT COMPATIBILITY LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3.1

DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3.2

Programmable Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3.3

Programmable Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.4

IDE CONTROLLERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.5

POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.5.1

GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.6

XPRESSAUDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.6.1

AC97 Codec Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.6.2

VSA Technology Support Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.7

DISPLAY SUBSYSTEM EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.8

CLOCK GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.9

UNIVERSAL SERIAL BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.10

PROCESSOR SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.0

Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1

PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.2.1

Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.2.2

Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.2.3

CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.2.4

PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.2.5

ISA Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.2.6

ROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.2.7

IDE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.2.8

USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.2.9

Game Port and General Purpose I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.2.10

Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.2.11

Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.2.12

DCLK PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.2.13

Power, Ground, and No Connects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.2.14

Internal Test and Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.0

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.1

PROCESSOR INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.1.1

Display Subsystem Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.1.2

PSERIAL Pin Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.1.2.1

Video Retrace Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.2

PCI BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.2.1

PCI Initiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.2.2

PCI Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.2.3

Special Bus Cycles�Shutdown/Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.2.4

PCI Bus Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.2.5

PCI Interrupt Routing Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.2.6

Delayed Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

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3.3

RESETS AND CLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.3.1

Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.3.2

ISA Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.3.3

DOT Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.3.3.1

DCLK Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.4

POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.4.1

CPU Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.4.1.1

On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.4.1.2

Active Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.4.1.3

Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.4.1.4

3 Volt Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.4.1.5

Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.4.1.6

Suspend Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.4.1.7

Save-to-Disk/Save-to-RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.4.2

APM Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.4.3

Peripheral Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.4.3.1

Device Idle Timers and Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.4.3.2

General Purpose Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.4.3.3

ACPI Timer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.4.3.4

General Purpose I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.4.3.5

Power Management SMI Status Reporting Registers . . . . . . . . . . . . . . . . . . . . . . . . 78

3.4.3.6

Device Power Management Register Programming Summary . . . . . . . . . . . . . . . . . 86

3.5

PC/AT COMPATIBILITY LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

3.5.1

ISA Subtractive Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

3.5.2

ISA Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.5.2.1

Delayed PCI Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3.5.2.2

Limited ISA and ISA Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

3.5.2.3

ISA Bus Data Steering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

3.5.2.4

I/O Recovery Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

3.5.2.5

ISA DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

3.5.3

ROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.5.4

Megacells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.5.4.1

Direct Memory Access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

3.5.4.2

Programmable Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

3.5.4.3

Programmable Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

3.5.4.4

PCI Compatible Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

3.5.5

I/O Ports 092h and 061h System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

3.5.5.1

I/O Port 092h System Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

3.5.5.2

I/O Port 061h System Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

3.5.5.3

SMI Generation for NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

3.5.6

Keyboard Interface Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

3.5.6.1

Fast Keyboard Gate Address 20 and CPU Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . 106

3.5.7

External Real-Time Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

3.6

IDE CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

3.6.1

IDE Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

3.6.2

IDE Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

3.6.2.1

PIO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

3.6.2.2

Bus Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

3.6.2.3

Ultra DMA/33 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

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3.7

XPRESSAUDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

3.7.1

Subsystem Data Transport Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

3.7.1.1

Audio Bus Masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

3.7.1.2

Physical Region Descriptor Table Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

3.7.1.3

Physical Region Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

3.7.1.4

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

3.7.1.5

AC97 Codec Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

3.7.2

VSA Technology Support Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

3.7.2.1

VSA Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

3.7.2.2

Audio SMI Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

3.7.2.3

IRQ Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

3.8

DISPLAY SUBSYSTEM EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

3.8.1

Video Interface Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

3.8.2

Video Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

3.8.2.1

Line Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

3.8.2.2

Video Port Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

3.8.2.3

Video Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

3.8.2.4

X and Y Scaler / Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

3.8.2.5

Color-Space-Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

3.8.3

Video Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

3.8.4

Gamma RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

3.8.5

Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

3.8.5.1

Video DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

3.8.5.2

VESA DDC2B / DPMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

3.8.5.3

Flat Panel Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

3.9

UNIVERSAL SERIAL BUS SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

3.9.1

USB PCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

3.9.2

USB Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

3.9.3

USB Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

4.0

Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

4.1

PCI CONFIGURATION SPACE AND ACCESS METHODS . . . . . . . . . . . . . . . . . . . . . . . . . 141

4.2

REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

4.3

CHIPSET REGISTER SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

4.3.1

Bridge Configuration Registers - Function 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

4.3.2

SMI Status and ACPI Timer Registers - Function 1 . . . . . . . . . . . . . . . . . . . . . . . . . 182

4.3.3

IDE Controller Registers - Function 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

4.3.4

XpressAUDIO Registers - Function 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

4.3.5

Video Controller Registers - Function 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

4.4

USB REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

4.5

CS5530A ISA LEGACY I/O REGISTER SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

4.6

V-ACPI I/O REGISTER SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Document Outline

• 1.0 Architecture Overview
  • 1.1 PCI Bus Interface
  • 1.2 ISA Bus Interface
  • 1.3 AT Compatibility Logic
    • 1.3.1 DMA Controller
    • 1.3.2 Programmable Interval Timer
    • 1.3.3 Programmable Interrupt Controller
  • 1.4 IDE Controllers
  • 1.5 Power Management
    • 1.5.1 GPIO Interface
  • 1.6 XpressAUDIO
    • 1.6.1 AC97 Codec Interface
    • 1.6.2 VSA Technology Support Hardware
  • 1.7 Display Subsystem Extensions
  • 1.8 Clock Generation
  • 1.9 Universal Serial Bus
  • 1.10 Processor Support
• 2.0 Signal Definitions
  • 2.1 Pin Assignments
  • 2.2 Signal Descriptions
    • 2.2.1 Reset Interface
    • 2.2.2 Clock Interface
    • 2.2.3 CPU Interface 
    • 2.2.4 PCI Interface 
    • 2.2.5 ISA Bus Interface 
    • 2.2.6 ROM Interface
    • 2.2.7 IDE Interface 
    • 2.2.8 USB Interface 
    • 2.2.9 Game Port and General Purpose I/O Interface 
    • 2.2.10 Audio Interface
    • 2.2.11 Display Interface 
    • 2.2.12 DCLK PLL
    • 2.2.13 Power, Ground, and No Connects
    • 2.2.14 Internal Test and Measurement
• 3.0 Functional Description
  • 3.1 Processor Interface
    • 3.1.1 Display Subsystem Connections
    • 3.1.2 PSERIAL Pin Interface
      • 3.1.2.1 Video Retrace Interrupt
  • 3.2 PCI Bus Interface
    • 3.2.1 PCI Initiator
    • 3.2.2 PCI Target
    • 3.2.3 Special Bus Cycles�Shutdown/Halt
    • 3.2.4 PCI Bus Parity
    • 3.2.5 PCI Interrupt Routing Support
    • 3.2.6 Delayed Transactions
  • 3.3 Resets and Clocks
    • 3.3.1 Resets
    • 3.3.2 ISA Clock
    • 3.3.3 DOT Clock
      • 3.3.3.1 DCLK Programming
  • 3.4 Power Management
    • 3.4.1 CPU Power Management
      • 3.4.1.1 On
      • 3.4.1.2 Active Idle
      • 3.4.1.3 Suspend
      • 3.4.1.4 3 Volt Suspend
      • 3.4.1.5 Off
      • 3.4.1.6 Suspend Modulation
      • 3.4.1.7 Save-to-Disk/Save-to-RAM
    • 3.4.2 APM Support
    • 3.4.3 Peripheral Power Management
      • 3.4.3.1 Device Idle Timers and Traps
      • 3.4.3.2 General Purpose Timers
      • 3.4.3.3 ACPI Timer Register
      • 3.4.3.4 General Purpose I/O Pins
      • 3.4.3.5 Power Management SMI Status Reporting Registers
      • 3.4.3.6 Device Power Management Register Programming Summary
  • 3.5 PC/AT Compatibility Logic
    • 3.5.1 ISA Subtractive Decode
    • 3.5.2 ISA Bus Interface
      • 3.5.2.1 Delayed PCI Transactions
      • 3.5.2.2 Limited ISA and ISA Master Modes
      • 3.5.2.3 ISA Bus Data Steering
      • 3.5.2.4 I/O Recovery Delays
      • 3.5.2.5 ISA DMA
    • 3.5.3 ROM Interface
    • 3.5.4 Megacells
      • 3.5.4.1 Direct Memory Access (DMA)
      • 3.5.4.2 Programmable Interval Timer
      • 3.5.4.3 Programmable Interrupt Controller
      • 3.5.4.4 PCI Compatible Interrupts
    • 3.5.5 I/O Ports 092h and 061h System Control
      • 3.5.5.1 I/O Port 092h System Control
      • 3.5.5.2 I/O Port 061h System Control
      • 3.5.5.3 SMI Generation for NMI
    • 3.5.6 Keyboard Interface Function
      • 3.5.6.1 Fast Keyboard Gate Address 20 and CPU Reset
    • 3.5.7 External Real-Time Clock Interface
  • 3.6 IDE Controller
    • 3.6.1 IDE Interface Signals
    • 3.6.2 IDE Configuration Registers
      • 3.6.2.1 PIO Mode
      • 3.6.2.2 Bus Master Mode
      • 3.6.2.3 Ultra DMA/33 Mode
  • 3.7 XpressAUDIO
    • 3.7.1 Subsystem Data Transport Hardware
      • 3.7.1.1 Audio Bus Masters
      • 3.7.1.2 Physical Region Descriptor Table Address
      • 3.7.1.3 Physical Region Descriptor Format
      • 3.7.1.4 Programming Model
      • 3.7.1.5 AC97 Codec Interface
    • 3.7.2 VSA Technology Support Hardware
      • 3.7.2.1 VSA Technology
      • 3.7.2.2 Audio SMI Related Registers
      • 3.7.2.3 IRQ Configuration Registers
  • 3.8 Display Subsystem Extensions
    • 3.8.1 Video Interface Configuration Registers
    • 3.8.2 Video Accelerator
      • 3.8.2.1 Line Buffers
      • 3.8.2.2 Video Port Protocol
      • 3.8.2.3 Video Format
      • 3.8.2.4 X and Y Scaler / Filter
      • 3.8.2.5 Color-Space-Converter
    • 3.8.3 Video Overlay
    • 3.8.4 Gamma RAM
    • 3.8.5 Display Interface
      • 3.8.5.1 Video DACs
      • 3.8.5.2 VESA DDC2B / DPMS
      • 3.8.5.3 Flat Panel Support
  • 3.9 Universal Serial Bus Support
    • 3.9.1 USB PCI Controller
    • 3.9.2 USB Host Controller
    • 3.9.3 USB Power Management
• 4.0 Register Descriptions
  • 4.1 PCI Configuration Space and Access Methods
  • 4.2 Register Summary
  • 4.3 Chipset Register Space
    • 4.3.1 Bridge Configuration Registers - Function 0
    • 4.3.2 SMI Status and ACPI Timer Registers - Function 1
    • 4.3.3 IDE Controller Registers - Function 2
    • 4.3.4 XpressAUDIO Registers - Function 3
    • 4.3.5 Video Controller Registers - Function 4
  • 4.4 USB Registers
  • 4.5 CS5530A ISA Legacy I/O Register Space
  • 4.6 V-ACPI I/O Register Space
• 5.0 Electrical Specifications
  • 5.1 Electrical Connections
    • 5.1.1 Pull-Up Resistors
    • 5.1.2 Unused Input Pins
    • 5.1.3 NC-Designated Pins
    • 5.1.4 Power/Ground Connections and Decoupling
  • 5.2 Absolute Maximum Ratings
  • 5.3 Operating Conditions
  • 5.4 DC Characteristics
    • 5.4.1 Definition of System Conditions for Measuring �On� Parameters
  • 5.5 AC Characteristics
  • 5.6 Display Characteristics
• 6.0 Test Mode Information
  • 6.1 NAND Tree Test Mode
  • 6.2 I/O Test
• 7.0 Physical Dimensions
• Appendix A Support Documentation
  • A.1 Revision History
• List of Figures
  • Figure 1-1. Internal Block Diagram
  • Figure 1-2. AC97 Codec Signal Connections
  • Figure 1-3. 8-Bit Display Subsystem Extensions
  • Figure 1-4. CS5530A Clock Generation
  • Figure 1-5. Example System Block Diagram
  • Figure 2-1. CS5530A Signal Groups
  • Figure 2-2. 352 PBGA Pin Assignment Diagram Order Number: CS5530A-UCE
  • Figure 3-1. Processor Signal Connections
  • Figure 3-2. Portable/Desktop Display Subsystem Configurations
  • Figure 3-3. PIXEL Signal Connections
  • Figure 3-4. Subtractive Decoding Timing
  • Figure 3-5. CS5530A Reset
  • Figure 3-6. System Clock Distribution
  • Figure 3-7. General Purpose Timer and UDEF Trap SMI Tree Example
  • Figure 3-8. Non-Posted PCI-to-ISA Access
  • Figure 3-9. PCI to ISA Cycles with Delayed Transaction Enabled
  • Figure 3-10. Limited ISA Mode
  • Figure 3-11. ISA Master Mode
  • Figure 3-12. ISA DMA Read from PCI Memory
  • Figure 3-13. ISA DMA Write To PCI Memory
  • Figure 3-14. PIT Timer
  • Figure 3-15. PIC Interrupt Controllers
  • Figure 3-16. PCI and IRQ Interrupt Mapping
  • Figure 3-17. SMI Generation for NMI
  • Figure 3-18. External RTC Interface
  • Figure 3-19. CS5530A and IDE Channel Connections
  • Figure 3-20. PRD Table Example
  • Figure 3-21. AC97 Signal Connections
  • Figure 3-22. Audio SMI Tree Example
  • Figure 3-23. 8-Bit Display Subsystem Extensions
  • Figure 3-24. Video Port Protocol
  • Figure 5-1. Test Measurements for AC Characteristics
  • Figure 5-2. Test Circuit for AC Characteristics
  • Figure 5-3. PCI Rising Edge (tLH) Test Circuit
  • Figure 5-4. PCI Falling Edge (tHL) Test Circuit
  • Figure 5-5. PCI Slew Rate Test Circuit
  • Figure 5-6. 3.3V PCICLK Waveform
  • Figure 5-7. CPU Interface Timing
  • Figure 5-8. Audio Interface Timing
  • Figure 5-9. USB Timing
  • Figure 5-10. USB Test Circuit
  • Figure 5-11. Display TFT/TV Outputs Delays
  • Figure 5-12. MPEG Timing
  • Figure 5-13. Typical Video Connection Diagram
  • Figure 6-1. NAND Tree Output Waveform
  • Figure 7-1. 352 PBGA Mechanical Package Outline
• List of Tables
  • Table 2-1. Pin Type Definitions
  • Table 2-2. 352 PBGA Pin Assignments - Sorted by Pin Number
  • Table 2-3. 352 PBGA Pin Assignments - Sorted Alphabetically by Signal Name
  • Table 3-1. GX-Series Processor Serial Packet Register
  • Table 3-2. PCI Command Register
  • Table 3-3. PCI Command Encoding
  • Table 3-4. Subtractive Decoding Related Bits
  • Table 3-5. PERR#/SERR# Associated Register Bits
  • Table 3-6. PCI Interrupt Steering Registers 
  • Table 3-7. Delay Transaction Programming Bits
  • Table 3-8. ISACLK Divider Bits
  • Table 3-9. DCLK Configuration Register
  • Table 3-10. F4BAR+Memory Offset 24h[22:12] Decode (Value of �N�)
  • Table 3-11. Base Address Register (F1BAR) for SMI Status and ACPI Timer Support
  • Table 3-12. Suspend Configuration Register 
  • Table 3-13. Clock Stop Control Register
  • Table 3-14. Suspend Modulation Related Registers 
  • Table 3-15. Power Management Shadow Registers 
  • Table 3-16. APM Support Registers 
  • Table 3-17. Power Management Global Enabling Bits
  • Table 3-18. Keyboard/Mouse Idle Timer and Trap Related Registers
  • Table 3-19. Parallel/Serial Idle Timer and Trap Related Registers
  • Table 3-20. Floppy Disk Idle Timer and Trap Related Registers
  • Table 3-21. Primary Hard Disk Idle Timer and Trap Related Registers
  • Table 3-22. Secondary Hard Disk Idle Timer and Trap Related Registers
  • Table 3-23. User Defined Device 1 (UDEF1) Idle Timer and Trap Related Registers
  • Table 3-24. User Defined Device 2 (UDEF2) Idle Timer and Trap Related Registers
  • Table 3-25. User Defined Device 3 (UDEF3) Idle Timer and Trap Related Registers
  • Table 3-26. Video Idle Timer and Trap Related Registers
  • Table 3-27. VGA Timer Related Registers
  • Table 3-28. General Purpose Timers and Control Registers 
  • Table 3-29. ACPI Timer Related Registers/Bits 
  • Table 3-30. V-ACPI I/O Register Space Summary
  • Table 3-31. GPIO Pin Function Selection
  • Table 3-32. GPIO Pin Configuration/Control Registers 
  • Table 3-33. Top Level SMI Status Register (Read to Clear)
  • Table 3-34. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear)
  • Table 3-35. Device Power Management Programming Summary 
  • Table 3-36. Cycle Configuration Bits 
  • Table 3-37. Signal Assignments
  • Table 3-38. I/O Recovery Programming Register
  • Table 3-39. ROM Interface Related Bits
  • Table 3-40. DMA Shadow Register
  • Table 3-41. PIT Control and I/O Port 061h Associated Register Bits
  • Table 3-42. PIT Shadow Register
  • Table 3-43. PIC Interrupt Mapping
  • Table 3-44. PCI INTA Cycle Disable/Enable Bit
  • Table 3-45. PIC Shadow Register
  • Table 3-46. PCI Interrupt Steering Registers 
  • Table 3-47. Interrupt Edge/Level Select Registers
  • Table 3-48. I/O Ports 061h and 092h
  • Table 3-49. I/O Port 092h Decode Enable Bit
  • Table 3-50. Decode Control Registers
  • Table 3-51. External Keyboard Controller Registers 
  • Table 3-52. A20 Associated Programming Bits
  • Table 3-53. Real-Time Clock Registers
  • Table 3-54. IDE Reset Bits
  • Table 3-55. Base Address Register (F2BAR) for IDE Support Registers
  • Table 3-56. PIO Programming Registers
  • Table 3-57. IDE Bus Master PRD Table Address Registers
  • Table 3-58. IDE Bus Master Command and Status Registers 
  • Table 3-59. Physical Region Descriptor Format
  • Table 3-60. Ultra DMA/33 Signal Definitions
  • Table 3-61. MDMA/UDMA Control Registers
  • Table 3-62. Base Address Register (F3BAR) for XpressAUDIO Registers
  • Table 3-63. Generic Bit Formats for Audio Bus Master Configuration Registers 
  • Table 3-64. Audio Bus Master Configuration Register Summary
  • Table 3-65. Physical Region Descriptor Format
  • Table 3-66. Codec Configuration/Control Registers 
  • Table 3-67. Second Level SMI Status Reporting Registers
  • Table 3-68. Third Level SMI Status Reporting Registers
  • Table 3-69. Sound Card I/O Trap and Fast Path Enable Registers
  • Table 3-70. IRQ Configuration Registers 
  • Table 3-71. Base Address Register (F4BAR) for Video Controller Support Registers
  • Table 3-72. Video Input Format Bits
  • Table 3-73. Video Scale Register
  • Table 3-74. Video X and Y Position Registers
  • Table 3-75. Video Color Registers
  • Table 3-76. Display Configuration Register 
  • Table 3-77. USB PCI Configuration Registers
  • Table 3-78. USB Controller Registers
  • Table 4-1. PCI Configuration Address Register (0CF8h)
  • Table 4-2. Function 0: PCI Header and Bridge Configuration Registers Summary 
  • Table 4-3. Function 1: PCI Header Registers for SMI Status and ACPI Timer Summary
  • Table 4-4. F1BAR: SMI Status and ACPI Timer Registers Summary
  • Table 4-5. Function 2: PCI Header Registers for IDE Controller Summary
  • Table 4-6. F2BAR: IDE Controller Configuration Registers Summary 
  • Table 4-7. Function 3: PCI Header Registers for XpressAUDIO Subsystem Summary
  • Table 4-8. F3BAR: XpressAUDIO Subsystem Configuration Registers Summary 
  • Table 4-9. Function 4: PCI Header Registers for Video Controller Summary
  • Table 4-10. F4BAR: Video Controller Configuration Registers Summary 
  • Table 4-11. USB PCI Configuration Registers Summary
  • Table 4-12. USB BAR: USB Controller Registers Summary 
  • Table 4-13. ISA Legacy I/O Registers Summary
  • Table 4-14. V-ACPI I/O Register Space Summary
  • Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers 
  • Table 4-16. F1 Index xxh: PCI Header Registers for SMI Status and ACPI Timer
  • Table 4-17. F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers
  • Table 4-18. F2 Index xxh: PCI Header Registers for IDE Configuration 
  • Table 4-19. F2BAR+I/O Offset xxh: IDE Configuration Registers 
  • Table 4-20. F3 Index xxh: PCI Header Registers for XpressAUDIO 
  • Table 4-21. F3BAR+Memory Offset xxh: XpressAUDIO Configuration Registers 
  • Table 4-22. F4 Index xxh: PCI Header Registers for Video Controller Configuration 
  • Table 4-23. F4BAR+Memory Offset xxh: Video Controller Configuration Registers 
  • Table 4-24. F4BAR+Memory Offset 24h[22:12] Decode (Value of �N�)
  • Table 4-25. USB Index xxh: USB PCI Configuration Registers 
  • Table 4-26. USB BAR+Memory Offset xxh: USB Controller Registers 
  • Table 4-27. DMA Channel Control Registers 
  • Table 4-28. DMA Page Registers
  • Table 4-29. Programmable Interval Timer Registers
  • Table 4-30. Programmable Interrupt Controller Registers 
  • Table 4-31. Keyboard Controller Registers
  • Table 4-32. Real-Time Clock Registers
  • Table 4-33. Miscellaneous Registers 
  • Table 4-34. V-ACPI Registers 
  • Table 4-35. SETUP_IDX Values
  • Table 4-36. GPIO Mapping (0x10-0x17)
  • Table 4-37. IRQ Wakeup Status Mapping (0x30-0x3F)
  • Table 4-38. Commands (0x41-0x43, and 0x50)
  • Table 4-39. Signature/Length Block for 0x43
  • Table 4-40. I/O Block for 0x43
  • Table 4-41. Audio Soft SMI Emulation (0x60-0x63)
  • Table 4-42. Audio Power Control (0x64)
  • Table 5-1. Pins with Weak Internal Pull-Up
  • Table 5-2. Absolute Maximum Ratings
  • Table 5-3. Operating Conditions
  • Table 5-4. DC Characteristics 
  • Table 5-5. System Conditions Used to Determine CS5530A�s Current Used During the �On� State
  • Table 5-6. DC Characteristics During Power States
  • Table 5-7. Drive Level and Measurement Points for AC Characteristics
  • Table 5-8. AC Characteristics 
  • Table 5-9. Clock and Reset Specifications
  • Table 5-10. DCLK PLL Specifications
  • Table 5-11. CPU Interface Timing
  • Table 5-12. Audio Interface Timing
  • Table 5-13. USB Timing
  • Table 5-14. CRT Display Recommended Operating Conditions
  • Table 5-15. CRT Display Analog (DAC) Characteristics
  • Table 5-16. Display Miscellaneous Characteristics
  • Table 5-17. CRT, TFT/TV and MPEG Display Timing
  • Table 6-1. NAND Tree Test Selection
  • Table 6-2. NAND Tree Test Mode Pins
  • Table 6-3. I/O Test Selection
  • Table 6-4. I/O Test Sequence
  • Table A-1. Revision History
  • Table A-2. Edits to Create Revision 1.1