TL F 6528
5476DM5476DM7476
Dual
Master-Slave
J-K
Flip-Flops
with
Clear
Preset
and
Complementary
Outputs
June 1989
5476 DM5476 DM7476
Dual Master-Slave J-K Flip-Flops with Clear
Preset and Complementary Outputs
General Description
This device contains two independent positive pulse trig-
gered J-K flip-flops with complementary outputs The J and
K data is processed by the flip-flop after a complete clock
pulse While the clock is low the slave is isolated from the
master On the positive transition of the clock the data from
the J and K inputs is transferred to the master While the
clock is high the J and K inputs are disabled On the nega-
tive transition of the clock the data from the master is trans-
ferred to the slave The logic state of J and K inputs must
not be allowed to change while the clock is high The data is
transfered to the outputs on the falling edge of the clock
pulse A low logic level on the preset or clear inputs will set
or reset the outputs regardless of the logic levels of the
other inputs
Features
Y
Alternate Military Aerospace device (5476) is available
Contact a National Semiconductor Sales Office Distrib-
utor for specifications
Connection Diagram
Dual-In-Line Package
TL F 6528 1
Order Number 5476DMQB 5476FMQB
DM5476J DM5476W or DM7476N
See NS Package Number J16A N16E or W16A
Function Table
Inputs
Outputs
PR
CLR
CLK
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H
H
H
H
L
L
Q
0
Q
0
H
H
H
L
H
L
H
H
L
H
L
H
H
H
H
H
Toggle
H
e
High Logic Level
L
e
Low Logic Level
X
e
Either Low or High Logic Level
e
Positive pulse data The J and K inputs must be held constant while
the clock is high Data is transfered to the outputs on the falling edge of the
clock pulse
e
This configuration is nonstable that is it will not persist when the preset
and or clear inputs return to their inactive (high) level
Q
0
e
The output logic level before the indicated input conditions were es-
tablished
Toggle
e
Each output changes to the complement of its previous level on
each complete active high level clock pulse
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
5 5V
Operating Free Air Temperature Range
DM54 and 54
b
55 C to
a
125 C
DM74
0 C to
a
70 C
Storage Temperature Range
b
65 C to
a
150 C
Note
The ``Absolute Maximum Ratings'' are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ``Electrical Characteristics''
table are not guaranteed at the absolute maximum ratings
The ``Recommended Operating Conditions'' table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
Parameter
DM5476
DM7476
Units
Min
Nom
Max
Min
Nom
Max
V
CC
Supply Voltage
4 5
5
5 5
4 75
5
5 25
V
V
IH
High Level Input Voltage
2
2
V
V
IL
Low Level Input Voltage
0 8
0 8
V
I
OH
High Level Output Current
b
0 4
b
0 4
mA
I
OL
Low Level Output Current
16
16
mA
f
CLK
Clock Frequency (Note 6)
0
15
0
15
MHz
t
W
Pulse Width
Clock High
20
20
(Note 6)
Clock Low
47
47
ns
Preset Low
25
25
Clear Low
25
25
t
SU
Input Setup Time (Notes 1
6)
0
u
0
u
ns
t
H
Input Hold Time (Notes 1
6)
0
v
0
v
ns
T
A
Free Air Operating Temperature
b
55
125
0
70
C
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 2)
V
I
Input Clamp Voltage
V
CC
e
Min I
I
e b
12 mA
b
1 5
V
V
OH
High Level Output
V
CC
e
Min I
OH
e
Max
2 4
3 4
V
Voltage
V
IL
e
Max V
IH
e
Min
V
OL
Low Level Output
V
CC
e
Min I
OL
e
Max
0 2
0 4
V
Voltage
V
IH
e
Min V
IL
e
Max
I
I
Input Current
Max
V
CC
e
Max V
I
e
5 5V
1
mA
Input Voltage
I
IH
High Level Input
V
CC
e
Max
J K
40
Current
V
I
e
2 4V
Clock
80
m
A
Clear
80
Preset
80
I
IL
Low Level Input
V
CC
e
Max
J K
b
1 6
Current
V
I
e
0 4V
Clock
b
3 2
mA
(Note 5)
Clear
b
3 2
Preset
b
3 2
I
OS
Short Circuit
V
CC
e
Max
DM54
b
20
b
55
mA
Output Current
(Note 3)
DM74
b
18
b
55
I
CC
Supply Current
V
CC
e
Max (Note 4)
18
34
mA
Note 1
The symbol (
u v
) indicates the edge of the clock pulse is used for reference (
u
) for rising edge (
v
) for falling edge
Note 2
All typicals are at V
CC
e
5V T
A
e
25 C
Note 3
Not more than one output should be shorted at a time
Note 4
With all outputs open I
CC
is measured with the Q and Q outputs high in turn At the time of measurement the clock input is grounded
Note 5
Clear is measured with preset high and preset is measured with clear high
Note 6
T
A
e
25 C and V
CC
e
5V
2
Switching Characteristics
at V
CC
e
5V and T
A
e
25 C (See Section 1 for Test Waveforms and Output Load)
From (Input)
R
L
e
400X
Symbol
Parameter
To (Output)
C
L
e
15 pF
Units
Min
Max
f
MAX
Maximum Clock
15
MHz
Frequency
t
PHL
Propagation Delay Time
Preset
40
ns
High to Low Level Output
to Q
t
PLH
Propagation Delay Time
Preset
25
ns
Low to High Level Output
to Q
t
PHL
Propagation Delay Time
Clear
40
ns
High to Low Level Output
to Q
t
PLH
Propagation Delay Time
Clear
25
ns
Low to High Level Output
to Q
t
PHL
Propagation Delay Time
Clock to
40
ns
High to Low Level Output
Q or Q
t
PLH
Propagation Delay Time
Clock to
25
ns
Low to High Level Output
Q or Q
Physical Dimensions
inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 5476DMQB or DM5476J
NS Package Number J16A
3
5476DM5476DM7476
Dual
Master-Slave
J-K
Flip-Flops
with
Clear
Preset
and
Complementary
Outputs
Physical Dimensions
inches (millimeters) (Continued)
16-Lead Molded Dual-In-Line Package (N)
Order Number DM7476N
NS Package Number N16E
16-Lead Ceramic Flat Package (W)
Order Number 5476FMQB or DM7476W
NS Package Number W16A
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SEMICONDUCTOR CORPORATION As used herein
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failure to perform when properly used in accordance
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with instructions for use provided in the labeling can
effectiveness
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to the user
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