TL F 6438

DM74LS962

(DM86LS62)

Dual

Rank

8-Bit

TRI-STATE

Shift

August 1991

DM74LS962 (DM86LS62)
Dual Rank 8-Bit TRI-STATE

Shift Register

General Description

These circuits are TRI-STATE edge-triggered 8-bit I O reg-
isters in parallel with 8-bit serial shift registers which are
capable of operating in any of the following modes parallel
load from I O pins to register ``A'' parallel transfer down
from register ``A'' to serial shift register ``B'' parallel transfer
up from shift register ``B'' to register ``A'' serial shift of regis-
ter ``B'' or exchange data between register ``A'' and shift
register ``B'' Since the registers are edge-triggered by the
positive transition of the clock the control lines which deter-
mine the mode or operation are completely independent of
the logic level applied to the clock Designed for bus-orient-
ed systems these circuits have their TRI-STATE inputs and
outputs on the same pins

Features

Registers are edge-triggered by the positive transition
of the clock

All inputs are PNP transistors

Input disable dominates over output disable

Output high impedance state does not impede any oth-
er mode of operation

8-bit I O pins are TRI-STATE buffers

Typical shift frequency is 36 MHz

Typical power dissipation is 305 mW

All control inputs are active when in an ``L'' logic state

Devices can be cascaded into N-bit word

Connection Diagram

Dual-In-Line Package

TL F 6438 � 1

Top View

Order Number DM74LS962N or DM86LS62N

See NS Package Number N18A

Pin Description

DIS

Output disable

Serial input

DIS

Input disable

DIS

Transfer up disable

DIS

Transfer down disable

DIS

Shift disable

Serial output

CLK

Clock

GND

Ground

I O 1

I O 8

8-bit I O pins

Supply Voltage

TRI-STATE

is a registered trademark of National Semiconductor Corporation

C1995 National Semiconductor Corporation

RRD-B30M105 Printed in U S A

Absolute Maximum Ratings

(Note)

Supply Voltage

Input Voltage

Operating Free Air Temperature Range

DM74LS DM86LS

0 C to

70 C

Storage Temperature Range

65 C to

150 C

Lead Temperature (Soldering 10 seconds)

300 C

Note

The ``Absolute Maximum Ratings'' are those values

beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ``Electrical Characteristics''
table are not guaranteed at the absolute maximum ratings
The ``Recommended Operating Conditions'' table will define
the conditions for actual device operation

Recommended Operating Conditions

Symbol

Parameter

Min

Typ

Max

Units

Supply Voltage

4 75

5 25

High-Level Input Voltage

Low-Level Input Voltage

0 8

High-Level Output Current

5 2

Low-Level Output Current

CLOCK

Clock Frequency (Note 5)

MHz

Clock

High Pulse Width (Note 5)

Pulse

Low Pulse Width (Note 5)

SET-UP

Data Set-Up Time (Note 5)

HOLD

Data Hold Time (Note 5)

Free Air Operating Temperature

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Symbol

Parameter

Conditions (1)

Min

Typ (2)

Max

Units

Input Clamp Voltage

Min I

e b

18 mA

1 5

High-Level Output Voltage

Min V

2 V

e b

2 6 mA

Max

e b

5 2 mA

2 4

Low-Level Output Voltage

Min V

2 V

8 mA

0 25

0 4

Max

16 mA

0 35

0 5

Input Current at Maximum

Max V

5 5V

0 1

Input Voltage

High-Level Input Current

Max V

2 7V

Low-Level Input Current

Max V

0 4V

Short-Circuit Output Current

Max (3)

100

Supply Current

Max (4)

OFF

TRI-STATE I O Current

Max V

2 4V

0 4V

Note 1

For conditions shown as min or max use the appropriate value specified under recommended operating conditions

Note 2

All typical values are at V

5V T

25 C

Note 3

Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second

Note 4

is measured with serial output open the clock and shift disable input at 2 4V All other control inputs and I O pins grounded

Note 5

25 C and V

Switching Characteristics

5V and T

25 C

Symbol

Parameter

Conditions

Min

Max

Units

MAX

Maximum Clock Frequency

MHz

PLH

Propagation Delay Time Low-to-High-Level

from Clock to Any Outputs

PHL

Propagation Delay Time High-to-Low Level

from Clock to Any Outputs

15 pF R

1 kX

ENABLE

Enable Time from Any Control Inputs

DISABLE

Disable Time from Any Control Inputs

Output Enable Time to High Level

Output Enable to Low Level

Output Disable Time from High Level

5 pF R

1 kX

Output Disable Time from Low Level

Logic Diagram

TL F 6438 � 2

Function

Table

DIS

CLK

8-Bit

Content

Upper

Reg

``A''

Content

Lower

Serial

Shift

Reg

``B''

Comments

Pins

Hi-Z

Stable

state

Output

Input

Entering

data

from

reg

``A''

Hi-Z

Transfer

data

from

reg

``B''

reg

``A''

Output

Input

www

DOR

xxx

Reg

``A''

will

data

from

reg

``B''

Hi-Z

Transfer

data

down

from

reg

``A''

reg

``B''

Output

Input

Entering

data

and

transfer

down

Hi-Z

(1)

Exchange

data

between

registers

Output

(2)

Beside

data

exchanging

reg

``A''

Input

www

DOR

xxx

(3)

will

``OR''

data

from

and

reg

``B''

Hi-Z

Serial

shifting

the

lower

reg

``B''

Output

Input

Entering

data

and

serial

shifting

Hi-Z

Transfer

and

serial

shifting

Output

Input

www

DOR

xxx

DOR

function

and

serial

shifting

Don't

Care

Hi-ZOutputInput

High

impedance

stateoutput

stateinput

state

a8b1

The

content

the

upper

``A''the

lower

serial

shift

``B''

before

the

most

recent

transition

the

clock

The

level

steady

state

inputs

the

pins

DOR

``Data

ORing

function''

ORing

data

from

both

pins

and

``B''

Data

the

serial

input

Электронный компонент: DM74LS962