TL F 9756
DP5380
Asynchronous
SCSI
Interface
(ASI)
May 1989
DP5380 Asynchronous SCSI Interface (ASI)
General Description
The DP5380 ASI is a CMOS device designed to provide a
low cost high performance Small Computer Systems Inter-
face It complies with the ANS X3 131-1986 SCSI standard
as defined by the ANSI X3T9 2 committee It can act as
both INITIATOR and TARGET making it suitable for any
application The ASI supports selection reselection arbitra-
tion and all other bus phases High-current open-drain driv-
ers on chip reduce application chip count by interfacing di-
rect to the SCSI bus An on-chip oscillator provides all tim-
ing delays
The DP5380 is pin and program compatible with the NMOS
NCR5380 device NCR5380 or AM5380 applications can
use it with no changes to hardware or software The
DP5380 is available in a 40-pin DIP or a 44-pin PCC
The ASI is intended to be used in a microprocessor based
application and achieves maximum performance with a
DMA controller The device is controlled by reading and
writing several internal registers A standard non-multi-
plexed address and data bus easily fits any mP environment
Data transfers can be performed by programmed-I O pseu-
do-DMA or via a DMA controller The ASI easily interfaces
to a DMA controller using normal or Block Mode The ASI
can be used in either a polled or interrupt-driven environ-
ment
Features
SCSI Interface
Y
Supports TARGET and INITIATOR roles
Y
Parity generation with optional checking
Y
Arbitration support
Y
Direct control monitoring of all SCSI signals
Y
High current outputs drive SCSI bus directly
Y
Faster and improved timing
Y
Very low SCSI bus loading
mP Interface
Y
Memory or I O-mapped control transfers
Y
Programmed-I O or DMA data transfers
Y
Normal or Block-mode DMA
Y
Fast DMA handshake timing
Connection Diagram
TL F 9756 1
Table of Contents
1 0 FUNCTIONAL DESCRIPTION
2 0 PIN DESCRIPTION
3 0 REGISTER DESCRIPTION
4 0 DEVICE OPERATION
5 0 INTERRUPTS
6 0 RESET CONDITIONS
7 0 APPLICATION GUIDE
8 0 ABSOLUTE MAXIMUM RATINGS
9 0 DC ELECTRICAL CHARACTERISTICS
10 0 AC ELECTRICAL CHARACTERISTICS
A1 FLOWCHARTS
A2 REGISTER CHART
TRI-STATE
is a registered trademark of National Semiconductor Corporation
PAL
is a registered trademark of and used under license from Monolithic Memories Inc
C1995 National Semiconductor Corporation
RRD-B30M115 Printed in U S A
1 0 Functional Description
1 1 OVERVIEW
The ASI is designed to be used as a peripheral device in a
m
P-based application and appears as a number of read
write registers Write registers are programmed to select de-
sired functions Status registers provide indication of operat-
ing conditions
For best performance a DMA controller can be easily inter-
faced directly to the ASI The ASI provides request ac-
knowledge and wait-state signals for the DMA interface
The SCSI bus is easily controlled via the ASI registers Any
bus signal may be asserted or deasserted via a bit in the
appropriate register and the state of every signal is avail-
able by reading registers This direct control over SCSI sig-
nals allows the user to implement all or part of the protocol
in firmware The ASI provides hardware support for much of
the protocol
The ASI provides the following SCSI support
Programmed-I O transfers for all eight information trans-
fer types with or without parity
Data transfers via DMA in either block or non-block
mode The DMA interface supports most devices
Individual setting resetting and monitoring of every SCSI
bus signal
Automatic release of the bus for BSY loss from a TAR-
GET SCSI RST and lost arbitration
Automatic bus arbitration
the mP has only to check for
highest priority
Selection or Reselection of any bus device The ASI will
respond to both Selection and Reselection
Optional automatic monitoring of the BSY signal from a
TARGET with an interrupt after releasing control of the
bus
Figure 1 shows an ASI in a typical application a low cost
embedded SCSI disk controller In this application the 8051
single-chip mP acts as the controller and the dual DMA
channels in the DP8475 allow one for the disk data and the
other for SCSI data The PAL
provides chip selection as
well as determining who has control of the bus The advan-
tage of using a mP with on-board ROM is that there is more
free time on the external bus
TL F 9756 2
FIGURE 1 ASI Application
2
1 0 Functional Description
(Continued)
1 2 mP INTERFACE
Figure 2 shows a block diagram of the ASI Key blocks with-
in the ASI are Read Write registers with associated decode
and control logic interrupt and DMA logic SCSI bus arbitra-
tion logic SCSI drivers receivers with parity and the SCSI
data input and output registers The ASI has three interfac-
es one to SCSI one to a DMA controller and the third to a
m
P The internal registers control all operations of the ASI
The mP interface consists of non-multiplexed address and
data busses with associated control signals Address de-
code logic selects a register for reading or writing The ad-
dress lines A0 2 select the register for mP accesses while
for DMA accesses the address lines are ignored
The register bank consists of twelve registers mapped into
an address space of eight locations Upon an external chip
reset the registers are cleared (all zeroes)
1 3 DMA INTERFACE
The DMA logic interfaces to single-cycle block mode flow-
through or fly-by controllers Single byte transfers are ac-
complished via the DRQ DACK handshake signals Block
mode transfers use the READY output to control the speed
(insert wait-states) An End Of Process (EOP) input from the
DMA controller signals the ASI to halt DMA transfers An
interrupt can be generated for DMA completion or an error
(see Section 5 0) All DMA data passes through the SCSI
data input and output registers automatically selected dur-
ing DMA cycles
1 4 SCSI INTERFACE
The ASI contains all logic required to interface directly to the
SCSI bus Direct control and monitoring of all SCSI signals
is provided The state of each SCSI signal may be deter-
mined by reading a register which continuously reflects the
state of the bus Each signal may be asserted by writing a
ONE to the appropriate bit
The ASI includes logic to automatically handle SCSI timing
sequences too fast for mP control In particular there is
hardware support for DMA transfers bus arbitration selec-
tion reselection bus phase monitoring BSY monitoring for
bus disconnection bus reset and parity generation and
checking
TL F 9756 3
FIGURE 2 ASI Block Diagram
3
1 0 Functional Description
(Continued)
The ASI arbitration logic controls arbitration for use of the
SCSI bus The mP programs the SCSI device ID into the
ASI then sets the ARBITRATE bit The INITIATOR COM-
MAND REGISTER (ICR) is read to determine when arbitra-
tion has started and whether it is won or lost
The BSY signal is continously monitored to detect bus dis-
connection and bus free phases The ASI incorporates an
on-board oscillator to determine Bus Settle Bus Free and
Arbitration Delays The oscillator tolerance guarantees all
timing to be within the SCSI specification
The ASI incorporates high-current drivers and SCHMITT
trigger receivers for interfacing directly to the SCSI bus This
feature reduces the chip count of any SCSI application
1 5 PARITY
The ASI provides for parity protection on the SCSI interface
The data bus has eight data bits and one parity bit The
parity may be enabled via a register bit A parity error can be
programmed to cause an interrupt
2 0 Pin Descriptions
Symbol
DIP
PCC
Type
Function
CS
21
24
I
Chip Select
an active low enable for read or write operations accessing the register
selected by A0
2
A0
2
30 32 33
33 36 37
I
Address 0
2
these three signals are used with CS RD and WR to address a
register for read or write
RD
24
27
I
Read
an active low enable for reading an internal register selected by A0
2 and
enabled by CS It also selects the Input Data Register when used with DACK
WR
29
32
I
Write
an active low enable for writing an internal register selected by A0
2 and
enabled by CS It also selects the Output Data Register when used with DACK
RESET
28
31
I
Reset
an active low input with a Schmitt trigger Clears all internal registers (SCSI
RST unaffected)
D0
7
1 40 34
2 44 38
I O
Data 0
7
bidirectional TRI-STATE signals connecting the active high mP data
bus to the internal registers
INT
23
26
O
Interrupt
an active high output to the mP when an error has occurred an event
requires service or has completed
DRQ
22
25
O
DMA Request
an active high output asserted when the data register is ready to read
or written DRQ occurs only if DMA mode is enabled The signal is cleared by DACK
DACK
26
29
I
DMA Acknowledge
an active low input that resets DRQ and addresses the data
registers for input or output transfers DACK is used instead of CS by the DMA
controller
READY
25
28
O
Ready
an active high output used to control the speed of block mode DMA transfers
Ready goes active when the chip is ready to send receive data and remains inactive
after the transfer until the byte is sent or until the DMA mode bit is reset
EOP
27
30
I
End Of Process
an active low signal that terminates a block of DMA transfers It
should be asserted during the transfer of the last byte
DB0
7
9
2 10
10
3 11
I O
DB0
7 DBP
SCSI data bus with parity DB7 is the MSB and is the highest priority
during arbitration Parity is ODD Parity is always generated and can be optionally
DBP
checked Parity is not valid during arbitration
RST
16
18
I O
Reset
SCSI reset monitored and can be set by ASI
BSY
13
15
I O
Busy
indicates the SCSI bus is being used Can be driven by TARGET or
INITIATOR
SEL
12
14
I O
Select
used by the INITIATOR to select a TARGET or by the TARGET to reselect an
INITIATOR
ACK
14
16
I O
Acknowledge
driven by the INITIATOR and received by the TARGET as part of the
REQ ACK handshake
ATN
15
17
I O
Attention
driven by the INITIATOR to indicate an attention condition to the
TARGET
4
2 0 Pin Descriptions
(Continued)
Symbol
DIP
PCC
Type
Function
REQ
20
22
I O
Request
driven by the TARGET and received by the INITIATOR as part of the REQ
ACK handshake
I O
17
19
I O
Input Output
driven by the TARGET to control the direction of transfers on the
SCSI bus This signal also distinguishes between selection and reselection
C D
18
20
I O
Command Data
driven by the TARGET to indicate whether command or data bytes
are being transferred
MSG
19
21
I O
Message
driven by the TARGET during message phase to identify message bytes
on the bus
VCC
31
35
VCC GND
a
5V DC is required Because of very large switching currents good
decoupling and power distribution is mandatory
GND
11
12 13
2 1 Connection Diagrams
TL F 9756 4
Order Number DP5380N
See NS Package Number N40A
TL F 9756 5
Order Number DP5380V
See NS Package Number V44A
5
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