TL F 6824
DP8212DP8212M
8-Bit
InputOutput
Port
June 1988
DP8212 DP8212M 8-Bit Input Output Port
General Description
The DP8212 DP8212M is an 8-bit input output port con-
tained in a standard 24-pin dual-in-line package The device
which is fabricated using Schottky Bipolar technology is
part of National Semiconductor's 8080A support family The
DP8212 DP8212M can be used to implement latches gat-
ed buffers or multiplexers Thus all of the major peripheral
and input output functions of a microcomputer system can
be implemented with this device
The
DP8212 DP8212M
includes
an
8-bit
latch
with
TRI-STATE
output buffers and device selection and con-
trol logic Also included is a service request flip-flop for the
generation and control of interrupts to the microprocessor
Features
Y
8-Bit data latch and buffer
Y
Service request flip-flop for generation and control of
interrupts
Y
0 25 mA input load current
Y
TRI-STATE TTL output drive capability
Y
Outputs sink 15 mA
Y
Asynchronous latch clear
Y
3 65V output for direct interface to INS8080A
Y
Reduces system package count by replacing buffers
latches and multiplexers in microcomputer systems
8080A Microcomputer Family Block Diagram
TL F 6824 1
TRI-STATE
is a registered trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
b
65 C to
a
160 C
All Output or Supply Voltages
b
0 5V to
a
7V
All Input Voltages
b
1 0V to 5 5V
Output Currents
125 mA
Maximum Power Dissipation at 25 C
Cavity Package
1903 mW
Molded Package
2005 mW
Derate cavity package 12 7 mW C above 25 C derate molded package
16 0 mW C above 25 C
Operating Conditions
Min
Max
Units
Supply Voltage (V
CC
)
DP8212M
4 50
5 50
V
DC
DP8212
4 75
5 25
V
DC
Operating Temperaure (T
A
)
DP8212M
b
55
a
125
C
DP8212
0
a
75
C
Note
Maximum ratings indicate limits beyond which perma-
nent damage may occur Continuous operation at these lim-
its is not intended and should be limited to those conditions
specified under DC electrical characteristics
Electrical Characteristics
Min
s
T
A
s
Max Min
s
V
CC
s
Max unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
I
F
Input Load Current
V
F
e
0 45V
b
0 25
mA
STB DS2 CLR DI
1
DI
8
Inputs
I
F
Input Load Current MD Input
V
F
e
0 45V
b
0 75
mA
I
F
Input Load Current DS1 Input
V
F
e
0 45V
b
1 0
mA
I
R
Input Leakage Current
V
R
e
V
CC
Max
10
m
A
STB DS2 CLR DI
1
DI
8
Inputs
I
R
Input Leakage Current MD Input
V
R
e
V
CC
Max
30
m
A
I
R
Input Leakage Current DS1 Input
V
R
e
V
CC
Max
40
m
A
V
C
Input Forward Voltage Clamp
I
C
e b
5 mA
b
1
V
V
IL
Input ``Low'' Voltage
DP8212M
0 08
V
DP8212
0 85
V
V
IH
Input ``High'' Voltage
2 0
V
V
OL
Output ``Low'' Voltage
I
OL
e
10 mA
DP8212M
0 45
V
I
OL
e
15 mA
DP8212
0 45
V
V
OH
Output ``High'' Voltage
I
OH
e
0 5 mA
DP8212M
3 40
4 0
V
I
OH
e
1 0 mA
DP8212
3 65
4 0
V
I
SC
Short-Circuit Output Current
V
O
e
0V V
CC
e
5V
b
15
b
75
mA
l
I
O
l
Output Leakage Current High
V
O
e
0 45V V
CC
Max
20
m
A
Impedance State
I
CC
Power Supply Current
DP8212M
90
145
mA
DP8212
90
130
mA
Capacitance
F
e
1 MHz V
BIAS
e
2 5V V
CC
e
5V T
A
e
25 C
Symbol
Parameter
Min
Typ
Max
Units
C
IN
DS1 MD Input Capacitance
9
12
pF
C
IN
DS2 CLR STB DI
1
DI
8
Input Capacitance
5
9
pF
C
OUT
DO1 DO8 Output Capacitance
8
12
pF
This parameter is sampled and not 100% tested
2
Switching Characteristics
Min
s
T
A
s
Max Min
s
V
CC
s
Max
Symbol
Parameter
Conditions
DP8212M
DP8212
Units
Min
Max
Min
Max
t
PW
Pulse Width
40
30
ns
t
PD
Data to Output Delay
(Note 1)
30
30
ns
t
WE
Write Enable to Output Delay
(Note 1)
50
40
ns
t
SET
Data Set-Up Time
20
15
ns
t
H
Data Hold Time
30
20
ns
t
R
Reset to Output Delay
(Note 1)
55
40
ns
t
S
Set to Output Delay
(Note 1)
35
30
ns
t
E
Output Enable Disable Time
(Note 2)
50
45
ns
t
C
Clear to Output Delay
(Note 1)
65
55
ns
Note 1
C
L
e
30 pF
Note 2
C
L
e
30 pF except for DP8212M
t
E (DISABLE)
C
L
e
5 pF
Switching Conditions
1 Input Pulse Amplitude
e
2 5V
2 Input Rise and Fall Times
e
5 ns
3 Between 1V and 2V Measurements made at 1 5V with 15 mA
30 pF Test Load
4 C
L
includes jig and probe capacitance
5 C
L
e
30 pF
6 C
L
e
30 pF except for DP8212M t
E (DISABLE)
C
L
e
5 pF
Test Load
TL F 6824 2
Alternate Test Load
(Refer to Timing Diagram)
TL F 6824 3
3
Timing Diagram
TL F 6824 4
4
Logic Diagram
TL F 6824 5
5
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