TL F 8795
DP8308
8-Bit
TRI-STATE
Bidirectional
Transceiver
(Non-Inverting)
February 1996
DP8308 8-Bit TRI-STATE
Bidirectional Transceiver (Non-Inverting)
General Description
The DP8308 is a high speed Schottky 8-bit TRI-STATE bidi-
rectional transceiver designed to provide bidirectional drive
for bus oriented microprocessor and digital communications
systems It is capable of sinking 16 mA on the A ports and
48 mA on the B ports (bus ports) PNP inputs for low input
current and an increased output high (V
OH
) level allow com-
patibility with MOS CMOS and other technologies that
have a higher threshold and less drive capabilities In addi-
tion it features glitch-free power up down on the B port
preventing erroneous glitches on the system bus in power
up or down
DP8308 is featured with Transmit (T) and Receive (R)
control inputs
Features
Y
8-bit bidirectional data flow reduces system package
count
Y
Bidirectional TRI-STATE inputs outputs interface with
bus oriented systems
Y
PNP inputs reduce input loading
Y
Output high voltage interfaces with TTL
MOS
and
CMOS
Y
48 mA 300 pF bus drive capability
Y
Pinouts simplify system interconnections
Y
Independent T and R controls for versatility
Y
Compact 20-pin dual-in-line package
Y
Bus port glitch free power up down
Logic and Connection Diagrams
TL F 8795 1
Dual-In-Line Package
TL F 8795 2
Top View
Order Number DP8308N
See NS Package Number N20A
Logic Table
Control Inputs
Resulting Conditions
Transmit
Receive
A Port
B Port
1
0
OUT
IN
0
1
IN
OUT
1
1
TRI-STATE
TRI-STATE
0
0
Both Active
This is not an intended logic condition and may cause oscillations
TRI-STATE
is a registered trademark of National Semiconductor Corp
C1996 National Semiconductor Corporation
RRD-B30M36 Printed in U S A
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Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
5 5V
Output Voltage
5 5V
Storage Temperature
b
65 C to
a
150 C
Maximum Power Dissipation at 25 C
Cavity Package
1667 mW
Molded Package
1832 mW
Lead Temperature (soldering 4 sec )
260 C
Derate cavity package 11 1 mW C above 25 C derate molded package
14 7 mW C above 25 C
Recommended Operating
Conditions
Min
Max
Units
Supply Voltage (V
CC
)
DP7308
4 5
5 5
V
DP8308
4 75
5 25
V
Temperature (T
A
)
DP7308
b
55
a
125
C
DP8308
0
a
70
C
DC Electrical Characteristics
(Notes 2 and 3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
A PORT (A0 A7)
V
IH
Logical ``1'' Input Voltage
T
e
V
IL
R
e
2 0V
2 0
V
V
IL
Logical ``0'' Input Voltage
T
e
V
IL
R
e
2 0V
DP8308
0 8
V
DP7308
0 7
V
V
OH
Logical ``1'' Output Voltage
T
e
2 0V R
e
V
IL
I
OH
e b
0 4 mA
V
CC
b
1 15
V
CC
b
0 7
V
I
OH
e b
3 mA
2 7
3 95
V
V
OL
Logical ``0'' Output Voltage
T
e
2 0V
I
OL
e
16 mA (8308)
0 35
0 5
V
R
e
V
IL
I
OL
e
8 mA (both)
0 3
0 4
V
I
OS
Output Short Circuit
T
e
2 0V R
e
V
IL
V
O
e
0V
b
10
b
38
b
75
mA
Current
V
CC
e
Max (Note 4)
I
IH
Logical ``1'' Input Current
T
e
V
IL
R
e
2 0V V
IH
e
2 7V
0 1
80
m
A
I
I
Input Current at Maximum
R
e
T
e
2 0V V
CC
e
Max V
IH
e
5 25V
1
mA
Input Voltage
I
IL
Logical ``0'' Input Current
T
e
V
IL
R
e
2 0V V
IN
e
0 4V
b
70
b
200
m
A
V
CLAMP
Input Clamp Voltage
T
e
R
e
2 0V I
IN
e b
12 mA
b
0 7
b
1 5
V
I
OD
Output Input
T
e
R
e
2 0V
V
IN
e
0 4V
b
200
m
A
TRI-STATE Current
V
IN
e
4 0V
80
m
A
B PORT (B0 B7)
V
IH
Logical ``1'' Input Voltage
T
e
2 0V R
e
V
IL
2 0
V
V
IL
Logical ``0'' Input Voltage
T
e
2 0V R
e
V
IL
DP8308
0 8
V
DP7308
0 7
V
V
OH
Logical ``1'' Output Voltage
T
e
V
IL
R
e
2 0V
I
OH
e b
0 4 mA
V
CC
b
1 15
V
CC
b
0 8
V
I
OH
e b
5 mA
2 7
3 9
V
I
OH
e b
10 mA
2 4
3 6
V
V
OL
Logical ``0'' Output Voltage
T
e
V
IL
R
e
2 0V
I
OL
e
20 mA
0 3
0 4
V
I
OL
e
48 mA
0 4
0 5
V
I
OS
Output Short Circuit
T
e
V
IL
R
e
2 0V V
O
e
0V
b
25
b
50
b
150
mA
Current
V
CC
e
Max (Note 4)
I
IH
Logical ``1'' Input Current
T
e
2 0V R
e
V
IL
V
IH
e
2 7V
0 1
80
m
A
I
I
Input Current at Maximum
T
e
R
e
2 0V V
CC
e
Max V
IH
e
5 25V
1
mA
Input Voltage
I
IL
Logical ``0'' Input Current
T
e
2 0V R
e
V
IL
V
IN
e
0 4V
b
70
b
200
m
A
V
CLAMP
Input Clamp Voltage
T
e
R
e
2 0V I
IN
e b
12 mA
b
0 7
b
1 5
V
I
OD
Output Input
T
e
R
e
2 0V
V
IN
e
0 4V
b
200
m
A
TRI-STATE Current
V
IN
e
4 0V
a
200
m
A
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2
DC Electrical Characteristics
(Notes 2 and 3) (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CONTROL INPUTS T R
V
IH
Logical ``1'' Input Voltage
2 0
V
V
IL
Logical ``0'' Input Voltage
DP8308
0 8
V
DP7308
0 7
V
I
IH
Logical ``1'' Input Current
V
IH
e
2 7V
0 5
20
m
A
I
I
Maximum Input Current
V
CC
e
Max V
IH
e
5 25V
1 0
mA
I
IL
Logical ``0'' Input Current
V
IL
e
0 4V
R
b
0 1
b
0 25
mA
T
b
0 25
b
0 5
mA
V
CLAMP
Input Clamp Voltage
I
IN
e b
12 mA
b
0 8
b
1 5
V
POWER SUPPLY CURRENT
I
CC
Power Supply Current
T
e
R
e
2 0V V
IN
e
0 4V V
CC
e
Max
70
100
mA
T
e
V
INA
e
0 4V R
e
2V V
CC
e
Max
90
140
mA
AC Electrical Characteristics
V
CC
e
5V T
A
e
25 C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
A PORT DATA MODE SPECIFICATIONS
t
PDHLA
Propagation Delay to a Logical ``0'' from
T
e
2 4V R
e
0 4V
(Figure A)
14
18
ns
B Port to A Port
R1
e
1k R2
e
5k C1
e
30 pF
t
PDLHA
Propagation Delay to a Logical ``1'' from
T
e
2 4V R
e
0 4V
(Figure A)
13
18
ns
B Port to A Port
R1
e
1k R2
e
5k C1
e
30 pF
t
PLZA
Propagation Delay from a Logical ``0'' to
B0 to B7
e
0 4V T
e
2 4V
(Figure B)
11
15
ns
TRI-STATE from R to A Port
S3
e
1 R5
e
1k C4
e
15 pF
t
PHZA
Propagation Delay from a Logical ``1'' to
B0 to B7
e
2 4V T
e
2 4V
(Figure B)
8
15
ns
TRI-STATE from R to A Port
S3
e
0 R5
e
1k C4
e
15 pF
t
PZLA
Propagation Delay from TRI-STATE to
B0 to B7
e
0 4V T
e
2 4V
(Figure B)
24
35
ns
a Logical ``0'' from R to A Port
S3
e
1 R5
e
1k C4
e
30 pF
t
PZHA
Propagation Delay from TRI-STATE to
B0 to B7
e
2 4V T
e
2 4V
(Figure B)
21
30
ns
a Logical ``1'' from R to A Port
S3
e
0 R5
e
5k C4
e
30 pF
B PORT DATA MODE SPECIFICATIONS
t
PDHLB
Propagation Delay to a Logical ``0'' from
T
e
0 4V R
e
2 4V
(Figure A)
A Port to B Port
R1
e
100X R2
e
1k C1
e
300 pF
18
23
ns
R1
e
667X R2
e
5k C1
e
45 pF
11
18
ns
t
PDLHB
Propagation Delay to a Logical ``1'' from
T
e
0 4V R
e
2 4V
(Figure A)
A Port to B Port
R1
e
100X R2
e
1k C1
e
300 pF
16
23
ns
R1
e
667X R2
e
5k C1
e
45 pF
11
18
ns
t
PLZB
Propagation Delay from a Logical ``0'' to
A0 to A7
e
0 4V R
e
2 4V
(Figure B)
13
18
ns
TRI-STATE from T to B Port
S3
e
1 R5
e
1k C4
e
15 pF
t
PHZB
Propagation Delay from a Logical ``1'' to
A0 to A7
e
2 4V R
e
2 4V
(Figure B)
8
15
ns
TRI-STATE from T to B Port
S3
e
0 R5
e
1k C4
e
15 pF
t
PZLB
Propagation Delay from TRI-STATE to
A0 to A7
e
0 4V R
e
2 4V
(Figure B)
a Logical ``0'' from T to B Port
S3
e
1 R5
e
100X C4
e
300 pF
25
35
ns
S3
e
1 R5
e
667X C4
e
45 pF
17
25
ns
t
PZHB
Propagation Delay from TRI-STATE to
A0 to A7
e
2 4V R
e
2 4V
(Figure B)
a Logical ``1'' from T to B Port
S3
e
0 R5
e
1k C4
e
300 pF
24
35
ns
S3
e
0 R5
e
5k C4
e
45 pF
17
25
ns
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AC Electrical Characteristics
(Continued)
Note 1
``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed Except for ``Operating Temperature
Range'' they are not meant to imply that the devices should be operated at these limits The table of ``Electrical Characteristics'' provides conditions for actual
device operation
Note 2
Unless otherwise specified min max limits apply across the supply and temperature range listed in the table of Recommended Operating Conditions
All typical values given are for V
CC
e
5V and T
A
e
25 C
Note 3
All currents into device pins are positive all currents out of device pins are negative All voltages are referenced to ground unless otherwise specified
Note 4
Only one output at a time should be shorted
Switching Time Waveforms and AC Test Circuits
TL F 8795 3
TL F 8795 4
Note
C1 includes test fixture capacitance
FIGURE A Propagation Delay from A Port to B Port or from B Port to A Port
TL F 8795 5
TL F 8795 6
Note
C4 includes test fixture capacitance Port input is in a fixed logical condition See AC Table
FIGURE B Propagation Delay to from TRI-STATE from R to A Port and T to B Port
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