TL F 11122
DP83200EB
FDDI
AT
Evaluation
Kit
February 1991
DP83200EB
FDDI AT Evaluation Kit
General Description
The DP83200EB FDDI is a complete design evaluation kit
(using an AT or compatible platform) that includes hard-
ware software and application documentation to imple-
ment a single node compliant with an ANSI X3T9 5 FDDI
network The kit has been designed to demonstrate the ca-
pabilities of National Semiconductor's FDDI chip set
It contains a Link card and MAC card that together imple-
ment one FDDI Single Attach node
The Evaluation Boards allow evaluation of the many capa-
bilities of the chip set and serve as an educational tool for
customers designing products with the FDDI chip set High
performance as a goal was sacrificed at the expense of
simplicity and accessibility There are many laboratories
around the world with a spare IBM
PC
or compatible
These boards allow users to experiment and gain experi-
ence with the FDDI chip set in order to unleash its capabili-
ties in their own products
The DP83200EB can be combined with a DP83200EK Kit to
create a dual attach station The DP83200EK Kit contains
the additional Link card (PHY Layer) and appropriate ca-
bles
Features
Y
System modularity supports single attachment or dual
attachment
Y
Utilizes a PC-AT
compatible form factor
Y
Built-in diagnostic capability for fault detection
Y
Supports an external optical bypass switch
Y
Supports asynchronous and synchronous transmission
classes
Y
PAL based buffer management
Y
Supported by demonstration and diagnostic software
Y
Board schematics
TL F 11122 1
BMAC
TM
CDD
TM
CRD
TM
and PLAYER
TM
are trademarks of National Semiconductor Corporation
PAL
is a registered trademark of Advanced Micro Devices Inc
IBM
PC
PC-AT
are registered trademarks of International Business Machines Corporation
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
TL F 11122 2
SAS Configuration
TL F 11122 3
DAS Configuration
FIGURE 1 Single attach and optional dual attach configuration
2
1 0 Link Card
1 1 Link Card Description
The Link Card is intended for evaluation of the following
three National Semiconductor devices which implement the
FDDI Physical Layer and clock distribution
DP83255 Physical Layer Controller (PLAYER
TM
device)
DP83241 Clock Distribution Device (CDD
TM
device)
DP83231 Clock Recovery Device (CRD
TM
device)
The design goal of the Link Card was to allow the user to
exercise the Physical Layer devices and CDD device The
Link Card can be used in tandem with the DP83291EB MAC
Card (see Section 2 3) A Link Card connected to a single
MAC Card inplements a single attachment station Dual at-
tachment stations require two Link Cards The Link Card
requires a PC-AT compatible machine which is a readily
available platform capable of supporting an FDDI applica-
tion
1 2 Link Card Features
The Link Card offers many features to provide a flexible and
convenient evaluation platform
Utilizes the National FDDI Chip Set
DP83255 PLAYER Device
DP83241 CDD Device
DP83231 CRD Device
System modularity supports single attachment or dual
attachment configurations
Utilizes a PC-AT compatible form factor
Built-in diagnostic capability for fault detection
Supports an external optical bypass switch
Power consumption is 1 5 amps typical per Link Card
2 0 Link Card System Description
2 1 Block Diagram Description
The Link Card block diagram is composed of the following
seven blocks
1 AT Bus Interface
2 Clock Bus Interface
3 Clock Distribution Device (CDD device)
4 Clock Recovery Device (CRD device)
5 Link Bus Interface
6 Physical Layer Controller (PLAYER device)
7 Transceiver Interface
Figure 2 is a detailed representation of the block diagram
3
2 0 Link Card System Description
(Continued)
TL F 11122 4
FIGURE 2 Link Card Block Diagram
4
2 0 Link Card System Description
(Continued)
2 2 AT Interface Block
The function of the AT Interface Block is to interface the
Link Card with the AT host This block features a full 24-bit
address bus for flexible Link Card memory map placement
The data bus is 8 bits wide which is adequate for this demo
platform Bits 8 through 15 are not used on the base Link
Card but they have been tapped to test points on the board
The test points are included in the event that an application
requires a 16-bit data bus In addition to the address and
data buses seven AT bus interrupts and the necessary con-
trol signals are included All address and data signal lines
are buffered with independent parity generation supplied for
the data bus
The AT bus block is the
sole power supply for the Link Card
The address decoding scheme is accomplished with gener-
ic array logic devices (GALs) Equations for each of the four
GAL devices are included in Appendix G of the DP83290EB
FDDI Physical Layer Evaluation Board User's Guide
Beyond these basic functions the AT Interface offers a
number of modes such as autoconfiguration base register
area select and memory map configuration
2 3 Clock Bus Block
The Clock Bus Block is included in the Link Card design to
provide a physical bus among all Link and MAC Cards that
form a station The consruction of the bus is a twenty pin
ribbon cable capable of supporting 9 signals Each signal is
surrounded on either side by a ground line to reduce cross-
talk
2 4 CDD Device Block
The Clock Distribution Device is a clock generation and dis-
tribution device intended for use in FDDI networks The de-
vice provides the complete set of clocks required to convert
byte wide data to serial format for fiber medium transmis-
sion and to move byte wide data between the PLAYER and
BMAC devices in various station configurations 12 5 MHz
and 125 MHz differential ECL clocks are generated for the
conversion of data to serial format and 12 5 MHz and
125 MHz TTL clocks are generated for the byte wide data
transfers
2 5 CRD Device Block
The Clock Recovery Device has been designed for use in
this FDDI implementation The device receives serial data
from a Fiber Optic Receiver (FORX) in differential ECL NRZI
4B 5B group code format and outputs resynchronized NRZI
received data and a 125 MHz received clock in differential
ECL format for use by the PLAYER device
2 6 Link Bus Block
The function of the Link Bus is to provide a data path be-
tween the Link and MAC Cards that form an FDDI station
Each connection contains two 10-bit data buses (Indicate
and Request) and station configuration signals The pinout
of the Link Bus has been designed to allow the user to build
Single Attachment and Dual Attachment Single MAC con-
figurations To build one of these configurations the user
must simply connect the cabling in the manner shown in
Appendix E of the User's Guide
Every other write in the LInk Bus is grounded to insure data
integrity This cabling scheme has been tested for resist-
ance to data corruption induced by crosstalk
2 7 PLAYER Device Block
The Physical Layer Controller is a part of National Semicon-
ductor's FDDI Chip Set It implements one Physical Layer
entity as defined by the ANSI X3T9 5 PHY standard The
PLAYER device performs the 4B 5B encoding and decod-
ing serialization and deserialization of data repeat filter
and line state control and detection It also contains a con-
figuration switch The PLAYER device supports many types
of station configurations as allowed by the standard
Although tailored to the FDDI specification the PLAYER de-
vice is also well suited for use in high speed point-to-point
communication links over optical fibers and coaxial cable
2 8 Transceiver Block
The transceiver block consists of two parts fiber optic re-
ceiver and fiber optic transmitter The Link Card supports
the following FDDI optical transceiver modules
AT T ODL 125 Lightwave Data Links
Sumitomo DM-742 1300nm Data Link
Any Transceiver pair which supports the
AT T footprint 2 1 8 1 pin format
composed of 2 independent 16-pin DIP (footprints)
See Appendix A of the User's Guide for a detailed footprint
description
5
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