TL F 10384

DP83231

CRD

Device

(FDDI

Clock

Recovery

Device)

February 1991

DP83231 CRD

Device

(FDDI Clock Recovery Device)

General Description

The DP83231 CRD device is a clock recovery device that
has been designed for use in 100 Mbps FDDI (Fiber Distrib-
uted Data Interface) networks The device receives serial
data from a Fiber Optic Receiver in differential ECL NRZI
4B 5B group code format and outputs resynchronized NRZI
received data and a 125 MHz received clock in differential
ECL format for use by the DP83251 55 PLAYER

device

Features

Clock recovery at 100 Mbps data rate

Internal 250 MHz VCO

0 1% VCO operating range
Crystal controlled

Precision window centering delay line

Single

5V supply

28-pin PLCC package

BiCMOS processing

TL F 10384 1

FIGURE 1-1 FDDI Chip Set Block Diagram

TRI-STATE

is a registered trademark of National Semiconductor Corporation

BSI

BMAC

PLAYER

CDD

and CRD

are trademarks of National Semiconductor Corporation

C1995 National Semiconductor Corporation

RRD-B30M105 Printed in U S A

1 0 FDDI Chip Set Overview

National Semiconductor's FDDI chip set consists of five
components as shown in

Figure 1-1 For more information

about the other devices in the chip set consult the appropri-
ate data sheets and application notes

DP83231 CRD

Device

Clock Recovery Device

The Clock Recovery Device extracts a 125 MHz clock from
the incoming bit stream

Features

PHY Layer loopback test

Crystal controlled

Clock locks in less than 85 ms

DP83241 CDD

Device

Clock Distribution Device

From a 12 5 MHz reference the Clock Distribution Device
synthesizes the 125 MHz 25 MHz and 12 5 MHz clocks
required by the BSI BMAC and PLAYER devices

DP83251 55 PLAYER

Device

Physical Layer Controller

The PLAYER device implements the Physical Layer (PHY)
protocol as defined by the ANSI FDDI PHY X3T9 5 Stan-
dard

Features

4B 5B encoders and decoders

Framing logic

Elasticity Buffer Repeat Filter and Smoother

Line state detector generator

Link error detector

Configuration switch

Full duplex operation

Separate management port that is used to configure and
control operation

addition

the

DP83255

contains

additional

PHY

Data request and PHY

Data indicate port required

for concentrators and dual attach stations

DP83261 BMAC

Device

Media Access Controller

The BMAC device implements the Timed Token Media Ac-
cess Control protocol defined by the ANSI FDDI X3T9 5
MAC Standard

Features

All of the standard defined ring service options

Full duplex operation with through parity

Supports all FDDI Ring Scheduling Classes (Synchro-
nous Asynchronous etc )

Supports Individual Group Short Long and External
Addressing

Generates Beacon Claim and Void frames internally

Extensive ring and station statistics gathering

Extensions for MAC level bridging

Separate management port that is used to configure and
control operation

Multi-frame streaming interface

DP83265 BSI

Device

System Interface

The BSI Device implements an interface between the Na-
tional FDDI BMAC device and a host system

Features

32-bit wide Address Data path with byte parity

Programmable transfer burst sizes of 4 or 8 32-bit words

Interfaces to low-cost DRAMs or directly to system bus

Provides 2 Output and 3 Input Channels

Supports Header Info splitting

Efficient data structures

Programmable Big or Little Endian alignment

Full Duplex data path allows transmission to self

Comfirmation status batching services

Receive frame filtering services

Operates from 12 5 MHz to 25 MHz synchronously with
host system

2 0 Functional Description

The DP83231 uses two phase locked loops (PLL's) to per-
form the clock recovery function The function of the first
PLL is to establish a 250 MHz Voltage Controlled Oscillator
(VCO) with a narrow frequency range which can be pulled
by the second PLL The function of the second PLL is to
force this same VCO to track the incoming data so that a
Receive Clock output and a data synchronizing flip-flop can
be driven from it Operation of the VCO at 250 MHz ensures
that the received clock output operating at half of the VCO
frequency has a 50% duty cycle waveform independent of
any VCO waveform dissymmetry

The first PLL uses a 10 41666 MHz crystal as a pullable
frequency reference to generate the 250 MHz VCO The
limited frequency pulling range of the crystal ensures that
the capture range of the 250 MHz VCO is limited to less
than 0 1% of the specified data transition rate thus elimi-
nating the possibility of fractional or harmonic lock up
modes The output of the VCO is divided by twenty four and
applied to the feedback input of the phase detector in the
first PLL The phase detector compares the phase of the
VCO divided by twenty four signal against the phase of the
crystal to maintain VCO lock at 250 MHz If the phase tran-
sition of the signal derived from the VCO arrives at the
phase detector before that of the crystal the charge pump
circuitry will apply a negative current pulse to the VCO FLTR
node who's width is proportional to the phase error The
charge pulled out of the filter capacitors will drive the volt-
age applied to the VCO downward This reduction in the
VCO's control voltage will slow down the frequency of the
VCO and will appear during successive cycles to reduce the
VCO's phase and frequency error As the frequency of the
crystal varies in response to the second PLL the frequency
of the 250 MHz VCO will change in an attempt to remain
24 times the crystal's frequency

The second PLL delays the phase transitions of the select-
ed incoming stream of data (DATA

or LBD

) and then

compares them against the phase transitions of a gated
125 MHz signal derived from the 250 MHz VCO The de-
layed incoming data is applied to the reference input of a
phase detector and the gated VCO signal is applied to it's
feedback input If the positive and negative phase tran-
sitions of the incoming data do not line up with the phase
transitions of the gate VCO signal the charge pump circuitry
associated with that phase detector will apply current pulses
to the OSC FLTR

nodes which are proportional to the

phase error The change in the charge on the filter capaci-
tors will modify the reverse bias on the varactors in the crys-
tal's tank circuit thus causing the frequency of the
10 41666 MHz crystal (and consequently the VCO) to shift

in the direction which will reduce their phase error When
the phase of the VCO and the incoming data are aligned a
VCO divided by two signal can be used as the Receive
Clock output Because the two PLL's share a common VCO
feedback path the cutoff frequency of the loop filters asso-
ciated with the second PLL are specified to be approximate-
ly 10 times lower than the cutoff frequency of the first PLL to
prevent instability between the two loops

The delay line associated with the second PLL precisely
centers the data transitions within the data window The de-
lay line remains accurate independent of temperature pow-
er supply IC process variation or external components The
design also ensures that the charge pump up and down
circuits both produce an active pulse at each zero phase
crossing when in lock to guarantee a linear phase detector
gain characteristic

The CRD continually monitors the data frequency at the se-
lected data inputs If this input frequency drops below

the

minimum allowed frequency (about 3 MHz) the CRD resets
itself by internally deasserting CRD-EN This centers the
crystal frequency and restarts the internal VCO

The CRD EN pin is provided to initialize the CLK DET circuit-
ry and enable the crystal to track incoming data The part is
enabled when this pin is active High Deassertion of this pin
will cause the CLK DET circuitry and the OSC FLTR

pins

to be disabled in a manner similar to when legitimate data is
not being received Deassertion of the CRD EN pin also
momentarily causes (1 ms) the VCO FLTR pin to be pulled
to ground and stops the VCO and RXC

outputs After this

time the VCO will be restarted and its output frequency will
climb quickly to approximately 250 MHz

The device is capable of locking on to a stream of Halt or
Master line states in less than 100 ms when using a
10 41666 MHz crystal to govern the 250 MHz VCO Lock on
time for a stream of Idle line states is less than 10 ms once
Halt or Master line status is obtained During quiet line con-
ditions the chip will output a continual stream of Received
Clock whose frequency will be within less than 0 1% of the
upstream station's data rate The Received Data outputs
are always active Prior to the CLK DET output transitioning
active High the Received Data outputs may issue invalid
data (see Typical Waveforms) When the device is locked
Received Data is presented on the falling edge of the Re-
ceive Clock output insuring sufficient setup and hold margin
for the receiving device

An ECL to TTL translator is provided on the chip to convert
the FORX's ECL signal detect output level to TTL for use by
the PLAYER device

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