TL F 10386
DP83251DP83255
PLAYER
Device
(FDDI
Physical
Layer
Controller)
February 1991
DP83251 55 PLAYER
TM
Device
(FDDI Physical Layer Controller)
General Description
The DP83251 DP83255 PLAYER device implements one
Physical Layer (PHY) entity as defined by the Fiber Distribut-
ed Data Interface (FDDI) ANSI X3T9 5 Standard The PLAY-
ER device contains NRZ NRZI and 4B 5B encoders and
decoders
serializer deserializer
framing logic
elasticity
buffer line state detector generator link error detector re-
peat filter smoother and configuration switch
Features
Y
Low power CMOS-BIPOLAR process
Y
Single 5V supply
Y
Full duplex operation
Y
Separate management interface (Control Bus)
Y
Parity on PHY-MAC Interface and Control Bus Interface
Y
On-chip configuration switch
Y
Internal and external loopback
Y
DP83251 for single attach stations
Y
DP83255 for dual attach stations
TL F 10386 1
FIGURE 1-1 FDDI Chip Set Block Diagram
TRI-STATE
is a registered trademark of National Semiconductor Corporation
BSI
TM
BMAC
TM
PLAYER
TM
CDD
TM
and CRD
TM
are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Table of Contents
1 0
FDDI CHIP SET OVERVIEW
2 0
ARCHITECTURE DESCRIPTION
2 1
Overview
2 2
Interfaces
3 0
FUNCTIONAL DESCRIPTION
3 1
Receiver Block
3 2
Transmitter Block
3 3
Configuration Switch
4 0
MODES OF OPERATION
4 1
Run Mode
4 2
Stop Mode
4 3
Loopback Mode
4 4
Cascade Mode
5 0
REGISTERS
6 0
PIN DESCRIPTIONS
6 1
DP83251
6 2
DP83255
7 0
ELECTRICAL CHARACTERISTICS
7 1
Absolute Maximum Ratings
7 2
Recommended Operating Conditions
7 3
DC Electrical Charcteristics
7 4
AC Electrical Charcteristics
7 5
Test Circuits
8 0
DETAILED DESCRIPTIONS
8 1
Framing Hold Rules
8 2
Noise Events
8 3
Link Errors
8 4
Repeat Filter
8 5
Smoother
8 6
National Byte-wide Code for PHY-MAC Interface
2
1 0 FDDI Chip Set Overview
National Semiconductor's FDDI chip set consists of five
components as shown in
Figure 1-1 For more information
on the other devices of the chip set consult the appropriate
datasheets and application notes
DP83231 CRD
TM
Device
Clock Recovery Device
The Clock Recovery Device extracts a 125 MHz clock from
the incoming bit stream
Features
PHY Layer loopback test
Crystal controlled
Clock locks in less than 85 ms
DP83241 CDD
TM
Device
Clock Distribution Device
From a 12 5 MHz reference the Clock Distribution Device
synthesizes the 125 MHz 25 MHz and 12 5 MHz clocks
required by the BSI BMAC and PLAYER devices
DP83251 55 PLAYER
TM
Device
Physical Layer Controller
The PLAYER device implements the Physical Layer (PHY)
protocol as defined by the ANSI FDDI PHY X3T9 5 Stan-
dard
Features
4B 5B encoders and decoders
Framing logic
Elasticity Buffer Repeat Filter and Smoother
Line state detector generator
Link error detector
Configuration switch
Full duplex operation
Separate management port that is used to configure and
control their operation
In
addition
the
DP83255
contains
an
additional
PHY
Data request and PHY
Data indicate port required
for concentrators and dual attach stations
DP83261 BMAC
TM
Device
Media Access Controller
The BMAC device implements the Timed Token Media Ac-
cess Control protocol defined by the ANSI FDDI X3T9 5
MAC Standard
Features
All of the standard defined ring service options
Full duplex operation with through parity
Supports all FDDI Ring Scheduling Classes (Synchro-
nous Asynchronous etc )
Supports Individual Group Short Long and External
Addressing
Generates Beacon Claim and Void frames internally
Extensive ring and station statistic gathering
Extensions for MAC level bridging
Separate management port that is used to configure and
control their operation
Multi-frame streaming interface
DP83265 BSI
TM
Device
System Interface
The BSI device implements the interface between the
BMAC device and a host system
Features
32-bit wide Address Data path with byte parity
Programmable transfer burst sizes of 4 or 8 32-bit words
Interfaces to low cost DRAMs or directly to system bus
Provides 2 Output and 3 Input Channels
Supports Header Info splitting
Efficient data structures
Programmable Big or Little Endian alignment
Full duplex data path allows transmission to self
Confirmation status batching services
Receive frame filtering services
Operates from 12 5 MHz to 25 MHz synchronously with
the host system
3
2 0 Architecture Description
2 1 OVERVIEW
The PLAYER device is comprised of four blocks Receiver
Transmitter Configuration Switch and Control Bus Interface
as shown in
Figure 2-1
Receiver
During normal operation the Receiver Block accepts serial
data as inputs at the rate of 125 Mbps from the Clock Re-
covery Device (DP83231) During the Internal Loopback
mode of operation the Receiver Block accepts data from
the Transmitter Block as inputs
The Receiver Block performs the following operations
Converts the incoming data stream from NRZI to NRZ if
necessary
Decodes the data from 5B to 4B coding
Converts the serial bit stream into 10-bit bytes
Compensates for the differences between the upstream
and local clocks
Decodes Line States
Detects link errors
Finally the Receiver Block presents data symbol pairs
(bytes) to the Configuration Switch Block
Configuration Switch
An FDDI station may be in one of three configurations Iso-
late Wrap or Thru The Configuration Switch supports these
configurations by switching the transmitted and received
data paths between the PLAYER and BMAC devices
The configuration switching is performed internally there-
fore no external logic is required for this function
Transmitter
The Transmiter Block accepts 10-bit bytes from the Config-
uration Switch
The Transmitter Block performs the following operations
Encodes the data from 4B to 5B coding
Filters out code violations from the data stream
Generates Idle Master Halt Quiet or other user defined
symbol pairs upon request
Converts the data stream from NRZ to NRZI format
ready for transmission if necessary
Provides smoothing function when necessary
During normal operation the Transmitter Block presents se-
rial data to the fiber optic transmitter While in the External
Loopback mode the Transmitter Block presents serial data
to the Clock Recovery Device
Control Bus Interface
The Control Bus Interface allows a user to
Program the Configuration Switch
Enable disable functions within the Transmitter and Re-
ceiver Blocks (i e NRZ NRZI Encoder Smoother PHY
Request Data Parity Line State Generation Symbol Pair
Injection NRZ NRZI Decoder Cascade Mode etc )
The Control Bus Interface also performs the following func-
tions
Monitors Line States received
Monitors link errors detected by the Receiver Block
Monitors other error conditions
2 2 INTERFACES
The PLAYER device connects to external components via 5
functional interfaces Serial Interface PHY Port Interface
Control Bus Interface Clock Interface and the Miscellane-
ous Interface
Serial Interface
The Serial Interface connects the PLAYER device to a fiber
optic transmitter (FOTX) and the Clock Recovery Device
(DP83231)
TL F 10386 2
FIGURE 2-1 PLAYER Device Block Diagram
4
2 0 Architecture Description
(Continued)
PHY Port Interface
The PHY Port Interface connects the PLAYER device to
one or more BMAC devices and or PLAYER devices Each
PHY Port Interface consists of two byte-wide-interfaces
one for PHY Request data input to the PLAYER device and
one for the PHY Indicate data output of the PLAYER device
Each byte-wide interface consists of a parity bit (odd parity)
a control bit and two 4-bit symbols
The DP8355 PLAYER device has two PHY Port Interfaces
and the DP83251 has only one PHY Port Interface
Control Bus Interface
The Control Bus Interface connects the PLAYER device to
a wide variety of microprocessors and microcontrollers The
Control Bus is an asynchronous interface which provides
access to 32 8-bit registers
Clock Interface
The Clock Interface consists of 12 5 MHz and 125 MHz
clocks used by the PLAYER device
The clocks are generated by either the Clock Distribution
Device (CDD device) or the Clock Recovery Device (CRD
device)
Miscellaneous Interface
The Miscellaneous Interface consists of
A reset signal
User definable sense signals
User definable enable signals
Synchronization for cascaded PLAYER devices (a high-
performance non-FDDI mode)
CMOS power and ground and ECL ground and power
3 0 Functional Description
The PLAYER Device is comprised of four blocks Receiver
Transmitter Configuration Switch and Control Bus Inter-
face
3 1 RECEIVER BLOCK
During normal operation the Receiver Block accepts serial
data as inputs at the rate of 125 Mbps from the Clock Re-
covery Device (DP83231) During the Internal Loopback
mode of operation the Receiver Block accepts data from
the Transmitter Block as input
The Receiver Block performs the following operations
Converts the incoming data stream from NRZI to NRZ if
necessary
Decodes the data from 5B to 4B coding
Converts the serial bit stream into National byte-wide
code
Compensates for the differences between the upstream
and local clocks
Decodes Line States
Detects link errors
Finally the Receiver Block presents data symbol pairs to
the Configuration Switch Block
The Receiver Block consists of the following functional
blocks
NRZI to NRZ Decoder
Shift Register
Framing Logic
Symbol Decoder
Line State Detector
Elasticity Buffer
Link Error Detector
See
Figure 3-1
TL F 10386 3
FIGURE 3-1 Receiver Block Diagram
5
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