TL F 10791
DP83265
BSI
Device
(FDDI
System
Interface)
PRELIMINARY
February 1991
DP83265 BSI
TM
Device
(FDDI System Interface)
General Description
The DP83265 BSI device implements an interface between
the National FDDI BMAC
TM
device and a host system It
provides a multi-frame MAC-level interface to one or more
MAC Users
The BSI device accepts MAC User requests to receive and
transmit multiple frames (Service Data Units) On reception
(Indicate) it receives the byte stream from the BMAC de-
vice packs it into 32-bit words and writes it to memory On
transmission (Request) it unpacks the 32-bit wide memory
data and sends it a byte at a time to the BMAC device The
host software and the BSI device communicate via regis-
ters descriptors and an attention notify scheme using clus-
tered interrupts
Features
Y
32-bit wide Address Data path with byte parity
Y
Programmable transfer burst sizes of 4 or 8 32-bit
words
Y
Interfaces to low-cost DRAMs or directly to system bus
Y
2 Output and 3 Input Channels
Y
Supports Header Info splitting
Y
Bridging support
Y
Efficient data structures
Y
Programmable Big or Little Endian alignment
Y
Full Duplex data path allows transmission to self
Y
Confirmation status batching services
Y
Receive frame filtering services
Y
Operates from 12 5 MHz to 25 MHz synchronously with
host system
TL F 10791 1
FIGURE 1 FDDI Chip Set Block Diagram
TRI-STATE
is a registered trademark of National Semiconductor Corporation
BSI
TM
BMAC
TM
CDD
TM
CRD
TM
and PLAYER
TM
are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Table of Contents
1 0 FDDI CHIP SET OVERVIEW
2 0 ARCHITECTURE DESCRIPTION
2 1 Interfaces
2 2 Data Structures
2 3 Map Engine
3 0 FEATURE OVERVIEW
3 1 32-Bit address Data Path to Host Memory
3 2 Multi-Channel Architecture
3 3 Support for Header Info Splitting
3 4 MAC Bridging Support
3 5 Confirmation Status Batching Services
3 6 Receive Frame Filtering Services
3 7 Two Timing Domains
3 8 Clustered Interrupts
4 0 FUNCTIONAL DESCRIPTION
4 1 Overview
4 2 Operation
4 3 Bus Interface Unit
5 0 CONTROL INFORMATION
5 1 Overview
5 2 Operation Registers
5 3 Control and Event Register Descriptions
5 4 Pointer RAM Registers
5 5 Limit RAM Registers
5 6 Descriptors
5 7 Operating Rules
5 8 Pointer RAM Register Descriptions
5 9 Limit RAM Register Descriptions
5 10 BSI Device Descriptors
6 0 SIGNAL DESCRIPTIONS
6 1 Pin Organization
6 2 Control Interface
6 3 BMAC Device Indicate Interface
6 4 BMAC Device Request Interface
6 5 ABus Interface
6 6 Electrical Interface
2
1 0 FDDI Chip Set Overview
National Semiconductor's FDDI chip set consists of five
components as shown in
Figure 1-1 For more information
about the other devices in the chip set consult the appropri-
ate data sheets and application notes
DP83231 CRD
TM
Device
Clock Recovery Device
The Clock Recovery Device extracts a 125 MHz clock from
the incoming bit stream
Features
PHY Layer loopback test
Crystal controlled
Clock locks in less than 85 ms
DP83241 CDD
TM
Device
Clock Distribution Device
From a 12 5 MHz reference the Clock Distributon Device
synthesizes the 125 MHz 25 MHz and 12 5 MHz clock re-
quired by the BSI BMAC and PLAYER devices
DP83251 55 PLAYER
TM
Device
Physical Layer Controller
The PLAYER device implements the Physical Layer (PHY)
protocol as defined by the ANSI FDDI PHY X3T9 5 Stan-
dard
Features
4B 5B encoders and decoders
Framing logic
Elasticity Buffer Repeat Filter and Smoother
Line state detector generator
Link error detector
Configuration switch
Full duplex operation
Separate management port that is used to configure and
control operation
In
addition
the
DP83255
contains
an
additional
PHY
Data request and PHY
Data indicate port required
for concentrators and dual attach stations
DP83261 BMAC
TM
Device
Media Access Controller
The BMAC device implements the Timed Token Media Ac-
cess Control protocol defined by the ANSI FDDI X3T9 5
MAC Standard
Features
All of the standard defined ring service options
Full duplex operation with through parity
Supports all FDDI Ring Scheduling Classes (Synchro-
nous Asynchronous etc )
Supports Individual Group Short Long and External
Addressing
Generates Beacon Claim and Void frames internally
Extensive ring and station statistics gathering
Extensions for MAC level bridging
Separate management port that is used to configure and
control operation
Multi-frame streaming interface
DP83265 BSI
TM
Device
System Interface
The BSI Device implements an interface between the
BMAC device and a host system
Features
32-bit wide Address Data path with byte parity
Programmable transfer burst sizes of 4 or 8 32-bit words
Interfaces to low-cost DRAMs or directly to system bus
Provides 2 Output and 3 Input Channels
Supports Header Info splitting
Efficient data structures
Programmable Big or Little Endian alignment
Full duplex data path allows transmission to self
Confirmation status batching services
Receive frame filtering services
Operates from 12 5 MHz to 25 MHz synchronously with
host system
3
2 0 Architecture Description
The BSI device is composed of three interfaces and the
Map Engine
The three interfaces are the BMAC device the ABus and
the Control Bus They are used to connect the BSI device to
the BMAC device Host System and external Control Bus
The Map Engine manages the operation of the BSI device
2 1 INTERFACES
The BSI device connects to external components via three
interfaces the BMAC device Interface the ABus Interface
and the Control Bus Interface (see Figure 2-1)
2 1 1 BMAC Device Interface
The BSI device connects to the BMAC device via the
MA
Indicate (receive) and MA
Request (transmit) Inter-
faces as shown in
Figure 2-1
Received Data is transferred from the BMAC device to
the BSI device via the MA
Indicate Interface
The
MA
Indicate Interface consists of a parity bit (odd parity)
and byte-wide data along with flag and control signals
Transmit Data is transferred from the BSI device to
the BMAC device via the MA
Request Interface The
MA
Request Interface consists of a parity bit (odd parity)
and byte-wide data along with flag and control signals
2 1 2 ABus Interface
The BSI device connects to the Host System via the ABus
Interface The ABus Interface consists of four bits of parity
(odd parity) and 32 bits of multiplexed address and data
along with transfer control and bus arbitration signals
2 1 3 Control Bus Interface
The Control Bus Interface connects the BSI device to the
external Control Bus
The Control Bus Interface is separate from the BMAC de-
vice and ABus Interfaces to allow independent operation of
the Control Bus
The host uses the Control Bus to access the BSI device's
internal registers and to manage the attention notify logic
2 2 DATA STRUCTURES
2 2 1 Data Types
The architecture of the BSI device defines two basic kinds
of objects Data Units and Descriptors A Data Unit is a
group of contiguous bytes which forms all or part of a frame
(Service Data Unit) A Descriptor is a two-word (64-bit) con-
trol object that provides addressing information and control
status information about BSI device operations
Data and Descriptor objects may consist of one or more
parts where each part is contiguous and wholly contained
within a 1k or 4k memory page A single-part object consists
of one Only Part a multiple-part object consists of one First
Part zero or more Middle Parts and one Last Part In De-
scriptor names the object part is denoted in a suffix pre-
ceded by a dot Thus an Input Data Unit Descriptor (IDUD)
which describes the last Data Unit of a frame received from
the ring is called an IDUD Last
A single-part Data Unit is stored in contiguous locations
within a single 4k byte page in memory Multiple-part Data
Units are stored in separate and not necessarily contiguous
4k byte pages Descriptors are stored in contiguous loca-
tions in Queues and Lists where each Queue or List occu-
pies a single 1k byte or 4k byte memory page aligned on
the queue-size boundary For both Queues and Lists an
access to the next location after the end of a page will auto-
matically wrap-around and access the first location in the
page
TL F 10791 2
FIGURE 2-1 BSI Device Interfaces
4
2 0 Architecture Description
(Continued)
Data Units (MAC Service Data Units) are transferred be-
tween the BSI device and BMAC device via five simplex
Channels three used for Indicate (receive) data and two for
Request (transmit) data Parts of frames received from the
ring and copied to memory are called Input Data Units
(IDUs) parts of frames read from memory to be tansmitted
to the ring are called Output Data Units (ODUs)
Descriptors are transferred between the BSI device and
Host via the ABus whose operation is for the most part
transparent to the user There are five Descriptor types rec-
ognized by the BSI device Input Data Unit Descriptors
(IDUDs)
Output Data Unit Descriptors (ODUDs)
Pool
Space Descriptors (PSPs) Request Descriptors (REQs)
and Confirmation Message Descriptors (CNFs)
Input and Output Data Unit Descriptors describe a single
Data Unit part i e
its address (page number and offset)
its size in bytes
and its part (Only
First
Middle
or
Last) Frames consisting of a single part are described by
a Descriptor Only
frames consisting of multiple parts
are described by a Descriptor First zero or more Descrip-
tor Middles and a Descriptor Last
Every Output Data Unit part is described by an Output Data
Unit Descriptor (ODUD) Output Data Unit Descriptors are
fetched from memory so that frame parts can be assembled
for transmission
Every Input Data Unit part is described by an Input Data Unit
Descriptor (IDUD) Input Data Unit Descriptors are generat-
ed on Indicate Channels to describe where the BSI device
wrote each frame part and to report status for the frame
Request Descriptors (REQs) are written by the user to spec-
ify the operational parameters for BSI device Request oper-
ations Request Descriptors also contain the start address
of part of a stream of ODUDs and the number of frames
represented by the ODUD stream part (i e the number of
ODUD Last descriptors) Typically the user will define a sin-
gle Request Object consisting of multiple frames of the
same request and service class frame control and expect-
ed status
Confirmation Messages (CNFs) are created by the BSI de-
vice to record the result of a Request operation
Pool Space Descriptors (PSPs) describe the location and
size of a region of memory space available for writing Input
Data Units
Request (transmit) and Indicate (receive) data structures
are summarized in
Figures 2-2 and 2-3
TL F 10791 3
FIGURE 2-2 BSI Device Request Data Structures
5
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