TL F 11705

DP83266

MACSI

Device

(FDDI

Media

Access

Controller

and

System

Interface)

PRELIMINARY

October 1994

DP83266 MACSI

Device

(FDDI Media Access Controller and System Interface)

General Description

The DP83266 Media Access Controller and System Inter-
face (MACSI) implements the ANSI X3T9 5 Standard Media
Access Control (MAC) protocol for operation in an FDDI
token ring and provides a comprehensive System Interface

The MACSI device transmits receives repeats and strips
tokens and frames It produces and consumes optimized
data structures for efficient data transfer Full duplex archi-
tecture with through parity allows diagnostic transmission
and self testing for error isolation and point-to-point connec-
tions

The MACSI device includes the functionality of both the
DP83261 BMAC

device and the DP83265 BSI-2

device

with additional enhancements for higher performance and
reliability

Features

Over 9 kBytes of on-chip FIFO

5 DMA channels (2 Output and 3 Input)

12 5 MHz to 25 MHz operation

Full duplex operation with through parity

Supports JTAG boundary scan

Real-time Void stripping indicator for bridges

On-chip address bit swapping capability

32-bit wide Address Data path with byte parity

Programmable transfer burst sizes of 4 or 8
32-bit words

Receive frame filtering services

Frame-per-Page mode controllable on each
DMA channel

Demultiplexed Addresses supported on ABus

New multicast address matching feature

ANSI X3T9 5 MAC standard defined ring
service options

Supports all FDDI Ring Scheduling Classes
(Synchronous Asynchronous etc )

Supports Individual Group Short Long and
External Addressing

Generates Beacon Claim and Void frames

Extensive ring and station statistics gathering

Extensions for MAC level bridging

Enhanced SBus compatibility

Interfaces to DRAMs or directly to system bus

Supports frame Header Info splitting

Programmable Big or Little Endian alignment

Block Diagram

TL F 11705 � 1

FIGURE 1-1 FDDI Chip Set Block Diagram

TRI-STATE

is a registered trademark of National Semiconductor Corporation

BMAC

BSI-2

MACSI

and PLAYERa

are trademarks of National Semiconductor Corporation

C1995 National Semiconductor Corporation

RRD-B30M105 Printed in U S A

Table of Contents

1 0 FDDI CHIP SET OVERVIEW

2 0 GENERAL FEATURES

2 1 FDDI MAC Support

2 2 MAC Addressing Support

2 3 MAC Bridging Support

2 4 MAC Service Class Support

2 5 Diagnostic Counters

2 6 Management Services

2 7 Ring Parameter Tuning

2 8 Multi-Frame Streaming Interface

2 9 Beacon Claim and Void Frames Generation

2 10 Self Testing

2 11 32-Bit Address Data Path to Host Memory

2 12 Multi-Channel Architecture

2 13 Support for Header Info Splitting

2 14 MAC Bridging Support

2 15 Address Bit Swapping

2 16 Status Batching Services

2 17 Receive Frame Filtering Services

2 18 Two Timing Domains

2 19 Clustered Interrupts

2 20 FIFO Memory

2 21 Frame-per-Page-per-Channel

2 22 Copy All Multicast

2 23 Bridge Stripping Information

2 24 LED Status Control Outputs

2 25 JTAG Boundary Scan

3 0 ARCHITECTURAL DESCRIPTION

3 1 Interfaces

3 2 Ring Engine

3 3 Data Structures

3 4 Service Engine

4 0 FDDI MAC FACILITIES

4 1 Symbol Set

4 2 Protocol Data Units

4 3 Frame Counts

4 4 Timers

4 5 Ring Scheduling

5 0 FUNCTIONAL DESCRIPTION (RING ENGINE)

5 1 Token Handling

5 2 Servicing Transmission Requests

5 3 Request Service Parameters

5 4 Frame Validity Processing

5 0 FUNCTIONAL DESCRIPTION (RING ENGINE)

(Continued)

5 5 Frame Status Processing

5 6 SMT Frame Processing

5 7 MAC Frame Processing

5 8 Receive Batching Support

5 9 Immediate Frame Transmission

5 10 Full Duplex Operation

5 11 Parity Processing

5 12 Handling Internal Errors

6 0 FUNCTIONAL DESCRIPTION (SERVICE ENGINE)

6 1 Overview

6 2 Operation

6 3 External Matching Interface

6 4 Bus Interface Unit

6 5 Enhanced ABUS Mode

7 0 CONTROL INFORMATION

7 1 Overview

7 2 Conventions

7 3 Access Rules

7 4 Ring Engine Operation Registers

7 5 MAC Parameters

7 6 Timer Values

7 7 Event Counters

7 8 Pointer RAM Registers

7 9 Limit RAM Registers

7 10 Descriptors

7 11 Operating Rules

7 12 Pointer RAM Register Descriptions

7 13 Limit RAM Register Descriptions

8 0 SIGNAL DESCRIPTIONS

8 1 Control Interface

8 2 PHY Interface

8 3 External Matching Interface

8 4 LED Interface

8 5 ABus Interface

8 6 Electrical Interface

9 0 ELECTRICAL CHARACTERISTICS

9 1 Absolute Maximum Ratings

9 2 Recommended Operating Conditions

9 3 DC Electrical Characteristics

9 4 AC Electrical Characteristics

10 0 PIN TABLE AND PIN DIAGRAM

1 0 FDDI Chip Set Overview

National Semiconductor's FDDI chip set is shown in

Figure

1-1 For more information about the PLAYER

device

consult the appropriate datasheet and application notes

DP83256 56-AP 57 PLAYER

Device Physical Layer Controller

The PLAYER

device implements the Physical Layer

(PHY) protocol as defined by the ANSI FDDI PHY X3T9 5
Standard along with all the necessary clock recovery and
clock generation functions

Features

Single chip FDDI Physical Layer (PHY) solution

Integrated Digital Clock Recovery Module provides en-
hanced tracking and greater lock acquisition range

Integrated Clock Generation Module provides all neces-
sary clock signals for an FDDI system from an external
12 5 MHz reference

Alternate PMD Interface (DP83256-AP 57) Supports
UTP twisted pair FDDI PMDS with no external clock re-
covery or clock generations functions required

No External Filter Components

Connection Management (CMT) Support (LEM TNE
PC

React CF

React Auto Scrubbing)

Full on-chip configuration switch

Low Power CMOS-BIPOLAR design using a single 5V
supply

Full duplex operation with through parity

Separate management interface (Control Bus)

Selectable Parity on PHY-MAC Interface and Control Bus
Interface

Two levels of on-chip loopback

4B 5B encoder decoder

Framing logic

Elasticity Buffer Repeat Filter and Smoother

Line state detector generator

Supports single attach stations dual attach stations and
concentrators with no external logic

DP83256 56-AP for SAS DAS single path stations

DP83257 for SAS DAS single dual path stations

addition

the

DP83257

contains

additional

PHY

Data request and PHY

Data indicate port required

for concentrators and dual attach stations

DP83266 MACSI Device
Media Access Controller and
System Interface

The MACSI device implements the Timed Token Media Ac-
cess Control protocol defined by the ANSI FDDI X3T9 5
MAC Standard as well as a high performance system inter-
face

Features

Over 9 kBytes of on-chip FIFO

5 DMA channels (2 Output and 3 Input)

12 5 MHz to 25 MHz operation

Full duplex operation with through parity

Supports JTAG boundary scan

Real-time Void stripping indicator for bridges

On-chip address bit swapping capability

32-bit wide Address Data path with byte parity

Programmable transfer burst sizes of 4 or 8 32-bit words

Receive frame filtering services

Frame-per-Page mode controllable on each
DMA channel

Demultiplexed Addresses supported on ABus

New multicast address matching feature

ANSI X3T9 5 MAC standard defined ring service options

Supports all FDDI Ring Scheduling Classes
(Synchronous Asynchronous etc )

Supports Individual Group Short Long and
External Addressing

Generates Beacon Claim and Void frames

Extensive ring and station statistics gathering

Extensions for MAC level bridging

Enhanced SBus compatibility

Interfaces to DRAMs or directly to system bus

Supports frame Header Info splitting

Programmable Big or Little Endian alignment

2 0 General Features

The DP83266 MACSI device is a highly integrated FDDI
controller Together with the DP83256 57 PLAYER

de-

vice it forms a full-featured high performance FDDI chip set
useful for designing end station attachments concentrators
bridges routers and other FDDI connections The MACSI
device provides all of the features and services of both the
DP83261 BMAC device and the DP83265 BSI-2 device with
enhanced performance and reliability

For system connection the MACSI device provides a simple
yet powerful bus interface and memory management
scheme to maximize system efficiency and it is capable of
interfacing to a variety of host buses environments The
MACSI device provides a 32-bit wide data interface which
can be configured to share a system bus to main memory or
to use external shared memory Also provided are 28-bit
addresses multiplexed on the data pins as well as demulti-
plexed on dedicated pins The system interface supports
virtual addressing using fixed-size pages

For network connection the MACSI device provides many
services which simplify network management and increase
system performance and reliability The MACSI device is
capable of batching confirmation and indication status fil-
tering MAC frames with the same Information field as well
as Void frames and performing network monitoring func-
tions

2 1 FDDI MAC SUPPORT

The MACSI device implements the ANSI X3T9 5 FDDI MAC
standard protocol for transmitting receiving repeating and
stripping frames The MACSI device provides all of the infor-
mation necessary to implement the service primitives de-
fined in the standard

2 2 MAC ADDRESSING SUPPORT

Both long (48-bit) and short (16-bit) addressing are support-
ed simultaneously for both Individual and Group addresses

2 3 MAC BRIDGING SUPPORT

Several features are provided to increase performance in
bridging applications

On the receive side external address matching logic can be
used to examine the PH

Indicate byte stream to decide

whether to copy a frame how to set the control indicators
and how to increment the counters

On the transmit side transparency options are provided on
the Source Address the most significant bit of the Source
Address and the Frame Check Sequence (FCS)

In addition support for an alternate stripping mechanism
(implemented using My

Void frames) provides maximum

flexibility in the generation of frames by allowing the use of
Source Address Transparency (SAT)

2 4 MAC SERVICE CLASS SUPPORT

All FDDI MAC service classes are supported by the MACSI
device including Synchronous Asynchronous Restricted
Asynchronous and Immediate service classes

For Synchronous transmission one or more frames are
transmitted in accordance with the station's synchronous
bandwidth allocation

For Asynchronous transmission one programmable asyn-
chronous priority threshold is supported in addition to the
threshold at the Negotiated Target Token Rotation time

For Restricted Asynchronous transmission support is pro-
vided to begin continue and end restricted dialogues

For Immediate transmissions support is provided to send
frames from either the Data Beacon or Claim states and
either ignore or respond to the received byte stream After
an immediate transmission a token may optionally be is-
sued

2 5 DIAGNOSTIC COUNTERS

The MACSI device includes a number of diagnostic coun-
ters and timers that monitor ring and station performance

These counters allow measurement of the following

Number of frames transmitted and received by the
station

Number of frames copied as well as frames not copied

Frame error rate of an incoming physical connection to
the MAC

Load on the ring based on the number of tokens re-
ceived and the ring latency

Ring latency

Lost frames

The size of these counters has been selected to keep the
frequency of overflow small even under worst case operat-
ing conditions

2 6 MANAGEMENT SERVICES

The MACSI device provides management services to the
Host System via the Control Bus Interface This interface
allows access to internal registers to control and configure
the MACSI device

2 7 RING PARAMETER TUNING

The MACSI device includes settable parameters to allow
tuning of the network to increase performance over a large
range of network sizes

The MACSI device supports systems of two stations with
little cable between them to ring configurations much larger
than the 1000 physical attachments and or 200 kilometer
distance that are specified as the default values in the stan-
dard

The MACSI device also handles frames larger than the
4500 byte default maximum frame size as specified in the
standard

2 8 MULTI-FRAME STREAMING INTERFACE

The MACSI device provides an interface to support multi-
frame streaming Multiple frames can be transmitted after a
token is captured within the limits of the token timer thresh-
olds

2 9 BEACON CLAIM AND VOID FRAMES GENERATION

For purposes of transient token and ring recovery no proc-
essor intervention is required The MACSI device automati-
cally generates the appropriate MAC frames

2 10 SELF TESTING

Since the MACSI device has a full duplex architecture loop-
back testing is possible before entering the ring and during
normal ring operation

There are several possible loopback paths

Internal to the MACSI device

Through the PLAYER

device(s) using the PLAYER

configuration switch

Through the PLAYER

Clock Recovery Module

2 0 General Features

(Continued)

These paths allow error isolation at the device level

The MACSI device also supports through parity Even when
parity is not used by the system parity support can be pro-
vided across the PHY Interface

2 11 32-BIT ADDRESS DATA PATH TO HOST MEMORY

The MACSI device provides a 32-bit wide synchronous data
interface which permits connection to a standard multi-
master system bus operating from 12 5 MHz to 33 MHz or
to local memory using Big or Little Endian byte ordering
Demultiplexed addresses are provided on dedicated pins
Address information is also multiplexed on the data pins to
provide backward compatibility for designs based on the
BSI device The local memory may be static or dynamic For
maximum performance the MACSI device uses burst mode
transfers with four or eight 32-bit words to a burst To assist
the user with the burst transfer capability the three bits of
the address which cycle during a burst are output as demul-
tiplexed signals Maximum burst speed is one 32-bit word
per clock but slower speeds may be accommodated by in-
serting wait states

The MACSI device can operate within any combination of
cached non-cached paged or non-paged memory environ-
ments To provide this capability all data structures are con-
tained within a page boundary and bus transactions never
cross page boundaries The MACSI device performs all bus
transactions within aligned blocks to ease the interface to a
cached environment

2 12 MULTI-CHANNEL ARCHITECTURE

The MACSI device provides three Input Channels and two
Output Channels which are designed to operate indepen-
dently and concurrently They are separately configured by
the user to manage the reception or transmission of a par-
ticular kind of frame (for example synchronous frames
only)

2 13 SUPPORT FOR HEADER INFO SPLITTING

In order to support high performance protocol processing
the MACSI device can be programmed to split the header
and information portions of (non-MAC SMT) frames be-
tween two Indicate Channels Frame bytes from the Frame
Control field (FC) up to the user-defined header length are
copied onto Indicate Channel 1 and the remaining bytes
(Info) are copied onto Indicate Channel 2 This is useful for
separating protocol headers from data and allows them to
be stored in different regions of memory to prevent unnec-
essary copying In addition a protocol monitor application
may decide to copy only the header portion of each frame

2 14 MAC BRIDGING SUPPORT

Support for bridging and monitoring applications is provided
by the Internal External Sorting Mode All frames matching
the external address (frames requiring bridging) are sorted
onto Indicate Channel 2 MAC and SMT frames matching
the internal (Ring Engine) address are sorted onto Indicate
Channel 0 and all other frames matching the device's inter-
nal address (short or long) are sorted onto Indicate
Channel 1

2 15 ADDRESS BIT SWAPPING

The MACSI contains the necessary logic for swapping the
address fields within each frame between FDDI and IEEE
Canonical bit order This involves a bit reversal within each
byte of the address field (e g 08-00-17-C2-A1-03 would be-

come 10 00 E8 43 85 C0) This option is selectable on a per
channel basis and is supported on all transmit and receive
channels This is useful for bridging FDDI to Ethernet or for
swapping addresses for higher level protocols

2 16 STATUS BATCHING SERVICES

The MACSI device provides status for transmitted and re-
ceived frames Interrupts to the host are generated only at
status breakpoints which are defined by the user on a per
DMA Channel basis Breakpoints are selected when the
Channel is configured for operation To allow batching the
MACSI provides a status option called Tend that causes
the device to generate a single Confirmation Message De-
scriptor (CNF) for one or more Request Descriptors (REQs)

The MACSI device further reduces host processing time by
separating received frame status from the received data
This allows the CPU to scan quickly for errors when decid-
ing whether further processing should be done on received
frames If status was embedded in the data stream all data
would need to be read contiguously to find the Status Indi-
cator

2 17 RECEIVE FRAME FILTERING SERVICES

To increase performance and reliability the MACSI device
can be programmed to filter out identical MAC (same FC
and Info field) or SMT frames received from the ring Void
frames are filtered out automatically Filtering unnecessary
frames reduces the fill rate of the Indicate FIFO reduces
CPU frame processing time and reduces memory bus
transactions

2 18 TWO TIMING DOMAINS

To provide maximum performance and system flexibility the
MACSI device uses two independent clocks one for the
MAC (ring) Interface and one for the system memory bus
The MACSI device provides a fully synchronized interface
between these two timing domains

2 19 CLUSTERED INTERRUPTS

The MACSI device can be operated in a polled or interrupt-
driven environment The MACSI device provides the ability
to generate attentions (interrupts) at group boundaries
Some boundaries are pre-defined in hardware others are
defined by the user when the Channel is configured This
interrupt scheme significantly reduces the number of inter-
rupts to the host thus reducing host processing overhead

2 20 FIFO MEMORY

The MACSI device contains over 9 kBytes of on-chip FIFO
memory This memory includes separate 4 6 kByte FIFOs
for both the Transmit (Request) and Receive (Indicate) data
paths These data FIFOs allow the MACSI device to support
over 370 ms of bus latency for both transmit and receive
They also allow the MACSI device to buffer entire maximum
length FDDI frames on-chip for both transmit and receive
simultaneously This allows lower cost systems by enabling
the MACSI device to reside directly on system buses with
high latency requirements

These FIFOs support all of the features available in the orig-
inal BSI device including two transmit and three receive
channels to make efficient use of the FIFO resources New
transmit thresholds are available to allow full use of the larg-
er transmit FIFO

Электронный компонент: DP83266VF