DP83816 10/100 Mb/s Integrated PC
I Ethernet Media Access
Controller and Physical
Layer (MacPHYTER-IITM)
2003 National Semiconductor Corporation
www.national.com
1
June 2003
DP83816 10/100 Mb/s Integrated PCI Ethernet Media Access
Controller and Physical Layer (MacPHYTER-II
TM
)
General Description
DP83816 is a single-chip 10/100 Mb/s Ethernet Controller
for the PCI bus. It is targeted at low-cost, high volume PC
motherboards, adapter cards, and embedded systems.
The DP83816 fully implements the V2.2 33 MHz PCI bus
interface for host communications with power management
support. Packet descriptors and data are transferred via
bus-mastering, reducing the burden on the host CPU. The
DP83816 can support full duplex 10/100 Mb/s transmission
and reception, with minimum interframe gap.
The DP83816 device is an integration of an enhanced
version of the National Semiconductor PCI MAC/BIU
(Media Access Controller/Bus Interface Unit) and a 3.3V
CMOS physical layer interface.
Features
-- IEEE 802.3 Compliant, PCI V2.2 MAC/BIU supports
traditional data rates of 10 Mb/s Ethernet and 100 Mb/s
Fast Ethernet (via internal phy)
-- Bus master - burst sizes of up to 128 dwords (512 bytes)
-- BIU compliant with PC 97 and PC 98 Hardware Design
Guides, PC 99 Hardware Design Guide draft, ACPI v1.0,
PCI Power Management Specification v1.1, OnNow
Device Class Power Management Reference
Specification - Network Device Class v1.0a
-- Wake on LAN (WOL) support compliant with PC98,
PC99, SecureOn, and OnNow, including directed
packets, Magic Packet
, VLAN packets, ARP packets,
pattern match packets, and Phy status change
-- Clkrun function for PCI Mobile Design Guide
-- Virtual LAN (VLAN) and long frame support
-- Support for IEEE 802.3x Full duplex flow control
-- Extremely flexible Rx packet filtration including: single
address perfect filter with MSb masking, broadcast, 512
entry multicast/unicast hash table, deep packet pattern
matching for up to 4 unique patterns
-- Statistics gathered for support of RFC 1213 (MIB II),
RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing
CPU overhead for management
-- Internal 2 KB Transmit and 2 KB Receive data FIFOs
-- Serial EEPROM port with auto-load of configuration data
from EEPROM at power-on
-- Flash/PROM interface for remote boot support
-- Fully integrated IEEE 802.3/802.3u 3.3V CMOS physical
layer
-- IEEE 802.3 10BASE-T transceiver with integrated filters
-- IEEE 802.3u 100BASE-TX transceiver
-- Fully integrated ANSI X3.263 compliant TP-PMD
physical sublayer with adaptive equalization and
Baseline Wander compensation
-- IEEE 802.3u Auto-Negotiation - advertised features
configurable via EEPROM
-- Full Duplex support for 10 and 100 Mb/s data rates
-- Single 25 MHz reference clock
-- 144-pin LQFP package
-- Low power 3.3V CMOS design with typical consumption
of 383 mW operating, 297 mW during WOL and 53 mW
during sleep mode
-- IEEE 802.3u MII for connecting alternative external
Physical Layer Devices
-- 3.3V signalling with 5V tolerant I/O.
System Diagram
PCI Bus
DP83816
EEPROM
Isolation
10/100 Twisted Pair
BIOS ROM
(optional) (optional)
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
MacPHYTER-II
is a trademark of National Semiconductor Corporation.
Magic Packet
is a trademark of Advanced Micro Devices, Inc.
2
www.national.com
DP83816
Table of Contents
1.0 Connection Diagram . . . . . . . . . . . . . . . . . . 4
1.1 144 LQFP Package (VNG) . . . . . . . . . . . . 4
2.0 Pin Description . . . . . . . . . . . . . . . . . . . . . . 5
3.0 Functional Description . . . . . . . . . . . . . . . 11
3.1 MAC/BIU . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.1 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.2 Tx MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.3 Rx MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Buffer Management . . . . . . . . . . . . . . . . . 13
3.2.1 Tx Buffer Manager . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.2 Rx Buffer Manager . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.3 Packet Recognition . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.4 MIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Interface Definitions . . . . . . . . . . . . . . . . . 14
3.3.1 PCI System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.2 Boot PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.3 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Physical Layer . . . . . . . . . . . . . . . . . . . . . 16
3.4.1 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.2 Auto-Negotiation Register Control . . . . . . . . . . . . . 16
3.4.3 Auto-Negotiation Parallel Detection . . . . . . . . . . . . 16
3.4.4 Auto-Negotiation Restart . . . . . . . . . . . . . . . . . . . . 17
3.4.5 Enabling Auto-Negotiation via Software . . . . . . . . 17
3.4.6 Auto-Negotiation Complete Time . . . . . . . . . . . . . . 17
3.5 LED Interfaces . . . . . . . . . . . . . . . . . . . . . 17
3.6 Half Duplex vs. Full Duplex . . . . . . . . . . . 18
3.7 Phy Loopback . . . . . . . . . . . . . . . . . . . . . 18
3.8 Status Information . . . . . . . . . . . . . . . . . . 18
3.9 100BASE-TX TRANSMITTER . . . . . . . . . 18
3.9.1 Code-group Encoding and Injection . . . . . . . . . . . 19
3.9.2 Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.9.3 NRZ to NRZI Encoder . . . . . . . . . . . . . . . . . . . . . . 20
3.9.4 Binary to MLT-3 Convertor / Common Driver . . . . 20
3.10 100BASE-TX Receiver . . . . . . . . . . . . . . 21
3.10.1 Input and Base Line Wander Compensation . . . . 21
3.10.2 Signal Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.10.3 Digital Adaptive Equalization . . . . . . . . . . . . . . . . 23
3.10.4 Line Quality Monitor . . . . . . . . . . . . . . . . . . . . . . . 24
3.10.5 MLT-3 to NRZI Decoder . . . . . . . . . . . . . . . . . . . . 24
3.10.6 Clock Recovery Module . . . . . . . . . . . . . . . . . . . . 25
3.10.7 NRZI to NRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.8 Serial to Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.9 De-scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.10 Code-group Alignment . . . . . . . . . . . . . . . . . . . . 25
3.10.11 4B/5B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.12 100BASE-TX Link Integrity Monitor . . . . . . . . . . 25
3.10.13 Bad SSD Detection . . . . . . . . . . . . . . . . . . . . . . 25
3.11 10BASE-T Transceiver Module . . . . . . . . 26
3.11.1 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11.2 Smart Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11.3 Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11.4 Normal Link Pulse Detection/Generation . . . . . . . 26
3.11.5 Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.11.6 Automatic Link Polarity Detection . . . . . . . . . . . . . 27
3.11.7 10BASE-T Internal Loopback . . . . . . . . . . . . . . . . 27
3.11.8 Transmit and Receive Filtering . . . . . . . . . . . . . . . 27
3.11.9 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.11.10 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.11.11 Far End Fault Indication . . . . . . . . . . . . . . . . . . . 27
3.12 802.3u MII . . . . . . . . . . . . . . . . . . . . . . . . 27
3.12.1 MII Access Configuration . . . . . . . . . . . . . . . . . . . 27
3.12.2 MII Serial Management . . . . . . . . . . . . . . . . . . . . 27
3.12.3 MII Serial Management Access . . . . . . . . . . . . . 28
3.12.4 Serial Management Access Protocol . . . . . . . . . 28
3.12.5 Nibble-wide MII Data Interface . . . . . . . . . . . . . . 28
3.12.6 Collision Detection . . . . . . . . . . . . . . . . . . . . . . . 29
3.12.7 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.0 Register Set . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1 Configuration Registers . . . . . . . . . . . . . . 30
4.1.1 Configuration Identification Register . . . . . . . . . . . 30
4.1.2 Configuration Command and Status Register . . . 31
4.1.3 Configuration Revision ID Register . . . . . . . . . . . 32
4.1.4 Configuration Latency Timer Register . . . . . . . . . 33
4.1.5 Configuration I/O Base Address Register . . . . . . . 33
4.1.6 Configuration Memory Address Register . . . . . . . 34
4.1.7 Configuration Subsystem Identification Register . 34
4.1.8 Boot ROM Configuration Register . . . . . . . . . . . . 35
4.1.9 Capabilities Pointer Register . . . . . . . . . . . . . . . . 35
4.1.10 Configuration Interrupt Select Register . . . . . . . . 36
4.1.11 Power Management Capabilities Register . . . . . 36
4.1.12 Power Management Control and Status Register 37
4.2 Operational Registers . . . . . . . . . . . . . . . 38
4.2.1 Command Register . . . . . . . . . . . . . . . . . . . . . . . . 39
4.2.2 Configuration and Media Status Register . . . . . . . 40
4.2.3 EEPROM Access Register . . . . . . . . . . . . . . . . . . 42
4.2.4 EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2.5 PCI Test Control Register . . . . . . . . . . . . . . . . . . . 43
4.2.6 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . 44
4.2.7 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . 45
4.2.8 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . 47
4.2.9 Interrupt Holdoff Register . . . . . . . . . . . . . . . . . . . 47
4.2.10 Transmit Descriptor Pointer Register . . . . . . . . . 48
4.2.11 Transmit Configuration Register . . . . . . . . . . . . . 48
4.2.12 Receive Descriptor Pointer Register . . . . . . . . . . 50
4.2.13 Receive Configuration Register . . . . . . . . . . . . . 51
4.2.14 CLKRUN Control/Status Register . . . . . . . . . . . . 52
4.2.15 Wake Command/Status Register . . . . . . . . . . . . 54
4.2.16 Pause Control/Status Register . . . . . . . . . . . . . . 56
4.2.17 Receive Filter/Match Control Register . . . . . . . . 57
4.2.18 Receive Filter/Match Data Register . . . . . . . . . . 58
4.2.19 Receive Filter Logic . . . . . . . . . . . . . . . . . . . . . . 59
4.2.20 Boot ROM Address Register . . . . . . . . . . . . . . . . 63
4.2.21 Boot ROM Data Register . . . . . . . . . . . . . . . . . . 63
4.2.22 Silicon Revision Register . . . . . . . . . . . . . . . . . . 63
4.2.23 Management Information Base Control Register 64
4.2.24 Management Information Base Registers . . . . . . 65
4.3 Internal PHY Registers . . . . . . . . . . . . . . . 66
4.3.1 Basic Mode Control Register . . . . . . . . . . . . . . . . 66
4.3.2 Basic Mode Status Register . . . . . . . . . . . . . . . . . 67
4.3.3 PHY Identifier Register #1 . . . . . . . . . . . . . . . . . . 68
4.3.4 PHY Identifier Register #2 . . . . . . . . . . . . . . . . . . 68
4.3.5 Auto-Negotiation Advertisement Register . . . . . . 68
4.3.6 Auto-Negotiation Link Partner Ability Register . . . 69
4.3.7 Auto-Negotiate Expansion Register . . . . . . . . . . . 70
4.3.8 Auto-Negotiation Next Page Transmit Register . . 70
4.3.9 PHY Status Register . . . . . . . . . . . . . . . . . . . . . . . 71
4.3.10 MII Interrupt Control Register . . . . . . . . . . . . . . . 73
4.3.11 MII Interrupt Status and Misc. Control Register . 73
4.3.12 False Carrier Sense Counter Register . . . . . . . . 74
4.3.13 Receiver Error Counter Register . . . . . . . . . . . . . 74
4.3.14 100 Mb/s PCS Configuration and Status Register 74
4.3.15 PHY Control Register . . . . . . . . . . . . . . . . . . . . . 75
4.3.16 10BASE-T Status/Control Register . . . . . . . . . . . 76
5.0 Buffer Management . . . . . . . . . . . . . . . . . . 77
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.1.1 Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.1.2 Single Descriptor Packets . . . . . . . . . . . . . . . . . . 79
3
www.national.com
DP83816
5.1.3 Multiple Descriptor Packets . . . . . . . . . . . . . . . . . . 80
5.1.4 Descriptor Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.2 Transmit Architecture . . . . . . . . . . . . . . . 81
5.2.1 Transmit State Machine . . . . . . . . . . . . . . . . . . . . . 81
5.2.2 Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3 Receive Architecture . . . . . . . . . . . . . . . . 84
5.3.1 Receive State Machine . . . . . . . . . . . . . . . . . . . . . 84
5.3.2 Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.0 Power Management and Wake-On-LAN. . 87
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 87
6.2 Definitions (for this document only) . . . . . 87
6.3 Packet Filtering . . . . . . . . . . . . . . . . . . . . 87
6.4 Power Management . . . . . . . . . . . . . . . . 87
6.4.1 D0 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.4.2 D1 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.4.3 D2 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.4.4 D3hot State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.4.5 D3cold State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.5 Wake-On-LAN (WOL) Mode . . . . . . . . . . 88
6.5.1 Entering WOL Mode . . . . . . . . . . . . . . . . . . . . . . . 88
6.5.2 Wake Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.5.3 Exiting WOL Mode . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.6 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . 89
6.6.1 Entering Sleep Mode . . . . . . . . . . . . . . . . . . . . . . 89
6.6.2 Exiting Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . 89
6.7 Pin Configuration for Power Management 89
7.0 DC and AC Specifications . . . . . . . . . . . . . 90
7.1 DC Specifications . . . . . . . . . . . . . . . . . . . 90
7.2 AC Specifications . . . . . . . . . . . . . . . . . . . 91
7.2.1 PCI Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.2.2 X1 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.2.3 Power On Reset (PCI Active) . . . . . . . . . . . . . . . . 92
7.2.4 Non Power On Reset . . . . . . . . . . . . . . . . . . . . . . 92
7.2.5 POR PCI Inactive . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.2.6 PCI Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.2.7 EEPROM Auto-Load . . . . . . . . . . . . . . . . . . . . . . 99
7.2.8 Boot PROM/FLASH . . . . . . . . . . . . . . . . . . . . . . 100
7.2.9 100BASE-TX Transmit . . . . . . . . . . . . . . . . . . . 101
7.2.10 10BASE-T Transmit End of Packet . . . . . . . . . 102
7.2.11 10 Mb/s Jabber Timing . . . . . . . . . . . . . . . . . . 102
7.2.12 10BASE-T Normal Link Pulse . . . . . . . . . . . . . 103
7.2.13 Auto-Negotiation Fast Link Pulse (FLP) . . . . . . 103
7.2.14 Media Independent Interface (MII) . . . . . . . . . . 104
List of Figures
Figure 3-1
DP83816 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 3-2
MAC/BIU Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 3-3
Ethernet Packet Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 3-4
DSP Physical Layer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 3-5
LED Loading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 3-6
100BASE-TX Transmit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 3-7
Binary to MLT-3 conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 3-8
100 M/bs Receive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 3-9
100BASE-TX BLW Event Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 3-10
EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 meters of CAT V cable . . . . . . . .24
Figure 3-11
MLT-3 Signal Measured at AII after 0 meters of CAT V cable. . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 3-12
MLT-3 Signal Measured at AII after 50 meters of CAT V cable. . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 3-13
MLT-3 Signal Measured at AII after 100 meters of CAT V cable. . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 3-14
10BASE-T Twisted Pair Smart Squelch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 3-15
Typical MDC/MDIO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 3-16
Typical MDC/MDIO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 4-1
Pattern Buffer Memory - 180h words (word = 18bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Figure 4-2
Hash Table Memory - 40h bytes addressed on word boundaries . . . . . . . . . . . . . . . . . . . . . . . .62
Figure 5-1
Single Descriptor Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Figure 5-2
Multiple Descriptor Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Figure 5-3
List and Ring Descriptor Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Figure 5-4
Transmit Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Figure 5-5
Transmit State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Figure 5-6
Receive Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Figure 5-7
Receive State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
List of Tables
Table 3-1
4B5B Code-Group Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 3-2
Typical MDIO Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 4-1
Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 4-2
Operational Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 4-3
MIB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 5-1
DP83816 Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Table 5-2
cmdsts Common Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Table 5-3
Transmit Status Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Table 5-4
Receive Status Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Table 5-5
Transmit State Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table 5-6
Receive State Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 6-1
Power Management Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 6-2
PM Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
4
www.national.com
DP83816
1.0 Connection Diagram
1.1 144 LQFP Package (VNG)
For Normal Operating Temperature - Order Number DP83816AVNG
See NS Package Number VNG144A
121
122
123
124
125
126
127
128
129
130
131
132
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
30
31
32
33
29
Identification
Pin1
37
38
39
40
120
119
118
117
116
115
114
113
112
110
109
111
DEV
SEL
N
T
RDY
N
IRDY
N
FRAMEN
CBEN2
AD16
AD17
AD18
STOP
N
PE
RRN
SE
RRN PA
R
CBEN1
AD15 AD14
AD13 AD12 AD11
AD10
AD9
VSS
AD8
AD19
AD20
AD21
AD22
AD23
I
D
SEL VSS
PCI
V
DD
NC
PCIV
DD
NC
V
SS
PCI
V
DD
CBEN3
AD24
AD25
AD26
CBEN0
VSS
AUXVDD
RESERVED
VREF
PCIVDD
AD29
AD31
VSS
REQN
GNTN
RSTN
INTAN
AD28
PCICLK
AD30
PMEN/CLKRUNN
VSS
VSS
TPTDP
TPTDM
REGEN
IAUXVDD
VSS
TPRDP
TPRDM
VSS
AD27
AD7
AD6
AD5
VSS
MA1/LED10N
MA2/LED100N
MA3
/
E
E
DI
MA4
/
E
E
CLK
MA5
MWRN
MD4/EEDO
MD3
EESEL
AD0
AD1
AD2
AD3
AD4
MD0
MCSN
MD1/CFGDISN
MD2
MD5
MD6
MD7
MA0/LEDACTN
PCIVDD
VS
S
C1
NC
NC
AUXVDD
VSS
MDI
O
MDC
RXCLK
RXD0/MA6
RXD1/MA7
RXD2/MA8
RXD3/MA9
RXOE
RXE
R
/MA1
0
RXDV
/MA1
1
TXD3/MA1
5
COL
/
MA
16
CRS
TXEN
TXCLK
TXD2/MA1
4
TXD1/MA1
3
TXD0/MA1
2
VS
S
AUX
V
DD
VS
S
AUX
V
DD
X2 X1
DP83816
NC
VS
S
AUX
V
DD
NC
3VAUX
36 35 34
67
68
69
70
71
72
100 101 102 103 104 105 106 107 108
144
143
142
141
140
139
138
137
136
135
134
133
VSS
IAUXVDD
PWRGOOD
MRDN
AUXVDD
NC VS
S
VS
S
AUX
V
DD
NC
RESERVED
NC
NC
RESERVED
VSS
5
www.national.com
DP83816
2.0 Pin Description
PCI Bus Interface
Symbol
LQFP Pin
No(s)
Dir
Description
AD[31-0]
66, 67, 68, 70,
71, 72, 73, 74,
78, 79, 81, 82,
83, 86, 87, 88,
101, 102, 104,
105, 106, 108,
109, 110, 112,
113, 115, 116,
118, 119, 120,
121
I/O
Address and Data: Multiplexed address and data bus. As a bus master, the
DP83816 will drive address during the first bus phase. During subsequent phases,
the DP83816 will either read or write data expecting the target to increment its
address pointer. As a bus target, the DP83816 will decode each address on the bus
and respond if it is the target being addressed.
CBEN[3-0]
75,
89,
100,
111
I/O
Bus Command/Byte Enable: During the address phase these signals define the
"bus command" or the type of bus transaction that will take place. During the data
phase these pins indicate which byte lanes contain valid data. CBEN[0] applies to
byte 0 (bits 7-0) and CBEN[3] applies to byte 3 (bits 31-24) in the Little Endian
Mode. In Big Endian Mode, CBEN[3] applies to byte 0 (bits 31-24) and CBEN[0]
applies to byte 3 (bits 7-0).
PCICLK
60
I
Clock: This PCI Bus clock provides timing for all bus phases. The rising edge
defines the start of each phase. The clock frequency ranges from 0 to 33 MHz.
DEVSELN
95
I/O
Device Select: As a bus master, the DP83816 samples this signal to insure that the
destination address for the data transfer is recognized by a PCI target. As a target,
the DP83816 asserts this signal low when it recognizes its address after FRAMEN
is asserted.
FRAMEN
91
I/O
Frame: As a bus master, this signal is asserted low to indicate the beginning and
duration of a bus transaction. Data transfer takes place when this signal is asserted.
It is de-asserted before the transaction is in its final phase. As a target, the device
monitors this signal before decoding the address to check if the current transaction
is addressed to it.
GNTN
63
I
Grant: This signal is asserted low to indicate to the DP83816 that it has been
granted ownership of the bus by the central arbiter. This input is used when the
DP83816 is acting as a bus master.
IDSEL
76
I
Initialization Device Select: This pin is sampled by the DP83816 to identify when
configuration read and write accesses are intended for it.
INTAN
61
O
Interrupt A: This signal is asserted low when an interrupt condition occurs as
defined in the Interrupt Status Register, Interrupt Mask, and Interrupt Enable
registers.
IRDYN
92
I/O
Initiator Ready: As a bus master, this signal will be asserted low when the
DP83816 is ready to complete the current data phase transaction. This signal is
used in conjunction with the TRYDN signal. Data transaction takes place at the
rising edge of PCICLK when both IRDYN and TRDYN are asserted low. As a target,
this signal indicates that the master has put the data on the bus.
PAR
99
I/O
Parity: This signal indicates even parity across AD[31-0] and CBEN[3-0] including
the PAR pin. As a master, PAR is asserted during address and write data phases.
As a target, PAR is asserted during read data phases.
PERRN
97
I/O
Parity Error: The DP83816 as a master or target will assert this signal low to
indicate a parity error on any incoming data (except for special cycles). As a bus
master, it will monitor this signal on all write operations (except for special cycles).
REQN
64
O
Request: The DP83816 will assert this signal low to request ownership of the bus
from the central arbiter.
RSTN
62
I
Reset: When this signal is asserted all outputs of DP83816 will be in TRI-STATE
and the device will be put into a known state.
PDF 
ZIP