1997 National Semiconductor Corportation
www.national.com
D
P
83
856
B 10
0 M
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/
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Rep
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for
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Bas
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N
PRELIMINARY
October 1997
DP83856B 100 Mb/s Repeater Information Base
General Description
The DP83856B 100 Mb/s Repeater Information
Base is designed specifically to meet the
management demands of today's high speed
Ethernet networking systems.
The DP83856B simplifies design of managed
multiport repeaters. Used in conjunction with up to
16 DP83850s it enables a repeater system to
become a single managed entity that is fully
compatible with the IEEE 802.3u clause 30
management requirements.
The DP83856B device incorporates all the
necessary functions and counters for collecting
network statistics. Information is gathered on a
per-packet, per-port basis: the port which is
receiving the packet is the active port for statistics
collection.
Features
Supports up to 16 DP83850 Repeater Interface
Controllers (192, 100Mb ports on one segment)
Fully IEEE 802.3u clause 30 compatible
Network management statistics processed on a
per activity (per packet) basis
Programmed I/O interface for statistics reporting
Uses external SRAM to maintain per port
network management statistics counters
Single interrupt acknowledgment provides
report on all per port SRAM based and P83856B
based statistics
Parallel register interface to CPU (16-bit)
Allows indirect access to the DP83850
Repeater Interface Controller and DP83840
Physical Layer Device serial registers through a
parallel register interface
132 pin PQFP
System Diagram
Man agement
CPU
Management
Memory/Cod e
Management
I/O Device/s
DP83856
100 Mb/s
Repeater Information Base
Statistics
SRAM
DP83850 100 Mb/s Repeater
Interface Controller
100 Mb/s
PHY #1
CPU Bus
Inter Repeater Bus, TX Bus and
Seri al Management Bus Si gnals
100 Mb/s
PHY #2
100 Mb/s
PHY #12
DP83850 100 Mb/s Repeater
In terface Controller
100 Mb/s
P HY #13
100 Mb/s
PHY #14
100 Mb/s
PHY #24
TRI-STATE
is a registered trademark of National Semiconductor corporation.
B
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2
Block Diagram
-IR_COL, -IRD_V, MD[3:0],
M_CK, -M_DV, -M_ER
RR
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CR-
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www.national.com
3
Table of Contents
1.0
Pin Connection Diagram
2.0 Pin
Description
2.1
CPU Interface
2.2 SRAM
Interface
2.3
Transmit Bus and Management Bus
2.4 MII
Interface
2.5 Test
Interface
2.6 Miscellaneous
2.7
Pin Type Designation
3.0 Functional
Description
3.1 Statistics
Generation
3.2 SRAM
Interface
3.3 SRAM
Arbiter
3.4
Interrupt Generation and Control
3.5
MII Register Interface
3.6
CPU Register Block
4.0 Registers
4.1
Register Memory Map
4.2
Configuration Register
4.3
Interrupt Register
4.4
SRAM Interface Register
4.5
MII Management Interface Register
4.6
SRAM Write Data Register
4.7
MII Write Data Register
4.8
Device ID Register
4.9
SRAM Read Data Registers
4.10 Carrier Count Register
4.11 Oct_Nib Count Register
4.12 Network Counters
4.13 MII Read Data Registers
5.0
A.C. & D.C. Specifications
5.1
D.C. Specifications
5.2
A.C. Specifications
6.0 System Considerations
6.1 Lost MII Read Error Status Events
6.2 Sixty-Three Byte Packet Counting
6.3 Initial Packet Logging
6.4 Random Activity On Management Interface
6.5 Symbol Error During Packet Count
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4
1.0 Pin Connection Diagram
DP83856
100 Mb/s
Repeater Information
Base
132 pin PQFP
(top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
13
2
13
1
13
0
12
9
12
8
12
7
12
6
12
5
12
4
12
3
12
2
12
1
12
0
11
9
11
8
11
7
116
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
3 5
3 6
3 7
3 8
3 9
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
4 8
4 9
5 0
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
GN
D
VC
C
-I
R
D
_
V
-R
S
T
LC
TX
D
0
TX
D
1
GN
D
VC
C
TX
D
2
TX
D
3
TX
_
R
D
Y
TX
_
E
R
-I
R
_
C
O
L
-T
E
S
T
_
H
_
L
-T
E
S
T
_
E
N
-
T
ST
AT
E
NC
-N
A
N
D
_
O
-N
A
N
D
_
E
-M
_
E
R
-M
_
D
V
M_
C
K
GN
D
VC
C
MD
3
MD
2
MD
1
MD
0
NC
NC
NC
NC
GND
VCC
C D0
C D1
C D2
C D3
C D4
GND
VCC
C D5
GND
VCC
C D6
C D7
GND
VCC
C D8
C D9
CD 10
CD 11
CD 12
CD 13
GND
VCC
CD 14
CD 15
-C IN T
CR -W
GND
VCC
-CCS
GND
VCC
NC
GN D
VCC
-SOE
-SCS
SR-W
SA0
SA1
SA2
VCC
SA4
SA5
SA6
SA7
SA8
GN D
VCC
SA9
SA10
SA11
GN D
VCC
SA12
RES2
RES1
GN D
VCC
RDIO
RDC
RRD IR
-SDV
NC
CA
7
CA
6
CA
5
CA
4
GN
D
VC
C
CA
2
CA
1
-
C
RDY
GN
D
VC
C
SD
1
5
GN
D
VC
C
SD
1
3
SD
1
2
SD
1
1
SD
1
0
SD
9
SD
8
SD
7
SD
6
GN
D
VC
C
SD
5
SD
4
SD
3
SD
2
SD
1
SD
0
CA
3
SA3
GN D
SD
1
4
Order Number DP83856BVF
NS Package Number VF132A
DP83856B
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5
2.0 Pin Descriptions
2.1 CPU Interface
The CPU interface pins are a set of generic interface signals designed to accommodate many different CPU
types with minimal external logic. The data interface is 16-bits wide and does not provide any steering
capabilities. Furthermore, all accesses must be aligned on 16-bit boundaries, as indicated in the CPU
Register map section 4.0.
2.2 SRAM Interface
The SRAM interface pins are used to connect the DP83856B to a fast (20ns) external SRAM. The DP83856B
supports up to an 8K x 16 bit SRAM configuration.
Signal Name
Type
Active
Description
-CINT
O/Z, L
Low
CPU Interrupt: Indicates that the DP83856B has at least
one interrupt pending. The -CINT signal will remain active
until the CPU reads the Interrupt Register. It is software's
responsibility to keep track of multiple interrupts pending,
and service all of the interrupts.
-CRDY
O/Z, L
Low
CPU Ready: Indicates that the DP83856B is ready to
terminate the current cycle. The DP83856B asserts -CRDY
on writes once it has strobed the data into its write data
holding register. The DP83856B asserts -CRDY on reads
once it has strobed data into its read data output register.
-CCS
I
Low
CPU Chip Select: Chip select for internal DP83856B
registers. Generated by external logic as an address
decode of the DP83856B register space. -CCS must remain
valid for the entire cycle.
CR-W
I
-
CPU Read-Write: Read/Write strobe for DP83856B internal
registers.
Read = 1, Write = 0.
CA[7:1]
I
-
CPU Address [7:1]: Address bus for DP83856B register
accesses. The DP83856B latches the address for internal
use within 45ns of -CCS being asserted.
CD[15:0]
I/O/Z, M
-
CPU Data [15:0]: 16-bit data bus for DP83856B register
accesses. CD[15:0] correspond to the low 16-bits of data
on the CPU. The DP83856B implements Big Endian
convention for data storage. All CPU register accesses
should be 16-bit accesses aligned on 16-bit boundaries.
Signal Name
Type
Active
Description
SA[12:0]
O/Z, L
-
SRAM Address [12:0]: The SRAM address bus should be
directly connected to the fast external SRAM's address
inputs.
SD[15:0]
I/O/Z/P, L
-
SRAM Data [15:0]: The SRAM data bus should be directly
connected to the fast external SRAM's data pins.
SR-W
O/Z,L
-
SRAM Read-Write: Should be directly connected to the fast
external SRAM's write enable pin.
Read = 1, Write = 0.
-SCS
O/Z, L
Low
SRAM Chip Select: Should be directly connected to the fast
external SRAM's chip select pin.
-SOE
O/Z, L
Low
SRAM Output Enable: Should be directly connected to the
fast external SRAM's (active low) output enable pin.
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