DP
8
392
4BV
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1998 National Semiconductor Corporation
www.national.com
October 1998
DP83924BVCE
Quad 10 Mb/s Ethernet Physical Layer - 4TPHYTM
General Description
The DP83924B Quad 10Mbps Ethernet Physical Layer
(4TPHY) is a 4-Port Twisted Pair PHYsical Layer Trans-
ceiver that includes all the circuitry required to interface
four Ethernet Media Access Controllers (MACs)
to
10BASE-T. This device is ideally suited for switch hub
applications where 8 to 32 ports are commonly used.
The 4TPHY has three dedicated 10Base-T ports. There is
an additional port that is selectable for either 10Base-T or
for an Attachment Unit Interface (AUI). In 10Base-T mode,
any port can be configured to be Half or Full Duplex.
(Continued)
Features
s
100 pin package
s
10BASE-T and AUI interfaces
s
Automatic or manual selection of twisted pair or Attach-
ment Unit Interfaces on port 1
s
Direct Interface to NRZ Compatible controllers
s
IEEE 802.3u Auto-Negotiation between 10Mb/s Full
and Half Duplex data traffic and parallel detection
s
MII-like Serial management interface for configuration
and monitoring of ENDEC/Transceiver operation.
System Diagram
IS
OL
A
T
I
O
N
D
P
8392
C
AUI
TPI
MAC Serial
NRZ Interface
10BASE-T
IS
O
L
A
T
IO
N
DP83924B
10BASE-2
Serial Mgmt Interface
TXD4,TXE4
RXD4,RXC4,COL4,CRS4
(port 1 option)
MAC
TXD3,TXE3
RXD3,RXC3,COL3,CRS3
TXD2,TXE2
RXD2,RXC2,COL2,CRS2
TXD1,TXE1
RXD1,RXC1,COL1,CRS1
TXC
ports 1-4
MDIO
MDC
s
Programmable MAC Interface supports most
standard 7 signal MAC interfaces
s
Twisted Pair Transceiver Module
On-chip filters for transmit outputs
Low Power Driver
Heartbeat and Jabber Timers
Link Disable and Smart Receive Squelch
Polarity detection and correction
Jabber Enable/Disable
Isolate mode for diagnostics
Low Power Class AB Attachment Unit Interface (AUI)
Driver for one port
Enhanced Supply Rejection
Enhanced Jitter Performance
Diagnostic Endec Loopback
Squelch on Collision and Receive Pair
s
Serial LED interface for LINK, POLARITY, ACTIVITY,
and ERROR.
s
JTAG Boundary Scan per IEEE 1149.1
4TPHYTM is a trademark of National Semiconductor Corporation.
TRI-STATE
is a registered trademark of National Semiconduct or Corporation.
General Description
(Continued)
2
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The various modes on the 4TPHY can be configured and
controlled via the MII management interface. This manage-
ment interface makes inter-operability with other manufac-
turers MAC units
relatively easy. If no management
interface is desired, most of the critical operating modes of
the transceiver can be set via strapping options (latching
configuration information during reset). The ENDEC sec-
tion of the transceiver also supplies a simple Non-Return-
to-Zero (NRZ) interface to transmit and receive data
to/from standard 10 Mb/s MACs.
The transceivers include on-chip filtered transmit outputs,
which reduce emissions and eliminate the need for exter-
nal filter.
The DP83924BVCE maintains complete hardware and
software backwards compatibility with the DP83924AVCE
with only a change to one resistor value and disconnecting
a second resistor.
Block Diagram
Output
Driver
Trans-
mit
Filter
Transmit
Pre-emphasis
/TX Logic
Link
Genera-
tor
Manches-
ter Encoder
Transmit
AUI
Driver
Transmit
Control
Interface
TXE
TXD
TXC
Oscilla-
tor Pres-
caler
X1
Management
Control Inter-
face
MDC
MDIO
Smart
Squelch
Link
Detect
Phase
Lock
Loop
Receive
Control
Interface
/decoder
CRS
RXD
RXC
MUX
TP
Rcv
+
-
AUI Rcv
+
-
+
-
Collision
Decoder
/Translator
COL
Heartbeat
Jabber
MUX
Common
Analog
/PLL for
Wave
Shapers
Transceiver
+ ENDEC Block
(replicated 4
times)
AUI Colli-
sion
TPLBK
AUI
Configu-
ration
Registers
RXI+
RXI-
TXU+
TXU-
CD+
CD-
TX+
TX-
RX+
RX-
LED_CLK
LED_DATA
LED Control
Interface
A
UI P
ort 1 only
A
UI P
o
r
t
1 only
3
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Table of Contents
1.0
Pin Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1
Pin Connection Diagram . . . . . . . . . . . . . . . . . . . . 4
1.2
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.0
Interface Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.1
Management Interface . . . . . . . . . . . . . . . . . . . . . .9
2.2
MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.3
LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.4
Network Interface . . . . . . . . . . . . . . . . . . . . . . . . .10
3.0
Detailed Functional Description . . . . . . . . . . . . . . . . .14
3.1
Twisted Pair Functional Description . . . . . . . . . . 14
3.2
ENDEC Module . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.3
Additional Features . . . . . . . . . . . . . . . . . . . . . . .15
3.4
Auto-negotiation Block . . . . . . . . . . . . . . . . . . . . .17
3.5
JTAG Boundary Scan . . . . . . . . . . . . . . . . . . . . .18
4.0
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .21
4.1
Register Map and Descriptions . . . . . . . . . . . . . .21
5.0
Application Information . . . . . . . . . . . . . . . . . . . . . . . .27
5.1
Magnetics Specifications . . . . . . . . . . . . . . . . . . .27
5.2
Layout Considerations . . . . . . . . . . . . . . . . . . . . .27
5.3
LED interface considerations . . . . . . . . . . . . . . . .28
6.0
User Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6.1
CRS Assertion Connected to a 100M Node . . . . 29
6.2
Link Fail Inhibit Timer . . . . . . . . . . . . . . . . . . . . . .29
6.3
Lockup during duplex mode change: . . . . . . . . . . 29
6.4
Start of TP_IDL, 45 Bit Times to 50 mV: . . . . . . . 29
6.5
Polarity detection: . . . . . . . . . . . . . . . . . . . . . . . .29
6.6
Link pulse template: . . . . . . . . . . . . . . . . . . . . . . .30
7.0
AC and DC Electrical Specifications . . . . . . . . . . . . .31
7.1
DC Specifications . . . . . . . . . . . . . . . . . . . . . . . .31
7.2
AC Switching Specifications . . . . . . . . . . . . . . . .32
8.0
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . .42
4
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1.0 Pin Information
1.1 Pin Connection Diagram
Figure 1. 100-Pin Plastic Quad Flat Pack (PQFP) Pinout
VDD_DIG
LED_CLK
LED_DATA
LINK_3, INT
LPBK, MDC
LINK_4, MDIO
X1
GND_CLK
VDD_CLK
NC
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
TX
+
97
98
99
100
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
TC
K
TD
O
TX
C
RX
C
[
1
]
CO
L
[
1
]
CRS
[
1
]
RX
D
[
1
]
T
XE[
1
]
TX
D
[
1
]
G
ND_
W
S
P
L
L
_
1
VD
D
_
W
S
PL
L
_
1
64
63
62
61
VD
D
_
1
RX
C
[
2
]
CO
L
[
2
]
CRS
[
2
]
60
59
58
57
56
55
RX
D
[
2
]
T
XE[
2
]
TX
D
[
2
]
RX
C
[
3
]
CO
L
[
3
]
G
ND_
1
54
53
52
51
CRS
[
3
]
RX
D
[
3
]
TXE[3]
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
VDD_WS_1
RXC[4]
COL[4]
CRS[4]
RXD[4]
TXE[4]
TXD[4]
G
ND_
P
L
L
_
4
G
ND_
P
L
L
_
3
V
D
D
_
P
L
L_2
G
ND_
P
L
L
_
2
V
D
D
_
P
L
L_1
G
ND_
P
L
L
_
1
RESET
34
33
32
31
FDX[4]
FDX[3]
FDX[2]
CD+
CD-
RX
+
RX
I
1
-
V
DD_
T
P
I
_
1
G
ND_
T
P
I
_
1
TX
U
1
+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DP83924B
TX
U
1
-
TX
U
2
+
TX
U
2
-
V
DD_
T
P
I
_
2
RX
I
2
-
RX
I
3
+
RX
I
3
-
V
DD_
T
P
I
_
3
G
ND_
T
P
I
_
3
TX
U
3
+
TX
U
3
-
TX
U
4
+
G
ND_
T
P
I
_
4
RX
I
4
+
RX
I
4
-
RX
-
RX
I
1
+
G
ND_
T
P
I
_
2
RX
I
2
+
TX
U
4
-
V
DD_
T
P
I
_
4
GND_WS_1
TXD[3]
NC
NC
TX
-
NC
GND_DIG
LINK_1
LINK_2
FDX[1]
ROC
RESERVED
NC
NC
NC
NC
TDI
TMS
TRST
GND_2
Order Number DP83924BVCE
NS Package Number VCE100A
1.0 Pin Information
(Continued)
5
www.national.com
1.2 Pin Description
Table 1. NRZ CONTROLLER INTERFACE and MANAGEMENT INTERFACE.
These pins provide the interface signalling between the Media Access Controller and the transceiver. (30 Pins)
Symbol
Pin #
Type
Description
TXC
77
O
Transmit Clock: This pin outputs a 10 MHz output clock signal synchronized to the
transmit data (for all ports).
TXD[4]
TXD[3]
TXD[2]
TXD[1]
40
46
56
71
I
Transmit Data: The serial TXD contains the transmit serial data output stream.
TXE[4]
TXE[3]
TXE[2]
TXE[1]
41
47
57
72
I
Transmit Enable: This active high input indicates the presence of valid data on the TXD
pins.
CRS[4]
CRS[3]
CRS[2]
CRS[1]
43
52
59
74
O, pull-up
O, pull-up
O, pull-up
O, pull-up
Carrier Sense: Active high output indicates that valid data has been detected on the
receive inputs.
CRS[3:1] are dual purpose pins. When RESET is active, the value on these pins are
sampled to determine the transceiver address for the mgmt interface. These pins have
internal pull-ups, a 2.7 k
pull down resistor is required to program a logic `0'.
COL[4]
COL[3]
COL[2]
COL[1]
44
54
60
75
O, pull-up
O, pull-up
O, pull-up
O, pull-up
Collision: This active high output is asserted when a collision condition has been de-
tected. It is also asserted for 1
s at the end of a packet to indicate the SQE test function.
COL[4:1] are dual purpose pins. When RESET is active, these pins are sampled and
selects the operating mode for the device. These pins have internal pull-ups to select
the default mode if no external pull-downs are connected. To select the non-default
mode(s), a 2.7 k
pull down resistor(s) is required. The strappable functions are:
COL[4]; selects the number of receive clocks after carrier sense deassertion (5 RXCs
or continuous RXCs). Default is 5 RXCs.
COL[3]; enables or disables the receive filter. Default is to disable the receive filter.
COL[2]; Disables Management Interface and selects the Full Duplex operating mode
(normal or enhanced). Default is normal full duplex mode. If the enhanced Full- Duplex
mode is selected, the functions of pins 89, 90, 92, 93, and 94 are also changed. See
the descriptions in Sectio n3.3.13 and Se ction3.3.14.
COL[1]; selects the LED operating mode (normal or enhanced). Default is normal LED
mode.
RXC[4]
RXC[3]
RXC[2]
RXC[1]
45
55
61
76
O
Receive Clock: This 10 MHz signal is generated by the transceiver, and is the recov-
ered clock from the decoded network data stream. This signal is 10 MHz.
The number of RXCs after the deassertion of CRS is programmable via the Global Con-
figuration Register, GATERXC bit, D0. The options are for 5 RXCs or continuous RXCs.
RXD[4]
RXD[3]
RXD[2]
RXD[1]
42
51
58
73
O, Pull-up Receive Data: Provides the decoded receive serial data. Data is valid on the risin
edge of RXC.
RXD[4:1] are dual purpose pins. When RESET is active, these pins are sampled and
selects the operating mode for the device. These pins have internal pull-ups to select
the default mode if no external pull-downs are connected. To select the non-default
mode(s), a 2.7 k
pull down resistor(s) is required. The strappable functions are:
RXD[4] enables/disables Auto-Negotiation.
RXD[3:1] selects one of five MAC interface modes. See the table in the Interface De-
scriptions section.
MDC
LPBK
93 I
Management Data Clock: When management interface is enabled (strap option,
COL[2]=1), this clock signal (0-2.5MHz) is the clock for transferring data across the
management interface.
LoopBack: When "Disable Management Interface" mode is selected (strap option,
COL[2]=0), then this pin is an active high input to configure all ports into diagnostic loop-
back mode.
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