DS90CF384A/DS90CF364A
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD)
Link--65 MHz,
+3.3V LVDS Receiver 18-Bit Flat Panel
Display (FPD) Link--65 MHz
General Description
The DS90CF384A receiver converts the four LVDS data
streams (Up to 1.8 Gbps throughput or 227 Megabytes/sec
bandwidth) back into parallel 28 bits of CMOS/TTL data (24
bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also
available is the DS90CF364A that converts the three LVDS
data streams (Up to 1.3 Gbps throughput or 170 Megabytes/
sec bandwidth) back into parallel 21 bits of CMOS/TTL data
(18 bits of RGB and 3 bits of Hsync, Vsync and DE). Both
Receivers' outputs are Falling edge strobe. A Rising edge or
Falling edge strobe transmitter (DS90C383A/DS90C363A)
will interoperate with a Falling edge strobe Receiver without
any translation logic.
The DS90CF384A / DS90CF364A devices are enhanced
over prior generation receivers and provided a wider data
valid time on the receiver output.
The DS90CF384A is also offered in a 64 ball, 0.8mm fine
pitch ball grid array (FBGA) package which provides a 44 %
reduction in PCB footprint compared to the 56L TSSOP
package.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n
20 to 65 MHz shift clock support
n
50% duty cycle on receiver output clock
n
BestinClass Set & Hold Times on RxOUTPUTs
n
Rx power consumption
<
142 mW (typ)
@
65MHz
Grayscale
n
Rx Power-down mode
<
200W (max)
n
ESD rating
>
7 kV (HBM),
>
700V (EIAJ)
n
Supports VGA, SVGA, XGA and Dual Pixel SXGA.
n
PLL requires no external components
n
Compatible with TIA/EIA-644 LVDS standard
n
Low profile 56-lead or 48-lead TSSOP package
n
DS90CF384A is also available in a 64 ball, 0.8mm fine
pitch ball grid array (FBGA) package
Block Diagrams
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
DS90CF384A
DS100870-27
Order Number DS90CF384AMTD or DS90CF384ASLC
See NS Package Number MTD56 or SLC64A
DS90CF364A
DS100870-28
Order Number DS90CF364AMTD
See NS Package Number MTD48
November 2000
DS90CF384A/DS90CF364A
+3.3V
L
VDS
Receiver
24-Bit-Color
Flat
Panel
Display
(FPD)
Link
--
6
5
MHz
,
+3.3V
L
VDS
Receiver
18-Bit-Color
Flat
Panel
Display
(FPD)
Link
--
6
5
MHz
2000 National Semiconductor Corporation
DS100870
www.national.com
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.3V to +4V
CMOS/TTL Input Voltage
-0.3V to (V
CC
+ 0.3V)
CMOS/TTL Output Voltage
-0.3V to (V
CC
+ 0.3V)
LVDS Receiver Input Voltage
-0.3V to (V
CC
+ 0.3V)
Junction Temperature
+150C
Storage Temperature
-65C to +150C
Lead Temperature
(Soldering, 4 sec)
+260C
Solder Reflow Temperature
(20 sec for FBGA)
+220C
Maximum Package Power
Dissipation Capacity
@
25C
MTD56 (TSSOP) Package:
DS90CF384A
1.61 W
MTD48 (TSSOP) Package:
DS90CF364A
1.89 W
SLC (FBGA) Package:
DS90CF384A
2.0 W
Package Derating:
DS90CF384AMTD
12.4 mW/C above +25C
DS90CF364AMTD
15 mW/C above +25C
DS90CF384ASLC
10.2 mW/C above +25C
ESD Rating
(HBM, 1.5 k
, 100 pF)
>
7 kV
(EIAJ, 0
, 200 pF)
>
700V
Recommended Operating
Conditions
Min
Nom
Max
Units
Supply Voltage (V
CC
)
3.0
3.3
3.6
V
Operating Free Air
Temperature (T
A
)
-10
+25
+70
C
Receiver Input Range
0
2.4
V
Supply Noise Voltage (V
CC
)
100
mV
PP
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS/TTL DC SPECIFICATIONS (For PowerDown Pin)
V
IH
High Level Input Voltage
2.0
V
CC
V
V
IL
Low Level Input Voltage
GND
0.8
V
V
CL
Input Clamp Voltage
I
CL
= -18 mA
-0.79
-1.5
V
I
IN
Input Current
V
IN
= 0.4V, 2.5V or V
CC
+1.8
+10
A
V
IN
= GND
-10
0
A
CMOS/TTL DC SPECIFICATIONS
V
OH
High Level Output Voltage
I
OH
= -0.4 mA
2.7
3.3
V
V
OL
Low Level Output Voltage
I
OL
= 2 mA
0.06
0.3
V
I
OS
Output Short Circuit Current
V
OUT
= 0V
-60
-120
mA
LVDS RECEIVER DC SPECIFICATIONS
V
TH
Differential Input High Threshold
V
CM
= +1.2V
+100
mV
V
TL
Differential Input Low Threshold
-100
mV
I
IN
Input Current
V
IN
= +2.4V, V
CC
= 3.6V
10
A
V
IN
= 0V, V
CC
= 3.6V
10
A
RECEIVER SUPPLY CURRENT
ICCRW
Receiver Supply Current
C
L
= 8 pF,
f = 32.5 MHz
49
65
mA
Worst Case
Worst Case Pattern,
f = 37.5 MHz
53
70
mA
DS90CF384A
(Figures
1, 4 )
f = 65 MHz
81
105
mA
ICCRW
Receiver Supply Current
C
L
= 8 pF,
f = 32.5 MHz
49
55
mA
Worst Case
Worst Case Pattern,
f = 37.5 MHz
53
60
mA
DS90CF364A
(Figures
1, 4 )
f = 65 MHz
78
90
mA
ICCRG
Receiver Supply Current,
C
L
= 8 pF,
f = 32.5 MHz
28
45
mA
16 Grayscale
16 Grayscale Pattern,
f = 37.5 MHz
30
47
mA
(Figures 2, 3, 4 )
f = 65 MHz
43
60
mA
ICCRZ
Receiver Supply Current
Power Down = Low
10
55
A
Power Down
Receiver Outputs Stay Low during
Power Down Mode
DS90CF384A/DS90CF364A
www.national.com
2
Electrical Characteristics
(Continued)
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation.
Note 2: Typical values are given for V
CC
= 3.3V and T
A
= +25C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V
OD
and
V
OD
).
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Units
CLHT
CMOS/TTL Low-to-High Transition Time
(Figure 4 )
2
5
ns
CHLT
CMOS/TTL High-to-Low Transition Time
(Figure 4 )
1.8
5
ns
RSPos0
Receiver Input Strobe Position for Bit 0
(Figure 11,
Figure 12 )
f = 65 MHz
0.7
1.1
1.4
ns
RSPos1
Receiver Input Strobe Position for Bit 1
2.9
3.3
3.6
ns
RSPos2
Receiver Input Strobe Position for Bit 2
5.1
5.5
5.8
ns
RSPos3
Receiver Input Strobe Position for Bit 3
7.3
7.7
8.0
ns
RSPos4
Receiver Input Strobe Position for Bit 4
9.5
9.9
10.2
ns
RSPos5
Receiver Input Strobe Position for Bit 5
11.7
12.1
12.4
ns
RSPos6
Receiver Input Strobe Position for Bit 6
13.9
14.3
14.6
ns
RSKM
RxIN Skew Margin (Note 4)
(Figure 13 )
f = 65 MHz
400
ps
RCOP
RxCLK OUT Period
(Figure 5)
15
T
50
ns
RCOH
RxCLK OUT High Time
(Figure 5 )
f = 65 MHz
5.0
7.6
9.0
ns
RCOL
RxCLK OUT Low Time
(Figure 5)
5.0
6.3
9.0
ns
RSRC
RxOUT Setup to RxCLK OUT
(Figure 5 )
4.5
7.3
ns
RHRC
RxOUT Hold to RxCLK OUT
(Figure 5 )
4.0
6.3
ns
RCCD
RxCLK IN to RxCLK OUT Delay 25C, V
CC
= 3.3V
(Figure 6 )
3.5
5.0
7.5
ns
RPLLS
Receiver Phase Lock Loop Set
(Figure 7 )
10
ms
RPDD
Receiver Power Down Delay
(Figure 10 )
1
s
Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the DS90C383A transmitter pulse
positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). The RSKM will change when different transmitters are
used. This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
AC Timing Diagrams
DS100870-2
FIGURE 1. "Worst Case" Test Pattern
DS90CF384A/DS90CF364A
www.national.com
3
AC Timing Diagrams
(Continued)
DS100870-12
FIGURE 2. "16 Grayscale" Test Pattern (DS90CF384A)(Notes 5, 6, 7, 8)
DS90CF384A/DS90CF364A
www.national.com
4
AC Timing Diagrams
(Continued)
Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 6: The 16 grayscale test pattern tests device power consumption for a "typical" LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 7:
Figures 1, 3
show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 8: Recommended pin to signal mapping. Customer may choose to define differently.
DS100870-3
FIGURE 3. "16 Grayscale" Test Pattern (DS90CF364A)(Notes 5, 6, 7, 8)
DS100870-4
FIGURE 4. DS90CF384A/DS90CF364A (Receiver) CMOS/TTL Output Load and Transition Times
DS100870-5
FIGURE 5. DS90CF384A/DS90CF364A (Receiver) Setup/Hold and High/Low Times
DS90CF384A/DS90CF364A
www.national.com
5
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