DS90CR287/DS90CR288A
+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel
Link-85 MHZ
General Description
The DS90CR287 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in par-
allel with the data streams over a fifth LVDS link. Every cycle
of the transmit clock 28 bits of input data are sampled and
transmitted. The DS90CR288A receiver converts the four
LVDS data streams back into 28 bits of CMOS/TTL data. At
a transmit clock frequency of 85 MHZ, 28 bits of TTL data are
transmitted at a rate of 595 Mbps per LVDS data channel.
Using a 85 MHZ clock, the data throughput is 2.38 Gbit/s
(297.5 Mbytes/sec).
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n
20 to 85 MHZ shift clock support
n
50% duty cycle on receiver output clock
n
BestinClass Set & Hold Times on TxINPUTs
n
Low power consumption
n
1V common mode range (around +1.2V)
n
Narrow bus reduces cable size and cost
n
Up to 2.38 Gbps throughput
n
Up to 297.5 Megabytes/sec bandwidth
n
345 mV (typ) swing LVDS devices for low EMI
n
PLL requires no external components
n
Rising edge data strobe
n
Compatible with TIA/EIA-644 LVDS standard
n
Low profile 56-lead TSSOP package
Block Diagrams
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
DS90CR287
DS101087-1
Order Number DS90CR287MTD
See NS Package Number MTD56
DS90CR288A
DS101087-27
Order Number DS90CR288AMTD
See NS Package Number MTD56
October 1999
DS90CR287/DS90CR288A
+3.3V
Rising
Edge
Data
Strobe
L
VDS
28-Bit
Channel
Link-85
MHZ
1999 National Semiconductor Corporation
DS101087
www.national.com
Pin Diagrams
Typical Application
DS90CR287
DS101087-21
DS90CR288A
DS101087-22
DS101087-23
DS90CR287/DS90CR288A
www.national.com
2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.3V to +4V
CMOS/TTL Input Voltage
-0.5V to (V
CC
+
0.3V)
CMOS/TTL Output Voltage
-0.3V to (V
CC
+
0.3V)
LVDS Receiver Input Voltage
-0.3V to (V
CC
+
0.3V)
LVDS Driver Output Voltage
-0.3V to (V
CC
+
0.3V)
LVDS Output Short Circuit
Duration
Continuous
Junction Temperature
+150C
Storage Temperature
-65C to +150C
Lead Temperature
(Soldering, 4 sec.)
+260C
Maximum Package Power Dissipation
@
+25C
MTD56 (TSSOP) Package:
DS90CR287
1.63 W
DS90CR288A
1.61 W
Package Derating:
DS90CR287
12.5 mW/C above
+25C
DS90CR288A
12.4 mW/C above
+25C
ESD Rating
(HBM, 1.5k
, 100pF)
>
7kV
(EIAJ, 0
, 200pF)
>
700V
Latch Up Tolerance
@
+25C
>
300mA
Recommended Operating
Conditions
Min
Nom
Max
Units
Supply Voltage (V
CC
)
3.0
3.3
3.6
V
Operating Free Air
Temperature (T
A
)
-10
+25
+70
C
Receiver Input Range
0
2.4
V
Supply Noise Voltage (V
CC
)
100
mV
PP
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS/TTL DC SPECIFICATIONS
V
IH
High Level Input Voltage
2.0
V
CC
V
V
IL
Low Level Input Voltage
GND
0.8
V
V
OH
High Level Output Voltage
I
OH
= -0.4 mA
2.7
3.3
V
V
OL
Low Level Output Voltage
I
OL
= 2 mA
0.06
0.3
V
V
CL
Input Clamp Voltage
I
CL
= -18 mA
-0.79
-1.5
V
I
IN
Input Current
V
IN
= 0.4V, 2.5V or V
CC
+1.8
+15
A
V
IN
= GND
-10
0
A
I
OS
Output Short Circuit Current
V
OUT
= 0V
-60
-120
mA
LVDS DRIVER DC SPECIFICATIONS
V
OD
Differential Output Voltage
R
L
= 100
250
290
450
mV
V
OD
Change in V
OD
between
Complimentary Output States
35
mV
V
OS
Offset Voltage (Note 4)
1.125
1.25
1.375
V
V
OS
Change in V
OS
between
Complimentary Output States
35
mV
I
OS
Output Short Circuit Current
V
OUT
= 0V, R
L
= 100
-3.5
-5
mA
I
OZ
Output TRI-STATE
Current
PWR DWN = 0V,
1
10
A
V
OUT
= 0V or V
CC
LVDS RECEIVER DC SPECIFICATIONS
V
TH
Differential Input High Threshold
V
CM
= +1.2V
+100
mV
V
TL
Differential Input Low Threshold
-100
mV
I
IN
Input Current
V
IN
= +2.4V, V
CC
= 3.6V
10
A
V
IN
= 0V, V
CC
= 3.6V
10
A
DS90CR287/DS90CR288A
www.national.com
3
Electrical Characteristics
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TRANSMITTER SUPPLY CURRENT
I
CCTW
Transmitter Supply Current
Worst Case (with Loads)
R
L
= 100
,
C
L
= 5 pF,
Worst Case
Pattern
(
Figures 1, 2)
f = 33 MHz
31
45
mA
f = 40 MHz
32
50
mA
f = 66 MHz
37
55
mA
f = 85 MHz
42
60
mA
I
CCTZ
Transmitter Supply Current
Power Down
PWR DWN = Low
Driver Outputs in TRI-STATE
under Powerdown Mode
10
55
A
RECEIVER SUPPLY CURRENT
I
CCRW
Receiver Supply Current Worst
Case
C
L
= 8 pF,
Worst Case
Pattern
(
Figures 1, 3)
f = 33 MHz
49
70
mA
f = 40 MHz
53
75
mA
f = 66 MHz
81
114
mA
f = 85 MHz
96
135
mA
I
CCRZ
Receiver Supply Current Power
Down
PWR DWN = Low
Receiver Outputs Stay Low during
Powerdown Mode
140
400
A
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation.
Note 2: Typical values are given for V
CC
= 3.3V and T
A
= +25C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V
OD
and
V
OD
).
Note 4: V
OS
previously referred as V
CM
.
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Units
LLHT
LVDS Low-to-High Transition Time (
Figure 2)
0.75
1.5
ns
LHLT
LVDS High-to-Low Transition Time (
Figure 2)
0.75
1.5
ns
TCIT
TxCLK IN Transition Time (
Figure 4)
1.0
6.0
ns
TPPos0
Transmitter Output Pulse Position for Bit0 (
Figure 15)
f = 85 MHz
-0.20
0
0.20
ns
TPPos1
Transmitter Output Pulse Position for Bit1
1.48
1 . 68
1.88
ns
TPPos2
Transmitter Output Pulse Position for Bit2
3.16
3 . 36
3.56
ns
TPPos3
Transmitter Output Pulse Position for Bit3
4.51
5 . 04
5.24
ns
TPPos4
Transmitter Output Pulse Position for Bit4
6.52
6 . 72
6.92
ns
TPPos5
Transmitter Output Pulse Position for Bit5
8.20
8 . 40
8.60
ns
TPPos6
Transmitter Output Pulse Position for Bit6
9.88
10 .
08
10.28
ns
TCIP
TxCLK IN Period
(Figure 6 )
11.76
T
50
ns
TCIH
TxCLK IN High Time (
Figure 6)
0.35T
0.5T
0.65T
ns
TCIL
TxCLK IN Low Time (
Figure 6)
0.35T
0.5T
0.65T
ns
TSTC
TxIN Setup to TxCLK IN (
Figure 6)
f = 85 MHz
2.5
ns
THTC
TxIN Hold to TxCLK IN (
Figure 6)
0
ns
TCCD
TxCLK IN to TxCLK OUT Delay
@
25C,V
CC
=3.3V (
Figure 8)
3.8
6.3
ns
TPLLS
Transmitter Phase Lock Loop Set (
Figure 10)
10
ms
TPDD
Transmitter Powerdown Delay (
Figure 13)
100
ns
TJIT
TxCLK IN Cycle-toCycle Jitter (Figure TBD)
2
ns
DS90CR287/DS90CR288A
www.national.com
4
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Units
CLHT
CMOS/TTL Low-to-High Transition Time (
Figure 3)
2
3.5
ns
CHLT
CMOS/TTL High-to-Low Transition Time (
Figure 3)
1.8
3.5
ns
RSPos0
Receiver Input Strobe Position for Bit 0 (
Figure 16)
f = 85 MHz
0.49
0.84
1.19
ns
RSPos1
Receiver Input Strobe Position for Bit 1
2.17
2.52
2.87
ns
RSPos2
Receiver Input Strobe Position for Bit 2
3.85
4.20
4.55
ns
RSPos3
Receiver Input Strobe Position for Bit 3
5.53
5.88
6.23
ns
RSPos4
Receiver Input Strobe Position for Bit 4
7.21
7.56
7.91
ns
RSPos5
Receiver Input Strobe Position for Bit 5
8.89
9.24
9.59
ns
RSPos6
Receiver Input Strobe Position for Bit 6
10.57
10.92
11.27
ns
RSKM
RxIN Skew Margin (Note 5) (
Figure 17)
f = 85 MHz
290
ps
RCOP
RxCLK OUT Period (
Figure 7)
11.76
T
50
ns
RCOH
RxCLK OUT High Time (
Figure 7)
f = 85 MHz
4
5
6.5
ns
RCOL
RxCLK OUT Low Time (
Figure 7)
3.5
5
6
ns
RSRC
RxOUT Setup to RxCLK OUT (
Figure 7)
3.5
ns
RHRC
RxOUT Hold to RxCLK OUT (
Figure 7)
3.5
ns
RCCD
RxCLK IN to RxCLK OUT Delay
@
25C, V
CC
= 3.3V (Note 6)(
Figure 9)
5.5
7
9.5
ns
RPLLS
Receiver Phase Lock Loop Set (
Figure 11)
10
ms
RPDD
Receiver Powerdown Delay (
Figure 14)
1
s
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window-RSPOS). This margin allows LVDS interconnect skew, inter-symbol interference
(both dependent on type/length of cable), and source clock (less than 150 ps).
Note 6: Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency
for the 217/287 transmitter and 218/288A receiver is: (T + TCCD) + (2
*
T + RCCD), where T = Clock period.
AC Timing Diagrams
DS101087-2
FIGURE 1. "Worst Case" Test Pattern
DS101087-3
DS101087-4
FIGURE 2. DS90CR287 (Transmitter) LVDS Output Load and Transition Times
DS90CR287/DS90CR288A
www.national.com
5
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