DS92LV1260
Six Channel 10 Bit BLVDS Deserializer
General Description
The DS92LV1260 integrates six deserializer devices into a
single chip. The chip uses a 0.25u CMOS process technol-
ogy. The DS92LV1260 can simultaneously deserialize up to
six data streams that have been serialized by the National
Semiconductor DS92LV1021 or DS92LV1023 Bus LVDS se-
rializers. The device also includes a seventh serial input
channel that serves as a redundant input.
Each deserializer block in the DS92LV1260 operates inde-
pendently with its own clock recovery circuitry and lock-
detect signaling.
The DS92LV1260 uses a single +3.3V power supply with a
typical power dissipation of 1.2W at 3.3V with a PRBS-15
pattern. Refer to the Connection Diagrams for packaging
information.
Features
n
Deserializes one to six BusLVDS input serial data
streams with embedded clocks
n
Seven selectable serial inputs to support n+1
redundancy of deserialized streams
n
Seventh channel has single pin monitor output that
reflects input from seventh channel input
n
Parallel clock rate up to 40MHz
n
On chip filtering for PLL
n
Absolute maximum worst case power dissipation =
1.9W at 3.6V
n
High impedance inputs upon power off (V
cc
= 0V)
n
Single power supply at +3.3V
n
196-pin LBGA package (Low-profile Ball Grid Array)
package
n
Industrial temperature range operation: -40C to +85C
Block Diagram
Application
20000202
August 2003
DS92L
V1260
Six
Channel
10
Bit
BL
VDS
Deserializer
2003 National Semiconductor Corporation
DS200002
www.national.com
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
cc
)
-0.3 to 4V
Bus LVDS Input Voltage
(Rin +/-)
-0.3V to 3.9V
Maximum Package
Power Dissipation
@
25C
3.7W
Package Thermal Resistance
JA
196 LBGA:
34C/W
JC
196 LBGA:
8C/W
Storage Temp. Range
-65C to +150C
Junction Termperature
+150C
Lead Temperature
(Soldering 10 Sec)
+225C
ESD Rating:
Human Body Model
>
3KV
Machine Model
>
750V
Reliability Information
Transistor Count
35,682
Recommended Operating
Conditions
Supply Voltage (V
CC
)
3.0V to 3.6V
Operating Free Air
Temperature (T
A
)
-40C to +85C
Operating Frequency
16-40 MHz
Electrical Characteristics
Basic functionality and specifications per deserializer channel will be similar to National Semiconductor's DS92LV1212A.
Over recommended operating supply and termperature ranges unless otherwise specified.(Note 2)
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
LVCMOS/LVTTL DC Specifications:
V
IH
High Level Input Voltage
REN,
REFCLK,
PWRDWN,
SEL (0:2),
R
OUT
2.0
V
CC
V
V
IL
Low Level Input Voltage
GND
0.8
V
V
CL
Input Clamp Voltage
-0.87
-1.5
V
I
IN
Input Current
V
in
= 0 or 3.6V
-10
+10
uA
V
OH
High Level Output Voltage
I
OH
= -6mA
R
out
,
RCLK,
LOCK
2
3
V
CC
V
V
OL
Low Level Output Voltage
I
OL
= 6mA
GND
0.18
0.4
V
I
OS
Output short Circuit Current
V
out
= 0V,(Note
4)
-15
-46
-85
mA
I
OZ
TRI-STATE Output Current
PWRDWN
or REN = 0.8V,
V
out
= 0V or
V
CC
-10
+/-0.2
+10
uA
Bus LVDS DC specifications
V
TH
Differential Threshold High
Voltage
VCM = 1.1V
(V
RI+
-V
RI-
)
+3
+50
mV
V
TL
Differential Threshold Low
Voltage
RI+, RI-
-50
-2
mV
I
IN
Input Current
V
in
= +2.4V,
V
cc
= 3.6 or 0V
-10
+/- 1
+10
uA
V
in
=0V,
V
cc
= 3.6 or 0V
-10
+/- 1
+10
uA
Supply Current
I
CCR
Worst Case Supply Current
3.6V, 40 MHz,
Checker Board
Pattern,
CL=15pF
460
530
mA
I
CCXR
Supply Current when
Powered Down
PWRDN= 0.8V
REN = 0.8V
0.36
1
mA
Timing Requirements for REFCLK
t
RFCP
REFCLK Period
25
62.5
ns
t
RFDC
REFCLK Duty Cycle
40
50
60
%
t
RFCP
/t
TCP
Ratio of REFCLK to TCLK
0.95
1.05
DS92L
V1260
www.national.com
2
Electrical Characteristics
(Continued)
Basic functionality and specifications per deserializer channel will be similar to National Semiconductor's DS92LV1212A.
Over recommended operating supply and termperature ranges unless otherwise specified.(Note 2)
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
t
RFTT
REFCLK Transition Time
8
ns
Deserializer Switching Characteristics
t
RCP
RCLK Period
RCLK
25
62.5
ns
t
RDC
RCLK Duty Cycle
43
50
55
%
t
CHTST
Period of Bus LVDS signal
when CHTST is selected by
MUX
(Note 7)
CHTST
25
ns
t
CLH
CMOS/TTL Low-to-High
Transition Time
1.7
6
ns
t
CHL
CMOS/TTL High-to-Low
Transition Time
1.6
6
ns
t
ROS
Rout Data Valid before
RCLK
Figure 2
0.4*t
RCP
ns
t
ROH
Rout Data Valid after RCLK
Figure 2
Rout,
LOCK,
RCLK
-0.4*t
RCP
ns
t
HZR
High to TRI-STATE Delay
10
ns
t
LZR
Low to TRI-STATE Delay
10
ns
t
ZHR
TRI-STATE to High Delay
12
ns
t
ZLR
TRI-STATE to Low Delay
12
ns
t
DD
Deserializer Delay
Figure 1
RCLK
1.75*t
RCP
+5
1.75*t
RCP
+7
1.75*t
RCP
+10
ns
Room Temp
3.3V
40MHz
1.75*t
RCP
+6
1.75*t
RCP
+7
1.75*t
RCP
+9
ns
t
DSR1
Deserializer PLL LOCK Time
from PWRDN (with
SYNCPAT)
Figure 3
(Note 5)
40MHz
3
us
20MHz
10
us
t
DSR2
Deserializer PLL Lock Time
from SYNCPAT
Figure 4
(Note 5)
40MHz
2
us
20MHz
5
us
t
RNM
Deserializer Noise Margin
(Note 6)
40MHz
450
920
ps
20MHz
1200
1960
ps
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation.
Note 2: Typical values are given for Vcc = 3.3V and TA =25C
Note 3: Current into the device pins is defined as positive. Current out of device pins is defined as negative. Voltage are referenced to ground except VTH and VTL
which are differential voltages.
Note 4: Only one output should be shorted at a time. Do not exceed maximum package power dissipation capacity.
Note 5: For the purpose of specifying deserializer PLL performance t
DSR1
and t
DSR2
are specified with the REFCLK running and stable, and specific conditions of
the incoming data stream (SYNCPATs). t
DSR1
is the time required for the deserializer to indicate lock upon power-up or when leaving the power-down mode. t
DSR2
is the time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and RI-) conditions change from not receiving data to receiving
synchronization patterns (SYNCPATs). The time to lock to random data is dependent upon the incoming data.
Note 6: t
RNM
is a measure of how much phase noise (jitter)the deserializer can tolerate in the incoming data stream before bit errors occur. The Deserializer Noise
Margin is Guaranteed By Design (GBD) using statistical analysis.
Note 7: Because the Bus LVDS serial data stream is not decoded, the maximum frequency of the CHTST output driver could be exceeded if the data stream were
switched to CHTST. The maximum frequency of the BUS LVDS input should not exceed the parallel clock rate.
DS92L
V1260
www.national.com
3
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