FPD33684A/ FPD33684B
Low Power, Low EMI, TFT-LCD Column Driver with
RSDS
TM
Inputs, 64 Grayshades, and 384 Outputs for
XGA/SXGA Applications
General Description
The FPD33684 Column Driver is a direct drive, 64 gray level,
384 output, TFT-LCD column driver with an RSDS
TM
data
interface. It provides the capability to display 262,144 colors
(18-bit color) with a large dynamic output range for twisted
nematic applications. When used in a bank with other
FPD33684 column drivers, the FPD33684 can support both
XGA (8 drivers) or SXGA (10 drivers) applications. Output
voltages are programmably gamma corrected to provide a
direct mapping between digital video and LCD panel bright-
ness.
An RSDS
TM
(Reduced Swing Differential Signaling) interface
is used between the timing controller and the column driver
to minimize EMI and reduce power.
The FPD33684 offers a low power, low EMI column driver
solution with direct-drive dynamic range and dot-inversion
addressing.
Features
n
RSDS
TM
(Reduced Swing Differential Signaling) data
bus for low power, reduced EMI and small PCB foot
print
n
Up to 85MHz clock
n
Supports both XGA and SXGA timing
n
Supports notebook and monitor applications
n
Smart Charge Conservation for low power consumption
n
64 Gray levels per color (18-bit color)
n
Supports both Dot and N-Line inversion
n
Externally programmable gamma characteristic
n
Very low offsets for artifact-free images
n
High voltage outputs for high contrast in a large range of
display panel applications
n
Optional, high current, repair line buffers
n
Available in 2 common gamma reference curves
Ordering Information
Part Number
Gamma Curve
Custom TCP #
Package Suffix
FPD33684
A or B
XX(Note 1)
CT
Note 1: Custom TCP # is assigned by National Semiconductor for each custom TCP design
System Diagram
DS200113-1
May 2002
FPD33684
Low
Power
,
Low
EMI,
TFT
-LCD
Column
Driver
with
RSDS
Inputs,
64
Grayshades,
and
384
Outputs
for
XGA/SXGA
Applications
2002 National Semiconductor Corporation
DS200113
www.national.com
Absolute Maximum Ratings
(Note 2)
Analog Supply, (V
DD2
) (Note 3)
-0.3V to +11.5V
Logic Supply, (V
DD1
) (Note 3)
-0.3V to +5.0V
High Bias Supply, (V
HBIAS
) (Note 3)
-0.3V to +13.0V
Low-Polarity RDAC Reference
Voltages, (V
GMA6
to V
GMA10
)
(Note 3)
-0.3V to 0.5V
DD2
High-Polarity RDAC Reference
Voltages, (V
GMA1
to V
GMA5
)
(Note 3)
0.5V
DD2
- 1.0V to
V
DD2
+ 0.3V
RDAC Current (All Gamma Voltage
Taps), (I
GMA
to I
GMA10
)
-2.5mA to 2.5mA
Input Voltage (Digital Logic), (V
IN
)
(Note 3)
-0.3V to V
DD1
+ 0.3V
Output Voltage, (V
OUT
) (Note 3)
-0.3V to V
DD2
+ 0.3V
Output Current (Analog), (I
OUT
)
-7mA to +7mA
Storage Temperature Range, (T
S
)
-55C to +125C
Note 2: "Absolute Maximum Ratings" are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply that
the devices should be operated at these limits. The table of "Electrical
Characteristics" specifies conditions of device operation.
Note 3: Absolute voltages referenced to V
SS1
= V
SS2
= 0.0V.
Recommended Operating
Conditions
Min
Typ
Max
Units
Logic Supply Voltage
(V
DD1
)
2.7
3.3
3.6
V
Supply Voltage (V
DD2
)
7.5
10.5
V
Supply Voltage (V
HBIAS
)
V
DD2
V
DD2
+1.5
V
Operating Temperature
(T
A
)
-10
+25
+70
C
DC Electrical Characteristics
Digital Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
IH
Logic Input High Voltage
0.7
V
DD1
V
V
IL
Logic Input Low Voltage
0.3
V
DD1
V
V
OH
Logic Output High Voltage
I
OH
= -0.5mA
V
DD1
-
0.5
V
V
OL
Logic Output Low Voltage
I
OL
= 0.5mA
0.5
V
I
DD1
Logic Current
(Note 4)
3.0
8.0
mA
I
IH
Input Leakage
V
DD1
= 3.6V, V
IN
= 3.6V
-1
1
A
I
IL
Input Leakage
V
DD1
= 3.6V, V
IN
= 0V
-1
1
A
C
IN
Input Capacitance
All logic pins
2
pF
Note 4: CLK frequency = 32.5 MHz, V
DD1
= 3.3V, V
SS1
= V
SS2
= 0.0V, charge share time = 1.5s, line time = 22s.
RSDS Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIH
RSDS
RSDS
TM
High Input Voltage
VCM
RSDS
= 1.2V (Note 5) see
Figure 1
100
200
mV
VIL
RSDS
RSDS
TM
Low Input Voltage
VCM
RSDS
= 1.2V (Note 5) see
Figure 1
-200
-100
mV
VCM
RSDS
RSDS
TM
Common Mode Input
Voltage Range
VIH
RSDS
= +100mV, VIL
RSDS
=
-100mV (Note 6) see Figure 1
V
SS1
+
0.1
V
DD1
-
1.3
V
IDL
RSDS
TM
Input Leakage Current
DxxP, DxxN, CLKP, CLKN
-10
10
A
Note 5: VCM
RSDS
= (VCLKP + VCLKN)/2 or (VDxxP + VDxxN)/2.
Note 6: Positive means that DxxP (or CLKP) is higher than RSDS ground DxxN (or CLKN). Negative means that DxxP (or CLKP) is lower than RSDS ground DxxN
(or CLKN).
FPD33684
www.national.com
2
RSDS Characteristics
(Continued)
Analog Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
I
DD2
Supply Current Consumption
(Note 7)
3.0
8.0
mA
I
HBIAS
Current Consumption through
HBIAS pin
1.25
mA
PD
Power Dissipation
(Note 7)
45
mW
V
GMA1
Upper RDAC High Side Input
(Note 8)
V
DD2
/2
+ 0.2
V
DD2
-
0.2
V
V
GMA5
Upper RDAC Low Side Input
(Note 8)
V
DD2
/2
+ 0.2
V
DD2
-
0.2
V
V
GMA6
Lower RDAC High Side Input
(Note 8)
0.2
V
DD2
/2
- 0.2
V
V
GMA10
Lower RDAC Low Side Input
(Note 8)
0.2
V
DD2
/2
- 0.2
V
V
CS
Charge Share Voltage
The
Greater
of V
DD1
or
V
GMA6
V
GMA5
V
C
LOAD
Output Capacitive Load
30
150
pF
V
OUT
Output Voltage Range
V
SS2
+
0.2
V
DD2
-
0.2
V
R
DAC
RDAC References (V
GMA1
to
V
GMA5
and V
GMA6
to V
GMA10
)
each
12.0
15.0
18.0
k
V
pperr
Output Peak to Peak Error (gray
levels 0 through 58)
V
GMA1
= V
DD2
- 0.2V
V
GMA10
= V
SS2
+ 0.2V
(Note 9)
3
12
mV
Output Peak to Peak Error (gray
levels 59 through 63)
5
25
mV
V
parterr
Output Part to Part Error
(Note 10)
5
mV
I
OUT RP
Repair Buffer Output Current
(Note 11)
2
3
mA
Note 7: V
DD2
= 10.5V, V
HBIAS
= 10.5V, V
DD1
= 3.3V, DCLK = 65 MHz, R
LOAD
= 5 k
, C
LOAD
= 50 pF, charge share time = 1.5 s, all other swinging between
V
GMA1
(= 8.0V) and V
GMA10
(= 0.5V) with a line time = 22 s.
Note 8: The following relationship must be maintained between the reference voltages: V
DD2
>
V
GMA1
>
V
GMA2
>
V
GMA3
>
V
GMA4
>
V
GMA5
>
V
GMA6
>
V
GMA7
>
V
GMA8
>
V
GMA9
>
V
GMA10
>
V
SS2
Note 9: V
pperr
is defined as the error in peak-to-peak output voltage for each gray level when the output swings from the gray level high value (VHxx) to the gray
level low value (VLxx). This parameter applies to every output on the die. The typical value represents one standard deviation from ideal based on final test data.
Note 10: V
parterr
is meant to guarantee the part to part output variation. The average of all outputs at gray level 32 is compared to a nominal gray level 32 value.
Note 11: Current into device pins is defined as positive. Current out of device pins is defined as negative. |V
OUT
- V
IN
|
>
500mV.
DS200113-2
FIGURE 1. RSDS
TM
Signal Definition
FPD33684
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3
AC Electrical Characteristics
Digital AC Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
PW
CLK
Clock Period
11.7
ns
PW
CLK(L)
Low Clock Pulse Width
5
ns
PW
CLK(H)
High Clock Pulse Width
5
ns
t
setup1
RSDS Data Setup Time
2
ns
t
hold1
RSDS Data Hold Time
0
ns
t
setup2
ENIOx Setup Time
2
ns
t
hold2
ENIOx Hold Time
4
ns
t
PLH1
Start Pulse Fall Delay
C
LINE
= 15 pF
8
ns
PW
DIO
ENIOx Pulse Width
1
2
T
CLK
PW
CLK1
LOAD Pulse Width
5 T
CLK
5s
t
LDT
Last Clock to LOAD Delay
5
T
CLK
t
DENSU
LOAD to First ENIO Setup
2
T
CLK
tPOLCLK1
POLCLK1 Time
14
ns
Analog AC Characteristics
Supplies: V
SS1
= V
SS2
= 0.0V, V
DD1
= 3.3V, V
DD2
= +9.5V, V
HBIAS
= 11.0V.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
settle 90%
Output Settling Time to 90% of
Final Value
Figure 2 (Note 12)
6
s
t
6-bit accy
Output Settling Time to 6-bit
accuracy
Figure 2 (Note 12)
10
s
t
RP 90%
Repair Line Output Settling Time
to 90% of Final Value
C
LOAD
= 150 pF,
(Note 12)
6
s
t
RP 6-bit accy
Repair Line Output Settling Time
to 6-bit accuracy
C
LOAD
= 150 pF,
(Note 12)
10
s
Note 12: Charge Share Time = 800ns, V
GMA1
= 10.3V, V
GMA10
= 0.2V, V
GMA5
= 5.45V, V
GMA6
= 5.05V.
DS200113-11
FIGURE 2. Test Circuit for Output Settling Time Measurements
FPD33684
www.national.com
4
Timing Diagrams
DS2001
13-3
FPD33684
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5
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