Geode GXLV Processor Series Low Power Integrated x86 Solutions

www.national.com

March 2001

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

w
P

wer

I
nte

rat
e

x86

Sol

t
i
ons

GeodeTM GXLV Processor Series
Low Power Integrated x86 Solutions

General Description

The National Semiconductor

GeodeTM GXLV processor

series is a new line of integrated processors specifically
designed to power information appliances for entertain-
ment, education, and business. Serving the needs of con-
sumers and business professionals alike, it is the perfect
solution for information appliance applications such as
thin clients, interactive set top boxes, and personal inter-
net access devices.

The GXLV processor series is divided into three main cat-
egories as defined by the core operating voltage. Avail-
able with core voltages of 2.2V, 2.5V, and 2.9V, it offers
extremely low typical power consumption (1.0W to 2.5W)

leading to longer battery life and enabling small form-fac-
tor, fanless designs. Each core voltage is offered in fre-
quencies that are enabled by specific system clock and
multiplier settings. This allows the user to select the
device(s) that best fit their power and performance
requirements. This flexibility makes the GXLV processor
series ideally suited for applications where power con-
sumption and performance (speed) are equally important.

Typical power consumption is defined as an average,
measured running Microsoft's Windows at 80% Active Idle
(Suspend-on-Halt) with a display resolution of 800x600x8
bpp at 75 Hz.

Internal Block Diagram

Interrupt

Control

Floating Point

Unit

Clock Module

SYSCLK

Core

X-Bus

X86 Compatible Core

TLB

Integer

Unit

Instruction

Fetch

MMU

Load/Store

16 KB

Unified L1

Cache

Arbiter

PCI Host

Controller

2D Accelerator

VGA

BLT Engine

ROP Unit

(128)

FP_Error

INT/NMI

X-Bus Controller

Power

Management

Control

SUSP#

SUSPA#

Core Suspend

Core Acknowledge

X-Bus Suspend

X-Bus Acknowledge

X-Bus (32)

C-Bus (64)

Write Buffers

Read Buffers

Display Controller

Compression Buffer

Palette RAM

Timing Generator

INTR

IRQ13

REQ/GNT

Pairs

PCI Bus

SDRAM

Clocks

64-bit SDRAM

RGB

YUV

Video Companion Interface

r
a

t
c

Arbiter

SMI#

I/O

i
o

Clocks

SYSCLK

multiplied by

X-Bus Clk ÷ B

National Semiconductor is a registered trademark of National Semiconductor Corporation.
Geode and WebPAD are trademarks of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.

www.national.com

Revision 1.3

odeTM

r
o

ries

While the x86 core provides maximum compatibility with
the vast amount of internet content available, the intelli-
gent integration of several other functions, such as mem-
ory controller and graphics, offer a true system-level
multimedia solution.

The GXLV processor core is a proven x86 design that
offers competitive performance. It contains integer and
floating point execution units based on sixth-generation
technology. The integer core contains a single, five-stage
execution pipeline and offers advanced features such as
operand forwarding, branch target buffers, and extensive
write buffering. Accesses to the 16 KB write-back L1
cache are dynamically reordered to eliminate pipeline
stalls when fetching operands.

In addition to the advanced CPU features, the GXLV pro-
cessor integrates a host of functions typically imple-
mented with external components. A full function graphics
accelerator contains a Video Graphics Array (VGA) con-
troller, bitBLT engine, and a Raster Operations (ROP) unit
for complete Graphical User Interface (GUI) acceleration
under most operating systems. A display controller con-
tains additional video buffering to enable >30 fps MPEG1
playback and video overlay when used with a National
Semiconductor I/O Companion chip such as the CS5530.
Graphics and system memory accesses are supported by
a tightly coupled SDRAM controller which eliminates the
need for an external L2 cache. A PCI host controller sup-
ports up to three bus masters for additional connectivity
and multimedia capabilities.

The GXLV processor also incorporates Virtual System
Architecture

(VSATM)

technology.

VSA

technology

enables the XpressGRAPHICS and XpressAUDIO sub-
systems. Software handlers are available that provide full
compatibility for industry standard VGA and 16-bit audio
functions that are transparent at the operating system
level.

The GXLV processor is designed to be used with the
CS5530 I/O Companion, also supplied by National Semi-
conductor. Together they provide a scalable, flexible, low-
power, system-level solution well suited for a wide array of
information appliances ranging from hand-held personal
information access devices to digital set top boxes and
thin clients.

Features

General Features

Packaging:
-- 352-Terminal Ball Grid Array (BGA) or
-- 320-Pin Staggered Pin Grid Array (SPGA)

0.25-micron four layer metal CMOS process

Split rail design:
-- Available 2.2V, 2.5V, or 2.9V core
-- 3.3V I/O interface (5V tolerant)

Low typical power consumption:
-- 1.0W @ 2.2V/166 MHz
-- 2.5W @ 2.9V/266 MHz

Note:

Typical power consumption is defined as an aver-
age, measured running Windows at 80% Active
Idle (Suspend-on-Halt) with a display resolution of
800x600x8 bpp @ 75 Hz.

Speeds offered up to 266 MHz

Unified Memory Architecture:
-- Frame buffer and video memory reside in main

memory

-- Minimizes Printed Circuit Board (PCB) area require-

ments

-- Reduces system cost

Compatible with multiple Geode I/O companion
devices provided by National Semiconductor

32-Bit x86 Processor

Supports Intel's MMX instruction set extension for the
acceleration of multimedia applications

16 KB unified L1 cache

Five-stage pipelined integer unit

Integrated Floating Point Unit (FPU)

Memory Management Unit (MMU) adheres to standard
paging mechanisms and optimizes code fetch perfor-
mance:
-- Load-store reordering gives priority to memory

reads

-- Memory-read bypassing eliminates unnecessary or

redundant memory reads

Re-entrant System Management Mode (SMM)
enhanced for VSA technology

Fully Static Design

Flexible Power Management

Supports a wide variety of standards:
-- APM for Legacy power management
-- ACPI for Windows power management

Direct support for all standard processor (C0-C4)

states

-- OnNOW specification compliant

Supports a wide variety of hardware and software
controlled modes:
-- Fully Active
-- Active Idle (core stopped, display active)
-- Standby (core and all integrated functions halted)
-- Sleep (core and integrated functions halted and all

external clocks stopped)

-- Suspend Modulation (automatic throttling of CPU

core)
Programmable duty cycle for optimal perfor-

mance/thermal balancing

-- Several dedicated and programmable wake-up

events (via Geode I/O companion chip)

Revision 1.3

www.national.com

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

PCI Host Controller

Several arbitration schemes supported

Supports up to three PCI bus masters

Synchronous to CPU core

Allows external PCI master accesses to main memory
concurrent with CPU accesses to L1 cache

Virtual Systems Architecture Technology

Innovative architecture allowing OS independent (soft-
ware) virtualization of hardware functions

Provides XpressGRAPHICS subsystem:
-- High performance legacy VGA core compatibility

Note:

Uses 2D Graphics Accelerator.

Provides 16-bit XpressAUDIO subsystem:
-- 16-bit stereo FM synthesis
-- OPL3 emulation
-- Supports MPU-401 MIDI interface
-- Hardware assist provided via Geode I/O companion

chip

Additional hardware functions can be supported as
needed

2D Graphics Accelerator

Accelerates BitBLTs, line draw, text

Bresenham vector engine

Supports all 256 ROPs

Supports transparent BLTs and page flipping for
Microsoft's DirectDraw

Runs at core clock frequency

Full VGA and VESA mode support

Special "driver level" instructions utilize internal
scratchpad for enhanced performance

Display Controller

Display Compression Technology (DCT) architecture
greatly reduces memory bandwidth consumption of
display refresh

Supports a separate video buffer and data path to
enable video acceleration in Geode I/O companion
devices

Internal palette RAM for gamma correction

Direct interface to Geode I/O companion devices for
CRT and TFT flat panel support eliminates the need for
an external RAMDAC

Hardware cursor

Supports up to 1280x1024x8 bpp and
1024x768x16 bpp

XpressRAM Subsystem

SDRAM interface tightly coupled to CPU core and
graphics subsystem for maximum efficiency

64-Bit wide memory bus

Support for:
-- Two 168-pin unbuffered DIMMs
-- Up to 16 simultaneously open banks
-- 16-byte reads (burst length of two)
-- Up to 256 MB total memory supported

Diverse Operating System Support

Microsoft's Windows 2000, 9X, NT, and CE

Sun Microsystems' Java

WindRiver Systems' VxWorks

QNX Software Systems' QNX

Linux

www.national.com

Revision 1.3

Table of Contents

odeTM

r
o

ries

1.0

Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.1

INTEGER UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.2

FLOATING POINT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3

WRITE-BACK CACHE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.4

MEMORY MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.5

INTERNAL BUS INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.6

INTEGRATED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.6.1

Graphics Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.6.2

Display Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.6.3

XpressRAM Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.6.4

PCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.7

GEODE GXLV/CS5530 SYSTEM DESIGNS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.7.1

Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.0

Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1

PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.2.1

System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.2.2

PCI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.2.3

Memory Controller Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.2.4

Video Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.2.5

Power, Ground, and No Connect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.2.6

Internal Test and Measurement Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.0

Processor Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.1

CORE PROCESSOR INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.2

INSTRUCTION SET OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.2.1

Lock Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.3

REGISTER SETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.3.1

Application Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.3.1.1

General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.3.1.2

Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.3.1.3

Instruction Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.3.1.4

EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.3.2

System Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.3.2.1

Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.3.2.2

Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.3.2.3

Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.3.2.4

TLB Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.3.2.5

Cache Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.3.3

Model Specific Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.3.4

Time Stamp Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.4

ADDRESS SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.4.1

I/O Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.4.2

Memory Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Revision 1.3

www.national.com

Table of Contents (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

3.5

OFFSET, SEGMENT, AND PAGING MECHANISMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.5.1

Offset Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.5.2

Segment Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.5.2.1

Real Mode Segment Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.5.2.2

Virtual 8086 Mode Segment Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.5.2.3

Segment Mechanism in Protected Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.5.2.4

Segment Selectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.5.3

Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.5.3.1

Global and Local Descriptor Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.5.3.2

Segment Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.5.3.3

Task, Gate, Interrupt, and Application and System Descriptors . . . . . . . . . . . . . . 71

3.5.4

Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.6

INTERRUPTS AND EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.6.1

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.6.2

Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.6.3

Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.6.3.1

Interrupt Vector Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.6.3.2

Interrupt Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.6.4

Interrupt and Exception Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

3.6.5

Exceptions in Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.6.6

Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.7

SYSTEM MANAGEMENT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.7.1

SMM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.7.2

SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.7.3

SMM Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.7.4

SMM Memory Space Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.7.5

SMM Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

3.7.6

SMM Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.7.7

SMI Generation for Virtual VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.7.8

SMM Service Routine Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.7.8.1

SMI Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.7.8.2

CPU States Related to SMM and Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . 90

3.8

HALT AND SHUTDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

3.9

PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

3.9.1

Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

3.9.2

I/O Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

3.9.3

Privilege Level Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

3.9.3.1

Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

3.9.4

Initialization and Transition to Protected Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

3.10

VIRTUAL 8086 MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

3.10.1

Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

3.10.2

Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

3.10.3

Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

3.10.4

Entering and Leaving Virtual 8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

3.11

FLOATING POINT UNIT OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.11.1

FPU Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.11.2

FPU Tag Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.11.3

FPU Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.11.4

FPU Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

www.national.com

Revision 1.3

Table of Contents (

Continued

)

odeTM

r
o

ries

4.0

Integrated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

4.1

INTEGRATED FUNCTIONS PROGRAMMING INTERFACE . . . . . . . . . . . . . . . . . . . . . . . 97

4.1.1

Graphics Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4.1.2

Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.1.3

Graphics Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.1.4

Scratchpad RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4.1.4.1

Initialization of Scratchpad RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4.1.4.2

Scratchpad RAM Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4.1.4.3

BLT Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4.1.5

Display Driver Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

4.1.6

CPU_READ/CPU_WRITE Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

4.2

INTERNAL BUS INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

4.2.1

FPU Error Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

4.2.2

A20M Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

4.2.3

SMI Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

4.2.4

640 KB to 1 MB Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

4.2.5

Internal Bus Interface Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

4.3

MEMORY CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

4.3.1

Memory Array Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4.3.2

Memory Organizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

4.3.3

SDRAM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

4.3.3.1

SDRAM Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

4.3.4

Memory Controller Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

4.3.5

Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

4.3.5.1

High Order Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

4.3.5.2

Auto Low Order Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

4.3.5.3

Physical Address to DRAM Address Conversion . . . . . . . . . . . . . . . . . . . . . . . . 117

4.3.6

Memory Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

4.3.7

SDRAM Interface Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

4.4

GRAPHICS PIPELINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

4.4.1

BitBLT/Vector Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

4.4.2

Master/Slave Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

4.4.3

Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

4.4.3.1

Monochrome Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

4.4.3.2

Dither Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

4.4.3.3

Color Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

4.4.4

Source Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

4.4.5

Raster Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

4.4.6

Graphics Pipeline Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Revision 1.3

www.national.com

Table of Contents (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

4.5

DISPLAY CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

4.5.1

Display FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

4.5.2

Compression Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

4.5.3

Hardware Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

4.5.4

Display Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

4.5.5

Dither and Frame Rate Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

4.5.6

Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

4.5.7

Graphics Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

4.5.7.1

DC Memory Organization Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

4.5.7.2

Frame Buffer and Compression Buffer Organization . . . . . . . . . . . . . . . . . . . . . . 140

4.5.7.3

VGA Display Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

4.5.8

Display Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

4.5.8.1

Configuration and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

4.5.9

Memory Organization Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

4.5.10

Timing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

4.5.11

Cursor Position and Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

4.5.12

Palette Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

4.5.13

FIFO Diagnostic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

4.5.14

CS5530 Display Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

4.5.14.1 CS5530 Video Port Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

4.6

VIRTUAL VGA SUBSYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

4.6.1

Traditional VGA Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

4.6.1.1

VGA Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

4.6.1.2

VGA Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

4.6.1.3

Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

4.6.1.4

Video Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

4.6.1.5

VGA Video BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

4.6.2

Virtual VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

4.6.2.1

Datapath Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

4.6.2.2

GXLV VGA Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

4.6.2.3

SMI Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

4.6.2.4

VGA Range Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

4.6.2.5

VGA Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

4.6.2.6

VGA Write/Read Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

4.6.2.7

VGA Address Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

4.6.2.8

VGA Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

4.6.3

VGA Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

4.6.4

Virtual VGA Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

4.7

PCI CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

4.7.1

X-Bus PCI Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

4.7.2

X-Bus PCI Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

4.7.3

PCI Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

4.7.4

Generating Configuration Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

4.7.5

Generating Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

4.7.6

PCI Configuration Space Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

4.7.7

PCI Configuration Space Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

4.7.8

PCI Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

4.7.8.1

PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

4.7.8.2

PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

4.7.8.3

PCI Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

4.7.8.4

PCI Halt Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

www.national.com

Revision 1.3

Table of Contents (

Continued

)

odeTM

r
o

ries

5.0

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

5.1

POWER MANAGEMENT FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

5.1.1

System Management Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

5.1.2

Suspend-on-Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

5.1.3

CPU Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

5.1.3.1

Suspend Modulation for Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . 177

5.1.3.2

Suspend Modulation for Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

5.1.4

3 Volt Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

5.1.5

GXLV Processor Serial Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

5.1.6

Advanced Power Management (APM) Support . . . . . . . . . . . . . . . . . . . . . . . . . . 177

5.2

SUSPEND MODES AND BUS CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

5.2.1

Timing Diagram for Suspend-on-Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

5.2.2

Initiating Suspend with SUSP# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

5.2.3

Stopping the Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

5.2.4

Serial Packet Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

5.3

POWER MANAGEMENT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

6.0

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

6.1

PART NUMBERS/PERFORMANCE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 184

6.2

ELECTRICAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

6.2.1

Power/Ground Connections and Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

6.2.1.1

Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

6.2.2

NC-Designated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

6.2.3

Pull-Up and Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

6.2.4

Unused Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

6.3

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

6.4

OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

6.5

DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

6.5.1

Input/Output DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

6.5.2

DC Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

6.5.2.1

Definition of CPU Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

6.5.2.2

Definition and Measurement Techniques of CPU Current Parameters . . . . . . . . 190

6.5.2.3

Definition of System Conditions for Measuring "On" Parameters . . . . . . . . . . . . 191

6.5.2.4

DC Current Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

6.6

I/O CURRENT DE-RATING CURVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

6.6.1

Display Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

6.6.2

Memory Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

6.6.3

I/O Current De-rating Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

6.7

AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Revision 1.3

www.national.com

Table of Contents (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

7.0

Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

7.1

GENERAL INSTRUCTION SET FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

7.1.1

Prefix (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

7.1.2

Opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

7.1.2.1

w Field (Operand Size) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

7.1.2.2

d Field (Operand Direction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

7.1.2.3

s Field (Immediate Data Field Size) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

7.1.2.4

eee Field (MOV-Instruction Register Selection) . . . . . . . . . . . . . . . . . . . . . . . . . . 209

7.1.3

mod and r/m Byte (Memory Addressing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

7.1.4

reg Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

7.1.4.1

sreg2 Field (ES, CS, SS, DS Register Selection) . . . . . . . . . . . . . . . . . . . . . . . . 210

7.1.4.2

sreg3 Field (FS and GS Segment Register Selection) . . . . . . . . . . . . . . . . . . . . 210

7.1.5

s-i-b Byte (Scale, Indexing, Base) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

7.1.5.1

ss Field (Scale Selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

7.1.5.2

index Field (Index Selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

7.1.5.3

Base Field (s-i-b Present) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

7.2

CPUID INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

7.2.1

Standard CPUID Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

7.2.1.1

CPUID Instruction with EAX = 0000 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

7.2.1.2

CPUID Instruction with EAX = 00000001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

7.2.1.3

CPUID Instruction with EAX = 00000002h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

7.2.2

Extended CPUID Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

7.2.2.1

CPUID Instruction with EAX = 80000000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

7.2.2.2

CPUID Instruction with EAX = 80000001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

7.2.2.3

CPUID Instruction with EAX = 80000002h, 80000003h, 80000004h . . . . . . . . . 215

7.2.2.4

CPUID Instruction with EAX = 80000005h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

7.3

PROCESSOR CORE INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

7.3.1

Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

7.3.2

Clock Counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

7.3.3

Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

7.4

FPU INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

7.5

MMX INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

7.6

EXTENDED MMX INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

8.0

Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

8.1

THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

8.1.1

Heatsink Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

8.2

MECHANICAL PACKAGE OUTLINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Appendix A Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

A.1

Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

A.2

Data Book Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

www.national.com

Revision 1.3

odeTM

r
o

ries

1.0

Architecture Overview

The Geode GXLV processor series represents the sixth
generation of x86-compatible 32-bit processors with sixth-
generation features. The decoupled load/store unit allows
reordering of load/store traffic to achieve higher perfor-
mance. Other features include single-cycle execution, sin-
gle-cycle instruction decode, 16 KB write-back cache, and
clock rates up to 266 MHz. These features are made pos-
sible by the use of advanced-process technologies and
pipelining.

The GXLV processor has low power consumption at all
clock frequencies. Where additional power savings are
required, designers can make use of Suspend Mode, Stop
Clock capability, and System Management Mode (SMM).

The GXLV processor is divided into major functional
blocks (as shown in Figure 1-1):

· Integer Unit
· Floating Point Unit (FPU)
· Write-Back Cache Unit
· Memory Management Unit (MMU)
· Internal Bus Interface Unit
· Integrated Functions

Instructions are executed in the integer unit and in the
floating point unit. The cache unit stores the most recently
used data and instructions and provides fast access to
this information for the integer and floating point units.

Figure 1-1. Internal Block Diagram

Write-Back

Unit

FPU

Internal Bus Interface Unit

Graphics

Memory

Display

PCI

SDRAM Port

CS5530

PCI Bus

Integer

Cache Unit

Integrated

Functions

MMU

(CRT/LCD TFT)

X-Bus

Pipeline

Controller

C-Bus

Revision 1.3

www.national.com

Architecture Overview (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

1.1

INTEGER UNIT

The integer unit consists of:
· Instruction Buffer
· Instruction Fetch
· Instruction Decoder and Execution

The pipelined integer unit fetches, decodes, and executes
x86 instructions through the use of a five-stage integer
pipeline.

The instruction fetch pipeline stage generates, from the
on-chip cache, a continuous high-speed instruction
stream for use by the processor. Up to 128 bits of code
are read during a single clock cycle.

Branch prediction logic within the prefetch unit generates
a predicted target address for unconditional or conditional
branch

instructions.

When

branch

instruction

detected, the instruction fetch stage starts loading instruc-
tions at the predicted address within a single clock cycle.
Up to 48 bytes of code are queued prior to the instruction
decode stage.

The instruction decode stage evaluates the code stream
provided by the instruction fetch stage and determines the
number of bytes in each instruction and the instruction
type. Instructions are processed and decoded at a maxi-
mum rate of one instruction per clock.

The address calculation function is pipelined and contains
two stages, AC1 and AC2. If the instruction refers to a
memory operand, AC1 calculates a linear memory
address for the instruction.

The AC2 stage performs any required memory manage-
ment

functions,

cache

accesses,

and

file

accesses. If a floating point instruction is detected by
AC2, the instruction is sent to the floating point unit for
processing.

The execution stage, under control of microcode, exe-
cutes instructions using the operands provided by the
address calculation stage.

Write-back

the last stage of the integer unit, updates the

1.2

FLOATING POINT UNIT

The floating point unit (FPU) interfaces to the integer unit
and the cache unit through a 64-bit bus. The FPU is x87-
instruction-set compatible and adheres to the IEEE-754
standard. Because almost all applications that contain
FPU instructions also contain integer instructions, the
GXLV processor's FPU achieves high performance by
completing integer and FPU operations in parallel.

FPU instructions are dispatched to the pipeline within the
integer unit. The address calculation stage of the pipeline
checks

for

memory

management

exceptions

and

accesses memory operands for use by the FPU. Once the
instructions and operands have been provided to the FPU,
the FPU completes instruction execution independently of
the integer unit.

1.3

WRITE-BACK CACHE UNIT

The 16 KB write-back unified (data/instruction) cache is
configured as four-way set associative. The cache stores
up to 16 KB of code and data in 1024 cache lines.

The GXLV processor provides the ability to allocate a por-
tion of the L1 cache as a scratchpad, which is used to
accelerate the Virtual Systems Architecture technology
algorithms as well as for some graphics operations.

1.4

MEMORY MANAGEMENT UNIT

The memory management unit (MMU) translates the lin-
ear address supplied by the integer unit into a physical
address to be used by the cache unit and the internal bus
interface unit. Memory management procedures are x86-
compatible, adhering to standard paging mechanisms.

The MMU also contains a load/store unit that is responsi-
ble for scheduling cache and external memory accesses.
The

load/store

unit

incorporates

two

performance-

enhancing features:

· Load-store reordering that gives memory reads

required by the integer unit a priority over writes to
external memory.

· Memory-read bypassing that eliminates unnecessary

memory reads by using valid data from the execution
unit.

1.5

INTERNAL BUS INTERFACE UNIT

The internal bus interface unit provides a bridge from the
GXLV processor to the integrated system functions (i.e.,
memory subsystem, display controller, graphics pipeline)
and the PCI bus interface.

When external memory access is required, the physical
address is calculated by the memory management unit
and then passed to the internal bus interface unit, which
translates the cycle to an X-Bus cycle (the X-Bus is a pro-
prietary internal bus which provides a common interface
for all of the integrated functions). The X-Bus memory
cycle is arbitrated between other pending X-Bus memory
requests to the SDRAM controller before completing.

In addition, the internal bus interface unit provides config-
uration control for up to 20 different regions within system
memory with separate controls for read access, write
access, cacheability, and PCI access.

www.national.com

Revision 1.3

Architecture Overview (

Continued

)

odeTM

r
o

ries

1.6

INTEGRATED FUNCTIONS

The GXLV processor integrates the following functions tra-
ditionally implemented using external devices:

· High-performance 2D graphics accelerator

· Separate CRT and TFT control from the display

controller

· SDRAM memory controller

· PCI bridge

The processor has also been enhanced to support VSA
technology implementation.

The GXLV processor implements a Unified Memory Archi-
tecture (UMA). By using DCT (Display Compression Tech-
nology)

architecture,

the

performance

degradation

inherent in traditional UMA systems is eliminated.

1.6.1

Graphics Accelerator

The graphics accelerator is a full-featured GUI accelera-
tor. The graphics pipeline implements a bitBLT engine for
frame buffer bitBLTs and rectangular fills. Additional
instructions in the integer unit may be processed, as the
bitBLT engine assists the CPU in the bitBLT operations
that take place between system memory and the frame
buffer. This combination of hardware and software is used
by the display driver to provide very fast bidirectional
transfers between system memory and the frame buffer.
The bitBLT engine also draws randomly oriented vectors,
and scanlines for polygon fill. All of the pipeline operations
described in the following list can be applied to any bitBLT
operation.

· Pattern Memory: Render with 8x8 dither, 8x8 mono-

chrome, or 8x1 color pattern.

· Color Expansion: Expand monochrome bitmaps to

full depth 8- or 16-bit colors.

· Transparency: Suppresses drawing of background

pixels for transparent text.

· Raster Operations: Boolean operation combines

source, destination, and pattern bitmaps.

1.6.2

Display Controller

The display port is a direct interface to the Geode I/O
companion (i.e., CS5530, part number 25420-03) which
drives a TFT flat panel display, LCD panel, or a CRT dis-
play.

The display controller (video generator) retrieves image
data from the frame buffer, performs a color-look-up if
required, inserts the cursor overlay into the pixel stream,
generates display timing, and formats the pixel data for
output to a variety of display devices. The display control-
ler contains DCT architecture that allows the GXLV pro-
cessor to refresh the display from a compressed copy of
the frame buffer. DCT architecture typically decreases the
screen refresh bandwidth requirement by a factor of 15 to
20, minimizing bandwidth contention.

1.6.3

XpressRAM Memory Subsystem

The memory controller drives a 64-bit SDRAM port
directly. The SDRAM memory array contains both the
main system memory and the graphics frame buffer. Up to
four module banks of SDRAM are supported. Each mod-
ule bank can have two or four component banks depend-
ing on the memory size and organization. The maximum
configuration is four module banks with four component
banks, each providing a total of 16 open banks. The maxi-
mum memory size is 256 MB.

The memory controller handles multiple requests for
memory data from the GXLV processor, the graphics
accelerator and the display controller. The memory con-
troller contains extensive buffering logic that helps mini-
mize contention for memory bandwidth between graphics
and CPU requests. The memory controller cooperates
with the internal bus controller to determine the cacheabil-
ity of all memory references.

1.6.4

PCI Controller

The GXLV processor incorporates a full-function PCI
interface module that includes the PCI arbiter. All
accesses to external I/O devices are sent over the PCI
bus, although most memory accesses are serviced by the
SDRAM controller. The internal bus interface unit contains
address mapping logic that determines if memory
accesses are targeted for the SDRAM or for the PCI bus.

Revision 1.3

www.national.com

Architecture Overview (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

1.7

GEODE GXLV/CS5530 SYSTEM DESIGNS

A GXLV processor and Geode CS5530 I/O companion
based design provides high performance using 32-bit x86
processing. The two chips integrate video, audio and
memory interface functions normally performed by exter-
nal hardware. The CS5530 enables the full features of the
GXLV processor with MMX support. These features
include full VGA and VESA video, 16-bit stereo sound,
IDE interface, ISA interface, SMM power management,
and IBM's AT compatibility logic. In addition, the CS5530
provides an Ultra DMA/33 interface, MPEG1 assist, and
AC97 Version 2.0 compliant audio.

Figure 1-2 shows a basic block system diagram which
also includes the Geode CS9210 graphics companion for

designs that need to interface to a Dual Scan Super
Twisted Pneumatic (DSTN) panel (instead of a TFT
panel).

Figure 1-3 shows an example of a CS9210 interface in a
typical GXLV/CS5530 based system design. The CS9210
converts the digital RGB output of the CS5530 to the digi-
tal output suitable for driving a color DSTN flat panel LCD.
It can drive all standard color DSTN flat panels up to a
1024x768 resolution.

Figures 1-4 and 1-5 show the signal connections between
the GXLV processor and the CS5530. For connections to
the CS9210, refer to the CS9210 data book.

Figure 1-2. GeodeTM GXLV/CS5530 System Block Diagram

YUV Port

(Video)

RGB Port

PCI Interface

SDRAM

MD[63:0]

PCI Bus

Graphics Data

Video Data

Analog RGB

Digital RGB

(to TFT or DSTN Panel)

CRT

TFT

Panel

USB

(2 Ports)

AC97

Codec

Speakers

ROM

Audio

Micro-
phone

GPIO

Port

(Graphics)

Super

ISA Bus

SDRAM

Serial
Packet

Clocks

I/O

BIOS

IDE

Devices

14.31818

MHz Crystal

IDE Control

DC-DC & Battery

CS9210

Graphics

Companion

DSTN Panel

GeodeTM

GXLV

Processor

GeodeTM

CS5530

I/O Companion

www.national.com

Revision 1.3

Architecture Overview (

Continued

)

odeTM

r
o

ries

Figure 1-3. GeodeTM CS9210 Interface System Diagram

Figure 1-4. GeodeTM GXLV/CS5530 Signal Connections

DRAM Data

Address Control

Panel Control

Panel Data

DSTN

Pixel Port

Pixel Data

LCD

CS5530

CS9210

Graphics

Companion

I/O

DRAM-B

256Kx16 Bit

DRAM-A

256Kx16 Bit

Address Control

DRAM Data

Serial
Configuration

Companion

(Control & Data)

Video Data

GeodeTM

GXLV

Processor

SYSCLK

SERIALP

IRQ13

SMI#

PCLK

CRT_HSYNC

CRT_VSYNC

PIXEL[17:0]

FP_HSYNC

FP_VSYNC

ENA_DISP

VID_VAL

VID_CLK

VID_DATA[7:0]

VID_RDY

INTR

SUSP#

SUSPA#
AD[31:0]

C/BE[3:0]#

PAR

FRAME#

IRDY#

TRDY#
STOP#
LOCK#

DEVSEL#

PERR#
SERR#

REQ0#

GX_CLK
PSERIAL
IRQ13
SMI#
PCLK

HSYNC
VSYNC

PIXEL[23:0]

FP_HSYNC
FP_VSYNC
ENA_DISP
VID_VAL
VID_CLK
VID_DATA[7:0]
VID_RDY
CPU_RST
INTR

SUSP#
SUSPA#
AD[31:0]
C/BE[3:0]#
PAR
FRAME#
IRDY#
TRDY#
STOP#
LOCK#
DEVSEL#
PERR#
SERR#
REQ#
GNT#

GNT0#

GeodeTM GXLV

GeodeTM CS5530

I/O Companion

Exclusive

Interconnect

Signals

(Do not connect to

any other device)

Nonexclusive

Interconnect

Signals

(May also connect

to other circuitry)

Not needed if
CRT only (no TFT)

(Note)

Note:

Refer to Figure 1-5 for interconnection of the pixel lines.

RESET

DCLK

Processor

www.national.com

Revision 1.3

Architecture Overview (

Continued

)

odeTM

r
o

ries

1.7.1

Reference Designs

As described previously, the GXLV series of integrated
processors is designed specifically to work with National's
Geode I/O and graphics companion devices. To help
define and drive the emerging information appliance mar-
ket, several reference systems have been developed by
National Semiconductor. These GXLV processor based
reference systems provide optimized and targeted solu-

tions for three main segments of the information appliance
market: Personal Internet Access, Thin Client, and Set-
top Box. Contact your local National Semiconductor sales
or field support representative for further information on
reference designs for the information appliance market.

Figure 1-6. Example WebPADTM System Diagram

PCMCIA

Touch

Control

512 KB DRAM

Li Batteries/

Charger

Data

PCI Bus

RF Interface

Backlight

Ultra DMA/33

Buttons

Pwr Mgmt

Embedded OS
Applications

DC Sense

Bootloader
Run-Time Diagnostics
Storage

Embedded OS
Applications
Bootloader
Run-Time Diagnostics
Storage

Microcontroller

DSTN

ISA Bus

USB Port

Control

Flash

Card

Optional

SDRAM

CS5530

I/O

Companion

GeodeTM

CS9210/11

Graphics

Companion

GeodeTM

GXLV

Processor

NSC

LM4549

Codec

Linear

Flash

(8 MB)

www.national.com

Revision 1.3

Signal Definitions (

Continued

)

odeTM

r
o

ries

2.1

PIN ASSIGNMENTS

The tables in this section use several common abbrevia-
tions. Table 2-1 lists the mnemonics and their meanings.

Figure 2-2 shows the pin assignment for the 352 BGA with
Table 2-2 and Table 2-3 listing the pin assignments sorted
by pin number and alphabetically by signal name, respec-
tively.

Figure 2-3 shows the pin assignment for the 320 SPGA
with Table 2-4 and Table 2-5 listing the pin assignments
sorted by pin number and alphabetically by signal name,
respectively.

In Section 2.2 "Signal Descriptions" on page 31 a descrip-
tion of each signal is provided within its associated func-
tional group.

Table 2-1. Pin Type Definitions

Mnemonic

Definition

Standard input pin.

I/O

Bidirectional pin.

Totem-pole output.

Open-drain output structure that
allows multiple devices to share the
pin in a wired-OR configuration.

Pull-up resistor.

Pull-down resistor.

s/t/s

Sustained tri-state an active-low tri-
state signal owned and driven by
one and only one agent at a time.
The agent that drives an s/t/s pin low
must drive it high for at least one
clock before letting it float. A new
agent cannot start driving an s/t/s
signal any sooner than one clock
after the previous owner lets it float.
A pull-up resistor on the mother-
board is required to sustain the inac-
tive state until another agent drives
it.

VCC (PWR)

Power pin.

VSS (GND)

Ground pin.

The "#" symbol at the end of a signal
name indicates that the active, or
asserted state occurs when the sig-
nal is at a low voltage level. When
"#" is not present after the signal
name, the signal is asserted when at
a high voltage level.

t/s

Tri-state signal.

Revision 1.3

www.national.com

Signal Definitions (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

Figure 2-2. 352 BGA Pin Assignment Diagram

For order information, refer to Section A.1 "Order Information" on page 246.

Index Corner

VSS

AD27

AD24

AD21

AD16

VCC2

FRAM# DEVS#

VCC3

PERR#

AD15

VSS

AD11

CBE0#

AD6

VCC2

AD4

AD2

VCC3

AD0

AD1

TEST2

MD2

VSS

AD28

AD25

AD22

AD18

VCC2

CBE2# TRDY#

VCC3

LOCK#

PAR

AD14

AD12

AD9

AD7

VCC2

INTR

AD3

VCC3

TEST1 TEST3

MD1

MD33

VSS

AD29

AD31

AD30

AD26

AD23

AD19

VCC2

AD17

IRDY#

VCC3

STOP# SERR# CBE1#

AD13

AD10

AD8

VCC2

AD5

SMI#

VCC3

TEST0

IRQ13

MD32

MD34

MD3

MD35

GNT0#

TDI

REQ2#

VSS

CBE3#

VSS

VCC2

VSS

VCC3

VSS

VCC2

VSS

VCC3

VSS

MD0

VSS

MD4

MD36

GNT2# SUSPA# REQ0#

AD20

MD6

MD5

MD37

TD0

GNT1#

TEST

VSS

MD38

MD7

MD39

VCC3

TMS

SUSP# REQ1#

VSS

MD8

MD40

MD9

FPVSY

TCLK

RESET

VSS

MD41

MD10

MD42

VCC2

CKM1 FPHSY SERLP

VSS

MD11

MD43

MD12

CKM2 VIDVAL CKM0

VSS

MD44

MD13

MD45

VSS

PIX1

PIX0

VSS

MD14

MD46

MD15

VIDCLK

PIX3

PIX2

VSS

MD47

CASA# SYSCLK

PIX4

PIX5

PIX6

VSS

WEB#

WEA# CASB#

PIX7

PIX8

PIX9

VSS

DQM0

DQM4

DQM1

VCC3

PIX10

PIX11

PIX12

VSS

DQM5

CS2#

CS0#

PIX13 CRTHSY PIX14

VSS

RASA# RASB#

MA0

VCC2

PIX15

PIX16 CRTVSY VSS

VSS

MA1

MA2

MA3

DCLK

PIX17

VDAT6 VDAT7

MA4

MA5

MA6

MA7

PCLK

FLT#

VDAT4

VSS

VCC2

VSS

VCC3

VSS

VCC2

VSS

VCC3

VSS

DQM6

VSS

MA8

MA9

MA10

VRDY

VDAT5 VDAT3 VDAT0 EDISP

MD63

VCC2

MD62

MD29

VCC3

MD59

MD26

MD56

MD55

MD22

CKEB

VCC2

MD51

MD18

VCC3

MD48

DQM3

CS1#

MA11

BA0

BA1

VSS

VDAT2 SCLK3 SCLK1 RWCLK VCC2

SCKIN

MD61

VCC3

MD28

MD58

MD25

MD24

MD54

MD21

VCC2

MD20

MD50

VCC3

MD17

DQM7

CS3#

MA12

VSS

VDAT1 SCLK0 SCLK2

MD31

VCC2 SCKOUT MD30

VCC3

MD60

MD27

MD57

VSS

MD23

MD53

VCC2

MD52

MD19

VCC3

MD49

MD16

DQM2

CKEA

VSS

352 BGA - Top View

Note: Signal names have been abbreviated in this figure due to space constraints.

= GND terminal
= PWR terminal (VCC2 = VCC_CORE; VCC3 = VCC_IO)

GXLV

Processor

GeodeTM

www.national.com

Revision 1.3

Signal Definitions (

Continued

)

odeTM

r
o

ries

Table 2-2. 352 BGA Pin Assignments - Sorted by Pin Number

Pin
No.

Signal Name

A1 VSS

A2 VSS

A3 AD27

A4 AD24

A5 AD21

A6 AD16

A7 VCC2

A8 FRAME#

A9 DEVSEL#

A10 VCC3

A11 PERR#

A12 AD15

A13 VSS

A14 AD11

A15 C/BE0#

A16 AD6

A17 VCC2

A18 AD4

A19 AD2

A20 VCC3

A21 AD0

A22 AD1

A23 TEST2

A24 MD2

A25 VSS

A26 VSS

B1 VSS

B2 VSS

B3 AD28

B4 AD25

B5 AD22

B6 AD18

B7 VCC2

B8 C/BE2#

B9 TRDY#

B10 VCC3

B11 LOCK#

B12 PAR

B13 AD14

B14 AD12

B15 AD9

B16 AD7

B17 VCC2

B18 INTR

B19 AD3

B20 VCC3

B21 TEST1

B22 TEST3

B23 MD1

B24 MD33

B25 VSS

B26 VSS

C1 AD29

C2 AD31

C3 AD30

C4 AD26

C5 AD23

C6 AD19

C7 VCC2

C8 AD17

C9 IRDY#

C10 VCC3

C11 STOP#

C12 SERR#

C13 C/BE1#

C14 AD13

C15 AD10

C16 AD8

C17 VCC2

C18 AD5

C19 SMI#

C20 VCC3

C21 TEST0

C22 IRQ13

C23 MD32

C24 MD34

C25 MD3

C26 MD35

D1 GNT0#

D2 TDI

D3 REQ2#

D4 VSS

D5 C/BE3#

D6 VSS

D7 VCC2

D8 VSS

D9 VSS

D10 VCC3

D11 VSS

D12 VSS

D13 VSS

D14 VSS

D15 VSS

D16 VSS

D17 VCC2

D18 VSS

Pin
No.

Signal Name

D19 VSS

D20 VCC3

D21 VSS

D22 MD0

D23 VSS

D24 MD4

D25 MD36

D26 NC

E1 GNT2#

E2 SUSPA#

E3 REQ0#

E4 AD20

E23 MD6

E24 NC

E25 MD5

E26 MD37

F1 TDO

F2 GNT1#

F3 TEST

F4 VSS

F23 VSS

F24 MD38

F25 MD7

F26 MD39

G1 VCC3

G2 VCC3

G3 VCC3

G4 VCC3

G23 VCC3

G24 VCC3

G25 VCC3

G26 VCC3

H1 TMS

H2 SUSP#

H3 REQ1#

H4 VSS

H23 VSS

H24 MD8

H25 MD40

H26 MD9

J1 FP_VSYNC

J2 TCLK

J3 RESET

J4 VSS

J23 VSS

J24 MD41

J25 MD10

J26 MD42

Pin
No.

Signal Name

K1 VCC2

K2 VCC2

K3 VCC2

K4 VCC2

K23 VCC2

K24 VCC2

K25 VCC2

K26 VCC2

L1 CLKMODE1

L2 FP_HSYNC

L3 SERIALP

L4 VSS

L23 VSS

L24 MD11

L25 MD43

L26 MD12

M1 CLKMODE2

M2 VID_VAL

M3 CLKMODE0

M4 VSS

M23 VSS

M24 MD44

M25 MD13

M26 MD45

N1 VSS

N2 PIXEL1

N3 PIXEL0

N4 VSS

N23 VSS

N24 MD14

N25 MD46

N26 MD15

P1 VID_CLK

P2 PIXEL3

P3 PIXEL2

P4 VSS

P23 VSS

P24 MD47

P25 CASA#

P26 SYSCLK

R1 PIXEL4

R2 PIXEL5

R3 PIXEL6

R4 VSS

R23 VSS

R24 WEB#

R25 WEA#

R26 CASB#

Pin
No.

Signal Name

T1 PIXEL7

T2 PIXEL8

T3 PIXEL9

T4 VSS

T23 VSS

T24 DQM0

T25 DQM4

T26 DQM1

U1 VCC3

U2 VCC3

U3 VCC3

U4 VCC3

U23 VCC3

U24 VCC3

U25 VCC3

U26 VCC3

V1 PIXEL10

V2 PIXEL11

V3 PIXEL12

V4 VSS

V23 VSS

V24 DQM5

V25 CS2#

V26 CS0#

W1 PIXEL13

W2 CRT_HSYNC

W3 PIXEL14

W4 VSS

W23 VSS

W24 RASA#

W25 RASB#

W26 MA0

Y1 VCC2

Y2 VCC2

Y3 VCC2

Y4 VCC2

Y23 VCC2

Y24 VCC2

Y25 VCC2

Y26 VCC2

AA1 PIXEL15

AA2 PIXEL16

AA3 CRT_VSYNC

AA4 VSS

AA23 VSS

AA24 MA1

AA25 MA2

AA26 MA3

Pin
No.

Signal Name

Revision 1.3

www.national.com

Signal Definitions (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

AB1 DCLK

AB2 PIXEL17

AB3 VID_DATA6

AB4 VID_DATA7

AB23 MA4

AB24 MA5

AB25 MA6

AB26 MA7

AC1 PCLK

AC2 FLT#

AC3 VID_DATA4

AC4 VSS

AC5 NC

AC6 VSS

AC7 VCC2

AC8 VSS

AC9 VSS

AC10 VCC3

AC11 VSS

AC12 VSS

AC13 VSS

AC14 VSS

AC15 VSS

Pin
No.

Signal Name

AC16 VSS

AC17 VCC2

AC18 VSS

AC19 VSS

AC20 VCC3

AC21 VSS

AC22 DQM6

AC23 VSS

AC24 MA8

AC25 MA9

AC26 MA10

AD1 VID_RDY

AD2 VID_DATA5

AD3 VID_DATA3

AD4 VID_DATA0

AD5 ENA_DISP

AD6 MD63

AD7 VCC2

AD8 MD62

AD9 MD29

AD10 VCC3

AD11 MD59

AD12 MD26

Pin
No.

Signal Name

AD13 MD56

AD14 MD55

AD15 MD22

AD16 CKEB

AD17 VCC2

AD18 MD51

AD19 MD18

AD20 VCC3

AD21 MD48

AD22 DQM3

AD23 CS1#

AD24 MA11

AD25 BA0

AD26 BA1

AE1 VSS

AE2 VSS

AE3 VID_DATA2

AE4 SDCLK3

AE5 SDCLK1

AE6 RW_CLK

AE7 VCC2

AE8 SDCLK_IN

AE9 MD61

Pin
No.

Signal Name

AE10 VCC3

AE11 MD28

AE12 MD58

AE13 MD25

AE14 MD24

AE15 MD54

AE16 MD21

AE17 VCC2

AE18 MD20

AE19 MD50

AE20 VCC3

AE21 MD17

AE22 DQM7

AE23 CS3#

AE24 MA12

AE25 VSS

AE26 VSS

AF1 VSS

AF2 VSS

AF3 VID_DATA1

AF4 SDCLK0

AF5 SDCLK2

AF6 MD31

Pin
No.

Signal Name

AF7 VCC2

AF8 SDCLK_OUT

AF9 MD30

AF10 VCC3

AF11 MD60

AF12 MD27

AF13 MD57

AF14 VSS

AF15 MD23

AF16 MD53

AF17 VCC2

AF18 MD52

AF19 MD19

AF20 VCC3

AF21 MD49

AF22 MD16

AF23 DQM2

AF24 CKEA

AF25 VSS

AF26 VSS

Pin
No.

Signal Name

Table 2-2.

352 BGA Pin Assignments - Sorted by Pin Number (Continued)

www.national.com

Revision 1.3

Signal Definitions (

Continued

)

odeTM

r
o

ries

Table 2-3. 352 BGA Pin Assignments - Sorted Alphabetically by Signal Name

Signal Name

Type

Pin No.

AD0

I/O

A21

AD1

I/O

A22

AD2

I/O

A19

AD3

I/O

B19

AD4

I/O

A18

AD5

I/O

C18

AD6

I/O

A16

AD7

I/O

B16

AD8

I/O

C16

AD9

I/O

B15

AD10

I/O

C15

AD11

I/O

A14

AD12

I/O

B14

AD13

I/O

C14

AD14

I/O

B13

AD15

I/O

A12

AD16

I/O

AD17

I/O

AD18

I/O

AD19

I/O

AD20

I/O

AD21

I/O

AD22

I/O

AD23

I/O

AD24

I/O

AD25

I/O

AD26

I/O

AD27

I/O

AD28

I/O

AD29

I/O

AD30

I/O

AD31

I/O

BA0

AD25

BA1

AD26

CASA#

P25

CASB#

R26

C/BE0#

I/O

A15

C/BE1#

I/O

C13

C/BE2#

I/O

C/BE3#

I/O

CKEA

AF24

CKEB

AD16

CLKMODE0

CLKMODE1

CLKMODE2

CRT_HSYNC

CRT_VSYNC

AA3

CS0#

V26

CS1#

AD23

CS2#

V25

CS3#

AE23

DCLK

AB1

DEVSEL#

s/t/s

A9 (PU)

DQM0

T24

DQM1

T26

DQM2

AF23

DQM3

AD22

DQM4

T25

DQM5

V24

DQM6

AC22

DQM7

AE22

ENA_DISP

AD5

FLT#

AC2

FP_HSYNC

FP_VSYNC

FRAME#

s/t/s

A8 (PU)

GNT0#

GNT1#

GNT2#

INTR

B18

IRDY#

s/t/s

C9 (PU)

IRQ13

C22

LOCK#

s/t/s

B11 (PU)

MA0

W26

MA1

AA24

MA2

AA25

MA3

AA26

MA4

AB23

MA5

AB24

MA6

AB25

MA7

AB26

MA8

AC24

MA9

AC25

MA10

AC26

MA11

AD24

MA12

AE24

MD0

I/O

D22

MD1

I/O

B23

MD2

I/O

A24

MD3

I/O

C25

MD4

I/O

D24

MD5

I/O

E25

MD6

I/O

E23

MD7

I/O

F25

MD8

I/O

H24

MD9

I/O

H26

MD10

I/O

J25

MD11

I/O

L24

MD12

I/O

L26

MD13

I/O

M25

MD14

I/O

N24

MD15

I/O

N26

MD16

I/O

AF22

MD17

I/O

AE21

MD18

I/O

AD19

MD19

I/O

AF19

Signal Name

Type

Pin No.

MD20

I/O

AE18

MD21

I/O

AE16

MD22

I/O

AD15

MD23

I/O

AF15

MD24

I/O

AE14

MD25

I/O

AE13

MD26

I/O

AD12

MD27

I/O

AF12

MD28

I/O

AE11

MD29

I/O

AD9

MD30

I/O

AF9

MD31

I/O

AF6

MD32

I/O

C23

MD33

I/O

B24

MD34

I/O

C24

MD35

I/O

C26

MD36

I/O

D25

MD37

I/O

E26

MD38

I/O

F24

MD39

I/O

F26

MD40

I/O

H25

MD41

I/O

J24

MD42

I/O

J26

MD43

I/O

L25

MD44

I/O

M24

MD45

I/O

M26

MD46

I/O

N25

MD47

I/O

P24

MD48

I/O

AD21

MD49

I/O

AF21

MD50

I/O

AE19

MD51

I/O

AD18

MD52

I/O

AF18

MD53

I/O

AF16

MD54

I/O

AE15

MD55

I/O

AD14

MD56

I/O

AD13

MD57

I/O

AF13

MD58

I/O

AE12

MD59

I/O

AD11

MD60

I/O

AF11

MD61

I/O

AE9

MD62

I/O

AD8

MD63

I/O

AD6

D26

E24

AC5

PAR

I/O

B12

PCLK

AC1

PERR#

s/t/s

A11 (PU)

PIXEL0

PIXEL1

PIXEL2

Signal Name

Type

Pin No.

PIXEL3

PIXEL4

PIXEL5

PIXEL6

PIXEL7

PIXEL8

PIXEL9

PIXEL10

PIXEL11

PIXEL12

PIXEL13

PIXEL14

PIXEL15

AA1

PIXEL16

AA2

PIXEL17

AB2

RASA#

W24

RASB#

W25

REQ0#

E3 (PU)

REQ1#

H3 (PU)

REQ2#

D3 (PU)

RESET

RW_CLK

AE6

SDCLK_IN

AE8

SDCLK_OUT

AF8

SDCLK0

AF4

SDCLK1

AE5

SDCLK2

AF5

SDCLK3

AE4

SERIALP

SERR#

C12 (PU)

SMI#

C19

STOP#

s/t/s

C11 (PU)

SUSP#

H2 (PU)

SUSPA#

SYSCLK

P26

TCLK

J2 (PU)

TDI

D2 (PU)

TDO

TEST

F3 (PD)

TEST0

C21

TEST1

B21

TEST2

A23

TEST3

B22

TMS

H1 (PU)

TRDY#

s/t/s

B9 (PU)

VCC2

PWR

VCC2

PWR

A17

VCC2

PWR

VCC2

PWR

B17

VCC2

PWR

VCC2

PWR

C17

VCC2

PWR

VCC2

PWR

D17

Signal Name

Type

Pin No.

Revision 1.3

www.national.com

Signal Definitions (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

Note: PU/PD indicates pin is

internally connected to a
weak (> 20-kohm) pull-
up/-down resistor.

VCC2

PWR

VCC2

PWR

VCC2

PWR

VCC2

PWR

VCC2

PWR

K23

VCC2

PWR

K24

VCC2

PWR

K25

VCC2

PWR

K26

VCC2

PWR

VCC2

PWR

VCC2

PWR

VCC2

PWR

VCC2

PWR

Y23

VCC2

PWR

Y24

VCC2

PWR

Y25

VCC2

PWR

Y26

VCC2

PWR

AC7

VCC2

PWR

AC17

VCC2

PWR

AD7

VCC2

PWR

AD17

VCC2

PWR

AE7

VCC2

PWR

AE17

VCC2

PWR

AF7

VCC2

PWR

AF17

VCC3

PWR

A10

VCC3

PWR

A20

VCC3

PWR

B10

VCC3

PWR

B20

VCC3

PWR

C10

VCC3

PWR

C20

VCC3

PWR

D10

VCC3

PWR

D20

VCC3

PWR

VCC3

PWR

VCC3

PWR

VCC3

PWR

Signal Name

Type

Pin No.

VCC3

PWR

G23

VCC3

PWR

G24

VCC3

PWR

G25

VCC3

PWR

G26

VCC3

PWR

VCC3

PWR

VCC3

PWR

VCC3

PWR

VCC3

PWR

U23

VCC3

PWR

U24

VCC3

PWR

U25

VCC3

PWR

U26

VCC3

PWR

AC10

VCC3

PWR

AC20

VCC3

PWR

AD10

VCC3

PWR

AD20

VCC3

PWR

AE10

VCC3

PWR

AE20

VCC3

PWR

AF10

VCC3

PWR

AF20

VID_CLK

VID_DATA0

AD4

VID_DATA1

AF3

VID_DATA2

AE3

VID_DATA3

AD3

VID_DATA4

AC3

VID_DATA5

AD2

VID_DATA6

AB3

VID_DATA7

AB4

VID_RDY

AD1

VID_VAL

VSS

GND

VSS

GND

VSS

GND

A13

VSS

GND

A25

VSS

GND

A26

Signal Name

Type

Pin No.

VSS

GND

VSS

GND

VSS

GND

B25

VSS

GND

B26

VSS

GND

VSS

GND

VSS

GND

VSS

GND

VSS

GND

D11

VSS

GND

D12

VSS

GND

D13

VSS

GND

D14

VSS

GND

D15

VSS

GND

D16

VSS

GND

D18

VSS

GND

D19

VSS

GND

D21

VSS

GND

D23

VSS

GND

VSS

GND

F23

VSS

GND

VSS

GND

H23

VSS

GND

VSS

GND

J23

VSS

GND

VSS

GND

L23

VSS

GND

VSS

GND

M23

VSS

GND

VSS

GND

VSS

GND

N23

VSS

GND

VSS

GND

P23

VSS

GND

VSS

GND

R23

VSS

GND

Signal Name

Type

Pin No.

VSS

GND

T23

VSS

GND

VSS

GND

V23

VSS

GND

VSS

GND

W23

VSS

GND

AA4

VSS

GND

AA23

VSS

GND

AC4

VSS

GND

AC6

VSS

GND

AC8

VSS

GND

AC9

VSS

GND

AC11

VSS

GND

AC12

VSS

GND

AC13

VSS

GND

AC14

VSS

GND

AC15

VSS

GND

AC16

VSS

GND

AC18

VSS

GND

AC19

VSS

GND

AC21

VSS

GND

AC23

VSS

GND

AE1

VSS

GND

AE2

VSS

GND

AE25

VSS

GND

AE26

VSS

GND

AF1

VSS

GND

AF2

VSS

GND

AF14

VSS

GND

AF25

VSS

GND

AF26

WEA#

R25

WEB#

R24

Signal Name

Type

Pin No.

Table 2-3.

352 BGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued)

www.national.com

Revision 1.3

Signal Definitions (

Continued

)

odeTM

r
o

ries

Figure 2-3. 320 SPGA Pin Assignment Diagram

For order information, refer to Section A.1 "Order Information" on page 246.

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Index Corner

27 28 29 30 31 32 33 34 35 36 37

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

VCC3

AD25

VSS

VCC2

AD16

VCC3

STOP#

SERR#

VSS

AD11

AD8

VCC3

AD2

VCC2

VSS

TEST0

VCC3

VSS

AD27

CBE3#

AD21

AD19

CBE2#

TRDY#

LOCK#

CBE1#

AD13

AD9

AD6

AD3

SMI#

AD1

TEST2

MD33

MD2

VCC3

AD31

AD26

AD23

VCC2

AD18

FRAME#

VSS

PAR

VCC3

AD10

VSS

AD4

AD0

VCC2

IRQ13

MD1

MD34

VCC3

AD30

AD29

AD24

AD22

AD20

AD17

IRDY#

PERR#

AD14

AD12

AD7

INTR

TEST1

TEST3

MD0

MD32

MD3

MD35

REQ0#

REQ2#

AD28

VSS

VCC2

VSS

DEVSEL#

AD15

VSS

CBE0#

AD5

VSS

VCC2

VSS

MD4

MD36

GNT0#

TDI

MD5

VSS

CKMD2

VSS

MD37

VSS

GNT2#

SUSPA#

TDO

VSS

TEST

REQ1#

GNT1#

VCC2

RESET

SUSP#

VCC3

TMS

VSS

FPVSYNC

TCLK

SERIALP

VSS

CKMD1

FPHSYNC

CKMD0

VID_VAL

PIX0

PIX1

PIX2

VSS

VCC3

VSS

PIX3

VID_CLK

PIX6

PIX5

PIX4

PIX9

PIX8

VSS

PIX7

PIX10

VCC3

PIX11

VSS

PIX12

PIX13

VCC2

CRTHSYNC

DCLK

PIX14

VSS

VCC2

PIX15

PIX16

VSS

PIX17

VSS

CRTVSYNC

VDAT6

MD6

MD38

VCC2

VSS

MD7

MD39

MD8

VCC2

MD40

MD9

VSS

MD41

VCC3

MD10

MD42

MD11

VSS

MD43

MD44

MD12

MD14

MD13

MD45

MD15

MD46

VSS

VCC3

VSS

SYSCLK

MD47

WEA#

WEB#

CASA#

DQM0

CASB#

DQM1

VSS

DQM4

CS2#

DQM5

VSS

CS0#

VCC3

RASB#

RASA#

VCC2

VSS

MA1

MA2

MA0

MA4

MA3

VSS

MA5

VSS

MA8

MA6

MA10

PCLK

FLT#

VDAT5

VSS

VCC2

MD31

VSS

MD60

MD57

VSS

MD22

MD52

VSS

VCC2

VSS

BA1

MA9

MA7

VRDY

VSS

VDAT0

SDCLK0

SDCLK2

SDCLKIN

MD29

MD27

MD56

MD55

MD21

MD20

MD50

MD16

DQM3

CS3#

VSS

BA0

VCC2

VDAT4

VDAT2

SDCLK1

VCC2

RWCLK

SDCLKOUT

VSS

MD58

VCC3

MD23

VSS

MD19

MD49

VCC2

DQM6

CKEA

MA11

VCC3

VDAT7

VDAT3

ENDIS

SDCLK3

MD63

MD30

MD61

MD59

MD25

MD24

MD53

MD51

MD18

MD48

DQM7

DQM2

MA12

VSS

VCC2

VDAT1

VSS

VCC2

MD62

VCC3

MD28

MD26

VSS

MD54

CKEB

VCC3

MD17

VCC2

VSS

CS1#

VCC3

VSS

Note: Signal names have been abbreviated in this figure due to space constraints.

= Denotes GND terminal
= Denotes PWR terminal (VCC2 = VCC_CORE; VCC3 = VCC_IO)

320 SPGA - Top View

GXLV

Processor

GeodeTM

Revision 1.3

www.national.com

Signal Definitions (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

Table 2-4. 320 SPGA Pin Assignments - Sorted by Pin Number

Pin
No.

Signal Name

A3 VCC3

A5 AD25

A7 VSS

A9 VCC2

A11 AD16

A13 VCC3

A15 STOP#

A17 SERR#

A19 VSS

A21 AD11

A23 AD8

A25 VCC3

A27 AD2

A29 VCC2

A31 VSS

A33 TEST0

A35 VCC3

A37 VSS

B2 VSS

B4 AD27

B6 C/BE3#

B8 AD21

B10 AD19

B12 C/BE2#

B14 TRDY#

B16 LOCK#

B18 C/BE1#

B20 AD13

B22 AD9

B24 AD6

B26 AD3

B28 SMI#

B30 AD1

B32 TEST2

B34 MD33

B36 MD2

C1 VCC3

C3 AD31

C5 AD26

C7 AD23

C9 VCC2

C11 AD18

C13 FRAME#

C15 VSS

C17 PAR

C19 VCC3

C21 AD10

C23 VSS

C25 AD4

C27 AD0

C29 VCC2

C31 IRQ13

C33 MD1

C35 MD34

C37 VCC3

D2 AD30

D4 AD29

D6 AD24

D8 AD22

D10 AD20

D12 AD17

D14 IRDY#

D16 PERR#

D18 AD14

D20 AD12

D22 AD7

D24 INTR

D26 TEST1

D28 TEST3

D30 MD0

D32 MD32

D34 MD3

D36 MD35

E1 REQ0#

E3 REQ2#

E5 AD28

E7 VSS

E9 VCC2

E11 VCC2

E13 VSS

E15 DEVSEL#

E17 AD15

E19 VSS

E21 C/BE0#

E23 AD5

E25 VSS

E27 VCC2

E29 VCC2

E31 VSS

E33 MD4

E35 MD36

E37 NC

F2 GNT0#

F4 TDI

F34 MD5

F36 NC

Pin
No.

Signal Name

G1 VSS

G3 CLKMODE2

G5 VSS

G33 VSS

G35 MD37

G37 VSS

H2 GNT2#

H4 SUSPA#

H34 MD6

H36 MD38

J1 TDO

J3 VSS

J5 TEST

J33 VCC2

J35 VSS

J37 MD7

K2 REQ1#

K4 GNT1#

K34 MD39

K36 MD8

L1 VCC2

L3 VCC2

L5 VCC2

L33 VCC2

L35 VCC2

L37 VCC2

M2 RESET

M4 SUSP#

M34 MD40

M36 MD9

N1 VCC3

N3 TMS

N5 VSS

N33 VSS

N35 MD41

N37 VCC3

P2 FP_VSYNC

P4 TCLK

P34 MD10

P36 MD42

Q1 SERIALP

Q3 VSS

Q5 NC

Q33 MD11

Q35 VSS

Q37 MD43

R2 CLKMODE1

R4 FP_HSYNC

Pin
No.

Signal Name

R34 MD44

R36 MD12

S1 CLKMODE0

S3 VID_VAL

S5 PIXEL0

S33 MD14

S35 MD13

S37 MD45

T2 PIXEL1

T4 PIXEL2

T34 MD15

T36 MD46

U1 VSS

U3 VCC3

U5 VSS

U33 VSS

U35 VCC3

U37 VSS

V2 PIXEL3

V4 VID_CLK

V34 SYSCLK

V36 MD47

W1 PIXEL6

W3 PIXEL5

W5 PIXEL4

W33 WEA#

W35 WEB#

W37 CASA#

X2 NC

X4 PIXEL9

X34 DQM0

X36 CASB#

Y1 PIXEL8

Y3 VSS

Y5 PIXEL7

Y33 DQM1

Y35 VSS

Y37 DQM4

Z2 NC

Z4 PIXEL10

Z34 CS2#

Z36 DQM5

AA1 VCC3

AA3 PIXEL11

AA5 VSS

AA33 VSS

AA35 CS0#

AA37 VCC3

Pin
No.

Signal Name

AB2 PIXEL12

AB4 PIXEL13

AB34 RASB#

AB36 RASA#

AC1 VCC2

AC3 VCC2

AC5 VCC2

AC33 VCC2

AC35 VCC2

AC37 VCC2

AD2 CRT_HSYNC

AD4 DCLK

AD34 MA2

AD36 MA0

AE1 PIXEL14

AE3 VSS

AE5 VCC2

AE33 VCC2

AE35 VSS

AE37 MA1

AF2 PIXEL15

AF4 PIXEL16

AF34 MA4

AF36 MA3

AG1 VSS

AG3 PIXEL17

AG5 VSS

AG33 VSS

AG35 MA5

AG37 VSS

AH2 CRT_VSYNC

AH4 VID_DATA6

AH32 MA10

AH34 MA8

AH36 MA6

AJ1 PCLK

AJ3 FLT#

AJ5 VID_DATA5

AJ7 VSS

AJ9 VCC2

AJ11 MD31

AJ13 VSS

AJ15 MD60

AJ17 MD57

AJ19 VSS

AJ21 MD22

AJ23 MD52

AJ25 VSS

Pin
No.

Signal Name

Revision 1.3

www.national.com

Signal Definitions (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

Table 2-5. 320 SPGA Pin Assignments - Sorted Alphabetically by Signal Name

Signal Name

Type

Pin. No.

AD0

I/O

C27

AD1

I/O

B30

AD2

I/O

A27

AD3

I/O

B26

AD4

I/O

C25

AD5

I/O

E23

AD6

I/O

B24

AD7

I/O

D22

AD8

I/O

A23

AD9

I/O

B22

AD10

I/O

C21

AD11

I/O

A21

AD12

I/O

D20

AD13

I/O

B20

AD14

I/O

D18

AD15

I/O

E17

AD16

I/O

A11

AD17

I/O

D12

AD18

I/O

C11

AD19

I/O

B10

AD20

I/O

D10

AD21

I/O

AD22

I/O

AD23

I/O

AD24

I/O

AD25

I/O

AD26

I/O

AD27

I/O

AD28

I/O

AD29

I/O

AD30

I/O

AD31

I/O

BA0

AK36

BA1

AJ33

CASA#

W37

CASB#

X36

C/BE0#

I/O

E21

C/BE1#

I/O

B18

C/BE2#

I/O

B12

C/BE3#

I/O

CKEA

AL33

CKEB

AN23

CLKMODE0

CLKMODE1

CLKMODE2

CRT_HSYNC

AD2

CRT_VSYNC

AH2

CS0#

AA35

CS1#

AN33

CS2#

Z34

CS3#

AK32

DCLK

AD4

DEVSEL#

s/t/s

E15 (PU)

DQM0

X34

DQM1

Y33

DQM2

AM32

DQM3

AK30

DQM4

Y37

DQM5

Z36

DQM6

AL31

DQM7

AM30

ENA_DISP

AM6

FLT#

AJ3

FP_HSYNC

FP_VSYNC

FRAME#

s/t/s

C13 (PU)

GNT0#

GNT1#

GNT2#

INTR

D24

IRDY#

s/t/s

D14 (PU)

IRQ13

C31

LOCK#

s/t/s

B16 (PU)

MA0

AD36

MA1

AE37

MA2

AD34

MA3

AF36

MA4

AF34

MA5

AG35

MA6

AH36

MA7

AJ37

MA8

AH34

MA9

AJ35

MA10

AH32

MA11

AL35

MA12

AM34

MD0

I/O

D30

MD1

I/O

C33

MD2

I/O

B36

MD3

I/O

D34

MD4

I/O

E33

MD5

I/O

F34

MD6

I/O

H34

MD7

I/O

J37

MD8

I/O

K36

MD9

I/O

M36

MD10

I/O

P34

MD11

I/O

Q33

MD12

I/O

R36

MD13

I/O

S35

MD14

I/O

S33

MD15

I/O

T34

MD16

I/O

AK28

MD17

I/O

AN27

MD18

I/O

AM26

MD19

I/O

AL25

Signal Name

Type

Pin. No.

MD20

I/O

AK24

MD21

I/O

AK22

MD22

I/O

AJ21

MD23

I/O

AL21

MD24

I/O

AM20

MD25

I/O

AM18

MD26

I/O

AN17

MD27

I/O

AK16

MD28

I/O

AN15

MD29

I/O

AK14

MD30

I/O

AM12

MD31

I/O

AJ11

MD32

I/O

D32

MD33

I/O

B34

MD34

I/O

C35

MD35

I/O

D36

MD36

I/O

E35

MD37

I/O

G35

MD38

I/O

H36

MD39

I/O

K34

MD40

I/O

M34

MD41

I/O

N35

MD42

I/O

P36

MD43

I/O

Q37

MD44

I/O

R34

MD45

I/O

S37

MD46

I/O

T36

MD47

I/O

V36

MD48

I/O

AM28

MD49

I/O

AL27

MD50

I/O

AK26

MD51

I/O

AM24

MD52

I/O

AJ23

MD53

I/O

AM22

MD54

I/O

AN21

MD55

I/O

AK20

MD56

I/O

AK18

MD57

I/O

AJ17

MD58

I/O

AL17

MD59

I/O

AM16

MD60

I/O

AJ15

MD61

I/O

AM14

MD62

I/O

AN11

MD63

I/O

AM10

E37

F36

AM36

PAR

I/O

C17

PCLK

AJ1

PERR#

s/t/s

D16 (PU)

Signal Name

Type

Pin. No.

PIXEL0

PIXEL1

PIXEL2

PIXEL3

PIXEL4

PIXEL5

PIXEL6

PIXEL7

PIXEL8

PIXEL9

PIXEL10

PIXEL11

AA3

PIXEL12

AB2

PIXEL13

AB4

PIXEL14

AE1

PIXEL15

AF2

PIXEL16

AF4

PIXEL17

AG3

RASA#

AB36

RASB#

AB34

REQ0#

E1 (PU)

REQ1#

K2 (PU)

REQ2#

E3 (PU)

RESET

RW_CLK

AL11

SDCLK_IN

AK12

SDCLK_OUT

AL13

SDCLK0

AK8

SDCLK1

AL7

SDCLK2

AK10

SDCLK3

AM8

SERIALP

SERR#

A17 (PU)

SMI#

B28

STOP#

s/t/s

A15 (PU)

SUSP#

M4 (PU)

SUSPA#

SYSCLK

V34

TCLK

P4 (PU)

TDI

F4 (PU)

TDO

TEST

J5 (PD)

TEST0

A33

TEST1

D26

TEST2

B32

TEST3

D28

TMS

N3 (PU)

TRDY#

s/t/s

B14 (PU)

VCC2

PWR

VCC2

PWR

A29

VCC2

PWR

VCC2

PWR

C29

VCC2

PWR

Signal Name

Type

Pin. No.

www.national.com

Revision 1.3

Signal Definitions (

Continued

)

odeTM

r
o

ries

Note: PU/PD indicates pin is

internally connected to a
weak (> 20-kohm)
pull-up/down resistor.

VCC2

PWR

E11

VCC2

PWR

E27

VCC2

PWR

E29

VCC2

PWR

J33

VCC2

PWR

VCC2

PWR

VCC2

PWR

VCC2

PWR

L33

VCC2

PWR

L35

VCC2

PWR

L37

VCC2

PWR

AC1

VCC2

PWR

AC3

VCC2

PWR

AC5

VCC2

PWR

AC33

VCC2

PWR

AC35

VCC2

PWR

AC37

VCC2

PWR

AE5

VCC2

PWR

AE33

VCC2

PWR

AJ9

VCC2

PWR

AJ27

VCC2

PWR

AJ29

VCC2

PWR

AL1

VCC2

PWR

AL9

VCC2

PWR

AL29

VCC2

PWR

AN3

VCC2

PWR

AN9

VCC2

PWR

AN29

VCC3

PWR

VCC3

PWR

A13

Signal Name

Type

Pin. No.

VCC3

PWR

A25

VCC3

PWR

A35

VCC3

PWR

VCC3

PWR

C19

VCC3

PWR

C37

VCC3

PWR

VCC3

PWR

N37

VCC3

PWR

VCC3

PWR

U35

VCC3

PWR

AA1

VCC3

PWR

AA37

VCC3

PWR

AL19

VCC3

PWR

AL37

VCC3

PWR

AN13

VCC3

PWR

AN25

VCC3

PWR

AN35

VID_CLK

VID_DATA0

AK6

VID_DATA1

AN5

VID_DATA2

AL5

VID_DATA3

AM4

VID_DATA4

AL3

VID_DATA5

AJ5

VID_DATA6

AH4

VID_DATA7

AM2

VID_RDY

AK2

VID_VAL

VSS

GND

VSS

GND

A19

Signal Name

Type

Pin. No.

VSS

GND

A31

VSS

GND

A37

VSS

GND

VSS

GND

C15

VSS

GND

C23

VSS

GND

VSS

GND

E13

VSS

GND

E19

VSS

GND

E25

VSS

GND

E31

VSS

GND

VSS

GND

VSS

GND

G33

VSS

GND

G37

VSS

GND

VSS

GND

J35

VSS

GND

VSS

GND

N33

VSS

GND

VSS

GND

Q35

VSS

GND

VSS

GND

VSS

GND

U33

VSS

GND

U37

VSS

GND

VSS

GND

Y35

VSS

GND

AA5

VSS

GND

AA33

VSS

GND

AE3

Signal Name

Type

Pin. No.

VSS

GND

AE35

VSS

GND

AG1

VSS

GND

AG5

VSS

GND

AG33

VSS

GND

AG37

VSS

GND

AJ7

VSS

GND

AJ13

VSS

GND

AJ19

VSS

GND

AJ25

VSS

GND

AJ31

VSS

GND

AK4

VSS

GND

AK34

VSS

GND

AL15

VSS

GND

AL23

VSS

GND

AN1

VSS

GND

AN7

VSS

GND

AN19

VSS

GND

AN31

VSS

GND

AN37

WEA#

W33

WEB#

W35

Signal Name

Type

Pin. No.

Table 2-5.

320 SPGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued)

Revision 1.3

www.national.com

Signal Definitions (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

2.2

SIGNAL DESCRIPTIONS

2.2.1

System Interface Signals

Signal Name

BGA

Pin No.

SPGA

Pin No.

Type

Description

SYSCLK

P26

V34

System Clock

PCI clock is connected to SYSCLK. The internal clock of the
GXLV processor is generated by a proprietary patented fre-
quency synthesis circuit which multiplies the SYSCLK input up to
ten times. The SYSCLK to core clock multiplier is configured
using the CLKMODE[2:0] inputs.

The SYSCLK input is a fixed frequency which can only be
stopped or varied when the GXLV processor is in full 3V Sus-
pend. (See Section 5.1.4 "3 Volt Suspend" on page 177 for
details regarding this mode.)

CLKMODE[2:0]

M1, L1,

G3, R2,

Clock Mode

These signals are used to set the core clock multiplier. The PCI
clock "SYSCLK" is multiplied by the value set by CLKMODE[2:0]
to generate the GXLV processor's core clock.

CLKMODE[2:0]:
000 = SYSCLK multiplied by 4 (Test mode only)
001 = SYSCLK multiplied by 10
010 = SYSCLK multiplied by 9
011 = SYSCLK multiplied by 5
100 = SYSCLK multiplied by 4
101 = SYSCLK multiplied by 6
110 = SYSCLK multiplied by 7
111 = SYSCLK multiplied by 8

RESET

Reset

RESET aborts all operations in progress and places the
GXLV processor into a reset state. RESET forces the CPU and
peripheral functions to begin executing at a known state. All data
in the on-chip cache is invalidated upon RESET.

RESET is an asynchronous input but must meet specified setup
and hold times to guarantee recognition at a particular clock
edge. This input is typically generated during the Power-On-
Reset sequence.

INTR

B18

D24

(Maskable) Interrupt Request

INTR is a level-sensitive input that causes the GXLV processor to
suspend execution of the current instruction stream and begin
execution of an interrupt service routine. The INTR input can be
masked through the EFlags Register IF bit. (See Table 3-4 on
page 46 for bit definitions.)

IRQ13

C22

C31

Interrupt Request Level 13

IRQ13 is asserted if an on-chip floating point error occurs.

When a floating point error occurs, the GXLV processor asserts
the IRQ13 pin. The floating point interrupt handler then performs
an OUT instruction to I/O address F0h or F1h. The GXLV proces-
sor accepts either of these cycles and clears the IRQ13 pin.

Refer to Section 3.4.1 "I/O Address Space" on page 63 for fur-
ther information on IN/OUT instructions.

www.national.com

Revision 1.3

Signal Definitions (

Continued

)

odeTM

r
o

ries

SMI#

C19

B28

System Management Interrupt

SMI# is a level-sensitive interrupt. SMI# puts the GXLV proces-
sor into System Management Mode (SMM).

SUSP#

(PU)

Suspend Request

This signal is used to request that the GXLV processor enter
Suspend mode. After recognition of an active SUSP# input, the
processor completes execution of the current instruction, any
pending decoded instructions and associated bus cycles.
SUSP# is enabled by setting the SUSP bit in CCR2, and is
ignored following RESET. (See Table 3-11 on page 52 for CCR2
bit definitions.)

Since the GXLV processor includes system logic functions as
well as the CPU core, there are special modes designed to sup-
port the different power management states associated with
APM, ACPI, and portable designs. The part can be configured to
stop only the CPU core clocks, or all clocks. When all clocks are
stopped, the external clock can also be stopped. (See Section
5.0 "Power Management" on page 176 for more details regarding
power management states.)

This pin is internally connected to a weak (>20-kohm) pull-up
resistor.

SUSPA#

Suspend Acknowledge

Suspend Acknowledge indicates that the GXLV processor has
entered low-power Suspend mode as a result of SUSP# asser-
tion or execution of a HALT instruction. SUSPA# floats following
RESET and is enabled by setting the SUSP bit in CCR2. (See
Table 3-11 on page 52 for CCR2 bit definitions.)

The SYSCLK input may be stopped after SUSPA# has been
asserted to further reduce power consumption if the system is
configured for 3V Suspend mode. (see Section 5.1.4 "3 Volt Sus-
pend" on page 177 for details regarding this mode).

SERIALP

Serial Packet

Serial Packet is the single wire serial-transmission signal to the
CS5530 chip. The clock used for this interface is SYSCLK. This
interface carries packets of miscellaneous information to the
chipset to be used by the VSA technology software handlers.

2.2.1

System Interface Signals (Continued)

Signal Name

BGA

Pin No.

SPGA

Pin No.

Type

Description

Revision 1.3

www.national.com

Signal Definitions (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

2.2.2

PCI Interface Signals

Signal Name

BGA

Pin No.

SPGA

Pin No

Type

Description

FRAME#

(PU)

C13

(PU)

s/t/s

Frame

FRAME# is driven by the current master to indicate the begin-
ning and duration of an access. FRAME# is asserted to indicate
a bus transaction is beginning. While FRAME# is asserted, data
transfers continue. When FRAME# is deasserted, the transac-
tion is in the final data phase.

This pin is internally connected to a weak (>20-kohm) pull-up
resistor.

IRDY#

(PU)

D14

(PU)

s/t/s

Initiator Ready

IRDY# is asserted to indicate that the bus master is able to com-
plete the current data phase of the transaction. IRDY# is used in
conjunction with TRDY#. A data phase is completed on any
SYSCLK in which both IRDY# and TRDY# are sampled
asserted. During a write, IRDY# indicates valid data is present
on AD[31:0]. During a read, it indicates the master is prepared to
accept data. Wait cycles are inserted until both IRDY# and
TRDY# are asserted together.

This pin is internally connected to a weak (>20-kohm) pull-up
resistor.

TRDY#

(PU)

B14

(PU)

s/t/s

Target Ready

TRDY# is asserted to indicate that the target agent is able to
complete the current data phase of the transaction. TRDY# is
used in conjunction with IRDY#. A data phase is complete on any
SYSCLK in which both TRDY# and IRDY# are sampled
asserted. During a read, TRDY# indicates that valid data is
present on AD[31:0]. During a write, it indicates the target is pre-
pared to accept data. Wait cycles are inserted until both IRDY#
and TRDY# are asserted together.

This pin is internally connected to a weak (>20-kohm) pull-up
resistor.

STOP#

C11

(PU)

A15

(PU)

s/t/s

Target Stop

STOP# is asserted to indicate that the current target is request-
ing the master to stop the current transaction. This signal is used
with DEVSEL# to indicate retry, disconnect or target abort. If
STOP# is sampled active while a master, FRAME# will be deas-
serted and the cycle will be stopped within three SYSCLKs.
STOP# can be asserted in the following cases:

· A PCI master tries to access memory that has been locked by

another master. This condition is detected if FRAME# and
LOCK# are asserted during an address phase.

· The PCI write buffers are full or a previously buffered cycle

has not completed.

· Read cycles that cross cache line boundaries. This is condi-

tional based upon the programming of bit 1 in the PCI Control
Function 2 Register.

This pin is internally connected to a weak (>20-kohm) pull-up
resistor.

www.national.com

Revision 1.3

Signal Definitions (

Continued

)

odeTM

r
o

ries

AD[31:0]

Refer

Table 2-3

Refer

Table 2-5

I/O

Multiplexed Address and Data

Addresses and data are multiplexed together on the same pins.
A bus transaction consists of an address phase in the cycle in
which FRAME# is asserted followed by one or more data
phases. During the address phase, AD[31:0] contain a physical
32-bit address. During data phases, AD[7:0] contain the least
significant byte (LSB) and AD[31:24] contain the most significant
byte (MSB). Write data is stable and valid when IRDY# is
asserted and read data is stable and valid when TRDY# is
asserted. Data is transferred during the SYSCLK when both
IRDY# and TRDY# are asserted.

C/BE[3:0]#

D5,
B8,

C13, A15

B6,

B12,

B18, E21

I/O

Multiplexed Command and Byte Enables

C/BE# are the bus commands and byte enables. They are multi-
plexed together on the same PCI pins. During the address phase
of a transaction when FRAME# is active, C/BE[3:0]# define the
bus command. During the data phase C/BE[3:0]# are used as
byte enables. The byte enables are valid for the entire data
phase and determine which byte lanes carry meaningful data.
C/BE0# applies to byte 0 (LSB) and C/BE3# applies to byte 3
(MSB).

The command encoding and types are listed below.

0000 = Interrupt Acknowledge
0001 = Special Cycle
0010 = I/O Read
0011 = I/O Write
0100 = Reserved
0101 = Reserved
0110 = Memory Read
0111 = Memory Write
1000 = Reserved
1001 = Reserved
1010 = Configuration Read
1011 = Configuration Write
1100 = Memory Read Multiple
1101 = Dual Address Cycle (Reserved)
1110 = Memory Read Line
1111 = Memory Write and Invalidate

PAR

B12

C17

I/O

Parity

PAR is used with AD[31:0] and C/BE[3:0]# to generate even par-
ity. Parity generation is required by all PCI agents: the master
drives PAR for address and write-data phases, the target drives
PAR for read-data phases.

For address phases, PAR is stable and valid one SYSCLK after
the address phase.

For data phases, PAR is stable and valid one SYSCLK after
either IRDY# is asserted on a write transaction or after TRDY# is
asserted on a read transaction. Once PAR is valid, it remains
valid until one SYSCLK after the completion of the data phase.
(Also see PERR# description on page 35.)

2.2.2

PCI Interface Signals (Continued)

Signal Name

BGA

Pin No.

SPGA

Pin No

Type

Description

Revision 1.3

www.national.com

Signal Definitions (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

LOCK#

B11

(PU)

B16

(PU)

s/t/s

Lock Operation

LOCK# indicates an atomic operation that may require multiple
transactions to complete. When LOCK# is asserted, nonexclu-
sive transactions may proceed to an address that is not currently
locked (at least 16 bytes must be locked). A grant to start a trans-
action on PCI does not guarantee control of LOCK#. Control of
LOCK# is obtained under its own protocol in conjunction with
GNT#. It is possible for different agents to use PCI while a single
master retains ownership of LOCK#. The arbiter can implement
a complete system lock. In this mode, if LOCK# is active, no
other master can gain access to the system until the LOCK# is
deasserted.

This pin is internally connected to a weak (>20-kohm) pull-up
resistor.

DEVSEL#

(PU)

E15

(PU)

s/t/s

Device Select

DEVSEL# indicates that the driving device has decoded its
address as the target of the current access. As an input,
DEVSEL# indicates whether any device on the bus has been
selected. DEVSEL# will also be driven by any agent that has the
ability to accept cycles on a subtractive decode basis. As a mas-
ter, if no DEVSEL# is detected within and up to the subtractive
decode clock, a master abort cycle will result except for special
cycles which do not expect a DEVSEL# returned.

This pin is internally connected to a weak (>20-kohm) pull-up
resistor.

PERR#

A11

(PU)

D16

(PU)

s/t/s

Parity Error

PERR# is used for the reporting of data parity errors during all
PCI transactions except a Special Cycle. The PERR# line is
driven two SYSCLKs after the data in which the error was
detected, which is one SYSCLK after the PAR that was attached
to the data. The minimum duration of PERR# is one SYSCLK for
each data phase in which a data parity error is detected. PERR#
must be driven high for one SYSCLK before going to TRI-STATE.
A target asserts PERR# on write cycles if it has claimed the
cycle with DEVSEL#. The master asserts PERR# on read
cycles.

This pin is internally connected to a weak (>20-kohm) pull-up
resistor.

SERR#

C12

(PU)

A17

(PU)

System Error

SERR# may be asserted by any agent for reporting errors other
than PCI parity. The intent is to have the PCI central agent assert
NMI to the processor. When the Parity Enable bit is set in the
Memory Controller Configuration register, SERR# will be
asserted upon detecting a parity error on read operations from
DRAM.

REQ[2:0]#

D3,
H3,

(PU)

E3,
K2,

(PU)

Request Lines

REQ# indicates to the arbiter that an agent desires use of the
bus. Each master has its own REQ# line. REQ# priorities are
based on the arbitration scheme chosen.

This pin is internally connected to a weak (>20-kohm) pull-up
resistor.

2.2.2

PCI Interface Signals (Continued)

Signal Name

BGA

Pin No.

SPGA

Pin No

Type

Description

www.national.com

Revision 1.3

Signal Definitions (

Continued

)

odeTM

r
o

ries

GNT[2:0]#

E1,
F2,

H2,
K4,

Grant Lines

GNT# indicates to the requesting master that it has been granted
access to the bus. Each master has its own GNT# line. GNT#
can be pulled away at any time a higher REQ# is received or if
the master does not begin a cycle within a minimum period of
time (16 SYSCLKs).

2.2.2

PCI Interface Signals (Continued)

Signal Name

BGA

Pin No.

SPGA

Pin No

Type

Description

2.2.3

Memory Controller Interface Signals

Signal Name

BGA

Pin No.

SPGA

Pin No.

Type

Description

MD[63:0]

Refer

Table 2-3

Refer

Table 2-5

I/O

Memory Data Bus

The data bus lines driven to/from system memory.

MA[12:0]

Refer

Table 2-3

Refer

Table 2-5

Memory Address Bus

The multiplexed row/column address lines driven to the system
memory.

Supports 256 MB SDRAM.

BA[1:0]

AD26,

AD25

AJ33,

AK36

Bank Address Bits

These bits are used to select the component bank within the
SDRAM.

CS[3:0]#

AE23,

V25,

AD23,

V26

AK32,

Z34,

AN33,

AA35

Chip Selects

The chip selects are used to select the module bank within the
system memory. Each chip select corresponds to a specific mod-
ule bank.

If CS# is high, the bank(s) do not respond to RAS#, CAS#, WE#
until the bank is selected again.

RASA#,
RASB#

W24,

W25

AB36,

AB34

Row Address Strobe

RAS#, CAS#, WE# and CKE are encoded to support the differ-
ent SDRAM commands. RASA# is used with CS[1:0]#. RASB#
is used with CS[3:2]#.

CASA#,
CASB#

P25, R26

W37,

X36

Column Address Strobe

RAS#, CAS#, WE# and CKE are encoded to support the differ-
ent SDRAM commands. CASA# is used with CS[1:0]#. CASB#
is used with CS[3:2]#.

WEA#,
WEB#

R25, R24

W33,

W35

Write Enable

RAS#, CAS#, WE# and CKE are encoded to support the differ-
ent SDRAM commands. WEA# is used with CS[1:0]#. WEB# is
used with CS[3:2]#.

CKEA,
CKEB

AF24,

AD16

AL33,

AN23

Clock Enable

For normal operation, CKE is held high. CKE goes low during
SUSPEND. CKEA is used with CS[1:0]#. CKEB is used with
CS[3:2]#.

Revision 1.3

www.national.com

Signal Definitions (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

DQM[7:0]

Refer

Table 2-3

Refer

Table 2-5

Data Mask Control Bits

During memory read cycles, these outputs control whether the
SDRAM output buffers are driven on the MD bus or not. All DQM
signals are asserted during read cycles.

During memory write cycles, these outputs control whether or
not MD data will be written into the SDRAM.

DQM[0] is associated with MD[7:0].
DQM[7] is associated with MD[63:56].

SDCLK[3:0]

AE4,
AF5,
AE5,

AF4

AM8,

AK10,

AL7,

AK8

SDRAM Clocks

The SDRAM devices sample all the control, address, and data
based on these clocks.

SDCLK_IN

AE8

AK12

SDRAM Clock Input

The GXLV processor samples the memory read data on this
clock. Works in conjunction with the SDCLK_OUT signal.

SDCLK_OUT

AF8

AL13

SDRAM Clock Output

This output is routed back to SDCLK_IN. The board designer
should vary the length of the board trace to control skew
between SDCLK_IN and SDCLK.

2.2.3

Memory Controller Interface Signals (Continued)

Signal Name

BGA

Pin No.

SPGA

Pin No.

Type

Description

2.2.4

Video Interface Signals

Signal Name

BGA

Pin No

SPGA

Pin No

Type

Description

PCLK

AC1

AJ1

Pixel Port Clock

PCLK is the pixel dot clock output. It clocks the pixel data from
the GXLV processor to the CS5530.

VID_CLK

Video Clock

VID_CLK is the video port clock to the CS5530.

DCLK

AB1

AD4

Dot Clock

The DCLK input is driven from the CS5530 and is the pixel dot
clock. In some cases this clock can be a 2x multiple of PCLK

CRT_HSYNC

AD2

CRT Horizontal Sync

CRT Horizontal Sync establishes the line rate and horizontal
retrace interval for an attached CRT. The polarity is programma-
ble. See DC-Timing_CFG Register in Table 4-29 on page 146 for
programming information.

CRT_VSYNC

AA3

AH2

CRT Vertical Sync

CRT Vertical Sync establishes the screen refresh rate and verti-
cal retrace interval for an attached CRT. The polarity is program-
mable. See DC-Timing_CFG Register in Table 4-29 on page 147
for programming information.

www.national.com

Revision 1.3

Signal Definitions (

Continued

)

odeTM

r
o

ries

FP_HSYNC

Flat Panel Horizontal Sync

Flat Panel Horizontal Sync establishes the line rate and horizon-
tal retrace interval for a TFT display. Polarity is programmable.
(See Table 4-31 on page 146 for programming information.)

This signal is an input to the CS5530. The CS5530 re-drives this
signal to the flat panel.

If no flat panel is used in the system, this signal is not connected.

FP_VSYNC

Flat Panel Vertical Sync

Flat Panel Vertical Sync establishes the screen refresh rate and
vertical retrace interval for a TFT display. Polarity is programma-
ble. (See Table 4-31 on page 146 for programming information.)

This signal is an input to the CS5530. The CS5530 re-drives this
signal to the flat panel.

If no flat panel is used in the system, this signal is not connected.

ENA_DISP

AD5

AM6

Display Enable

Display Enable indicates the active display portion of a scan line
to the CS5530.

In a CS5530-based system, this signal is required to be con-
nected.

VID_RDY

AD1

AK2

Video Ready

This input signal indicates that the video FIFO in the CS5530 is
ready to receive more data.

VID_VAL

Video Valid

VID_VAL indicates that video data to the CS5530 is valid.

VID_DATA[7:0]

Refer

Table 2-3

Refer

Table 2-5

Video Data Bus

When the Video Port is enabled, this bus drives Video (YUV or
RGB 5:6:5) data synchronous to the VID_CLK output.

PIXEL[17:0]

Refer

Table 2-3

Refer

Table 2-5

Graphics Pixel Data Bus

This bus drives graphics pixel data synchronous to the PCLK
output.

2.2.4

Video Interface Signals (Continued)

Signal Name

BGA

Pin No

SPGA

Pin No

Type

Description

Revision 1.3

www.national.com

Signal Definitions (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

2.2.5

Power, Ground, and No Connect Signals

Signal Name

BGA

Pin No.

SPGA

Pin No.

Type

Description

VSS

Refer

Table 2-3

(Total of

71)

Refer

Table 2-5

(Total of

50)

GND

Ground Connection

VCC2

Refer

Table 2-3

(Total of

32)

Refer

Table 2-5

(Total of

32)

PWR

2.2V, 2.5V, or 2.9V (Nominal) Core Power Connection

VCC3

Refer

Table 2-3

(Total of

32)

Refer

Table 2-5

(Total of

18)

PWR

3.3V (Nominal) I/O Power Connection

D26,
E24,

AC5

E37,

F36, Q5,

X2, Z2,

AM36

No Connection

A line designated as NC must be left disconnected.

2.2.6

Internal Test and Measurement Signals

Signal Name

BGA

Pin No.

SPGA

Pin No.

Type

Description

FLT#

AC2

AJ3

Float

Float forces the GXLV processor to float all outputs in the high-
impedance state and to enter a power-down state.

RW_CLK

AE6

AL11

Raw Clock

This output is the GXLV processor clock. This debug signal can
be used to verify clock operation.

TEST[3:0]

B22,
A23,
B21,

C21

D28,
B32,
D26,

A33

SDRAM Test Outputs

These outputs are used for internal debug only.

TCLK

(PU)

Test Clock

JTAG test clock.

This pin is internally connected to a weak (>20-kohm) pull-up
resistor.

TDI

(PU)

Test Data Input

JTAG serial test-data input.

This pin is internally connected to a weak (>20-kohm) pull-up
resistor.

TDO

Test Data Output

JTAG serial test-data output.

Revision 1.3

www.national.com

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

3.0

Processor Programming

This section describes the internal operations of the
Geode GXLV processor from a programmer's point of
view. It includes a description of the traditional "core" pro-
cessing and FPU operations. The integrated function reg-
isters are described at the end of this chapter.

The primary register sets within the processor core
include:

· Application Register Set
· System Register Set
· Model Specific Register Set

The initialization of the major registers within the core are
shown in Table 3-1.

The integrated function sets are located in main memory
space and include:

· Internal Bus Interface Unit Register Set
· Graphics Pipeline Register Set
· Display Controller Register Set
· Memory Controller Register Set
· Power Management Register Set

3.1

CORE PROCESSOR INITIALIZATION

The GXLV processor is initialized when the RESET signal
is asserted. The processor is placed in real mode and the
registers listed in Table 3-1 are set to their initialized val-
ues. RESET invalidates and disables the CPU cache, and
turns off paging. When RESET is asserted, the CPU ter-
minates all local bus activity and all internal execution.
While RESET is asserted the internal pipeline is flushed
and no instruction execution or bus activity occurs.

Approximately 150 to 250 external clock cycles after
RESET is deasserted, the processor begins executing
instructions at the top of physical memory (address loca-
tion FFFFFFF0h). The actual number of clock cycles
depends on the clock scaling in use. Also, before execu-
tion begins, an additional 2

clock cycles are needed

when self-test is requested.

Typically, an intersegment jump is placed at FFFFFFF0h.
This instruction will force the processor to begin execution
in the lowest 1 MB of address space.

Table 3-1 lists the core registers and illustrates how they
are initialized.

Table 3-1. Initialized Core Register Controls

Register

Register Name

Initialized Contents

Comments

EAX

Accumulator

xxxxxxxxh

0000 0000h indicates self-test passed.

EBX

Base

xxxxxxxxh

ECX

Count

xxxxxxxxh

EDX

Data

xxxx 04 [DIR0]h

DIR0 = Device ID

EBP

Base Pointer

xxxxxxxxh

ESI

Source Index

xxxxxxxxh

EDI

Destination Index

xxxxxxxxh

ESP

Stack Pointer

xxxxxxxxh

EFLAGS

Flags

00000002h

See Table 3-4 on page 46 for bit definitions.

EIP

Instruction Pointer

0000FFF0h

Extra Segment

0000h

Base address set to 00000000h. Limit set to FFFFh.

Code Segment

F000h

Base address set to FFFF0000h. Limit set to FFFFh.

Stack Segment

0000h

Base address set to 00000000h. Limit set to FFFFh.

Data Segment

0000h

Base address set to 00000000h. Limit set to FFFFh.

Extra Segment

0000h

Base address set to 00000000h. Limit set to FFFFh.

Extra Segment

0000h

Base address set to 00000000h. Limit set to FFFFh.

IDTR

Interrupt Descriptor Table Register

Base = 0, Limit = 3FFh

GDTR

Global Descriptor Table Register

xxxxxxxxh

LDTR

Local Descriptor Table Register

xxxxh

Task Register

xxxxh

CR0

Control Register 0

60000010h

See Table 3-7 on page 49 for bit definitions.

CR2

Control Register 2

xxxxxxxxh

See Table 3-7 on page 49 for bit definitions.

CR3

Control Register 3

xxxxxxxxh

See Table 3-7 on page 48 for bit definitions.

CR4

Control Register 4

00000000h

See Table 3-7 on page 48 for bit definitions.

CCR1

Configuration Control 1

00h

See Table 3-11 on page 52 for bit definitions.

CCR2

Configuration Control 2

00h

See Table 3-11 on page 52 for bit definitions.

CCR3

Configuration Control 3

00h

See Table 3-11 on page 52 for bit definitions.

CCR4

Configuration Control 4

00h

See Table 3-11 on page 52 for bit definitions.

CCR7

Configuration Control 7

00h

See Table 3-11 on page 52 for bit definitions.

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

3.2

INSTRUCTION SET OVERVIEW

The GXLV processor instruction set can be divided into
nine types of operations:

· Arithmetic
· Bit Manipulation
· Shift/Rotate
· String Manipulation
· Control Transfer
· Data Transfer
· Floating Point
· High-Level Language Support
· Operating System Support

The GXLV processor instructions operate on as few as
zero operands and as many as three operands. A NOP
(no operation) instruction is an example of a zero-operand
instruction. Two-operand instructions allow the specifica-
tion of an explicit source and destination pair as part of
the instruction. These two-operand instructions can be
divided into ten groups according to operand types:

· Register to Register
· Register to Memory
· Memory to Register
· Memory to Memory
· Register to I/O
· I/O to Register
· Memory to I/O
· I/O to Memory
· Immediate Data to Register
· Immediate Data to Memory

An operand can be held in the instruction itself (as in the
case of an immediate operand), in one of the processor's
registers or I/O ports, or in memory. An immediate oper-
and is fetched as part of the opcode for the instruction.

Operand lengths of 8, 16, 32 or 48 bits are supported as
well as 64 or 80 bits associated with floating-point instruc-
tions. Operand lengths of 8 or 32 bits are generally used
when executing code written for 386- or 486-class (32-bit
code) processors. Operand lengths of 8 or 16 bits are
generally used when executing existing 8086 or 80286
code (16-bit code). The default length of an operand can
be overridden by placing one or more instruction prefixes
in front of the opcode. For example, the use of prefixes
allows a 32-bit operand to be used with 16-bit code or a
16-bit operand to be used with 32-bit code.

Section 7.3 "Processor Core Instruction Set" on page 216
contains the clock count table that lists each instruction in
the CPU instruction set. Included in the table are the
associated opcodes, execution clock counts, and effects
on the EFLAGS register.

3.2.1

Lock Prefix

The LOCK prefix may be placed before certain instruc-
tions that read, modify, then write back to memory. The
PCI will not be granted access in the middle of locked
instructions. The LOCK prefix can be used with the follow-
ing instructions only when the result is a write operation to
memory.

· Bit Test Instructions (BTS, BTR, BTC)

· Exchange Instructions (XADD, XCHG, CMPXCHG)

· One-Operand Arithmetic and Logical Instructions

(DEC, INC, NEG, NOT)

· Two-Operand Arithmetic and Logical Instructions

(ADC, ADD, AND, OR, SBB, SUB, XOR).

An invalid opcode exception is generated if the LOCK pre-
fix is used with any other instruction or with one of the
instructions above when no write operation to memory
occurs (for example, when the destination is a register).

SMHR

SMM Header Address

000000h

See Table 3-11 on page 54 for bit definitions

SMAR

SMM Address 0

000000h

See Table 3-11 on page 54 for bit definitions.

DIR0

Device Identification 0

4xh

Device ID and reads back initial CPU clock-speed set-
ting. See Table 3-11 on page 54 for bit definitions.

DIR1

Device Identification 1

xxh

Stepping and Revision ID (RO). See Table 3-11 on
page 54 for bit definitions.

DR7

Debug Register 7

00000400h

See Table 3-13 on page 56 for bit definitions.

Note: x = Undefined value

Table 3-1. Initialized Core Register Controls (Continued)

Register

Register Name

Initialized Contents

Comments

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

3.3

REGISTER SETS

The accessible registers in the processor are grouped into
three sets:

The Application Register Set contains the registers
frequently used by application programmers. Table 3-
2 shows the General Purpose, Segment, the Instruc-
tion Pointer and the EFLAGS Registers.

The System Register Set contains the registers typi-
cally reserved for operating systems programmers:
Control, System Address, Debug, Configuration, and
Test Registers.

The Model Specific Register (MSR) Set is used to
monitor the performance of the processor or a
specific component within the processor. The Model
Specific Register set has one 64-bit register called
the Time Stamp Counter.

Each of these register sets are discussed in detail in the
subsections that follow. Additional registers to support
integrated GXLV processor subsystems are described in
Section 4.1 "Integrated Functions Programming Interface"
on page 97.

3.3.1

Application Register Set

The Application Register Set consists of the registers most
often used by the applications programmer. These regis-
ters are generally accessible, although some bits in the
EFLAGS register are protected.

The General Purpose Register contents are frequently
modified by instructions and typically contain arithmetic
and logical instruction operands.

In real mode, Segment Registers contain the base
address for each segment. In protected mode, the seg-
ment registers contain segment selectors. The segment
selectors provide indexing for tables (located in memory)
that contain the base address for each segment, as well
as other memory addressing information.

The Instruction Pointer Register points to the next
instruction that the processor will execute. This register is
automatically incremented by the processor as execution
progresses.

The EFLAGS Register contains control bits used to
reflect the status of previously executed instructions. This
register also contains control bits that affect the operation
of some instructions.

3.3.1.1

General Purpose Registers

The General Purpose Registers are divided into four data
registers, two pointer registers, and two index registers as
shown in Table 3-2.

The Data Registers are used by the applications pro-
grammer to manipulate data structures and to hold the
results of logical and arithmetic operations. Different por-
tions of general data registers can be addressed by using
different names.

An "E" prefix identifies the complete 32-bit register. An "X"
suffix without the "E" prefix identifies the lower 16 bits of
the register.

The lower two bytes of a data register are addressed with
an "H" suffix (identifies the upper byte) or an "L" suffix (iden-
tifies the lower byte). These _L and _H portions of the
data registers act as independent registers. For example,
if the AH register is written to by an instruction, the AL reg-
ister bits remain unchanged.

The Pointer and Index Registers are listed below.

SI or ESI

Source Index

DI or EDI

Destination Index

SP or ESP

Stack Pointer

BP or EBP

Base Pointer

These registers can be addressed as 16- or 32-bit registers,
with the "E" prefix indicating 32 bits. The Pointer and Index
Registers can be used as general purpose registers; how-
ever, some instructions use a fixed assignment of these
registers. For example, repeated string operations always
use ESI as the source pointer, EDI as the destination
pointer, and ECX as a counter. The instructions that use
fixed registers include multiply and divide, I/O access,
string operations, stack operations, loop, variable shift and
rotate, and translate instructions.

The GXLV processor implements a stack using the ESP
Register. This stack is accessed during the PUSH and
POP instructions, procedure calls, procedure returns,
interrupts, exceptions, and interrupt/exception returns.
The GXLV processor automatically adjusts the value of
the ESP during operations that result from these instruc-
tions.

The EBP Register may be used to refer to data passed on
the stack during procedure calls. Local data may also be
placed on the stack and accessed with BP. This register
provides a mechanism to access stack data in high-level
languages.

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

3.3.1.2

Segment Registers

The 16-bit segment registers, part of the main memory
addressing mechanism, are described in Section 3.5 "Off-
set, Segment, and Paging Mechanisms" on page 64. The
six segment registers are:

Code Segment

Data Segment

Stack Segment

Extra Segment

Additional Data Segment

The segment registers are used to select segments in
main memory. A segment acts as private memory for dif-
ferent elements of a program such as code space, data
space and stack space.

There are two segment mechanisms, one for real and vir-
tual 8086 operating modes and one for protected mode.
Initialization and transition to protected mode is described
in Section 3.9.4 "Initialization and Transition to Protected
Mode" on page 93. The segment mechanisms are
described in Section 3.5.2 "Segment Mechanisms" on
page 66.

The active segment register is selected according to the
rules listed in Table 3-3 and the type of instruction being
currently processed. In general, the DS register selector is
used for data references. Stack references use the SS
register, and instruction fetches use the CS register. While
some selections may be overridden, instruction fetches,
stack operations, and the destination write operation of
string operations cannot be overridden. Special segment-
override instruction prefixes allow the use of alternate
segment registers. These segment registers include the
ES, FS, and GS registers.

3.3.1.3

Instruction Pointer Register

The Instruction Pointer (EIP) Register contains the off-
set into the current code segment of the next instruction to
be executed. The register is normally incremented by the
length of the current instruction with each instruction exe-
cution unless it is implicitly modified through an interrupt,
exception, or an instruction that changes the sequential
execution flow (for example JMP and CALL).

Table 3-3 illustrates the code segment selection rules.

Table 3-3. Segment Register Selection Rules

Type of Memory Reference

Implied (Default)

Segment

Segment-Override

Prefix

Code Fetch

None

Destination of PUSH, PUSHF, INT, CALL, PUSHA instructions

None

Source of POP, POPA, POPF, IRET, RET instructions

None

Destination of STOS, MOVS, REP STOS, REP MOVS instructions

None

Other data references with effective address using base registers of:

EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP

CS, ES, FS, GS, SS

CS, DS, ES, FS, GS

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

3.3.1.4

EFLAGS Register

The EFLAGS Register contains status information and
controls certain operations on the GXLV processor. The
lower 16 bits of this register are referred to as the

EFLAGS register that is used when executing 8086 or
80286 code. Table 3-4 gives the bit formats for the
EFLAGS Register

Table 3-4. EFLAGS Register

Bit

Name

Flag Type

Description

31:22

RSVD

Reserved: Set to 0.

System

Identification Bit: The ability to set and clear this bit indicates that the CPUID instruction is sup-
ported. The ID can be modified only if the CPUID bit in CCR4 (Index E8h[7]) is set.

20:19

RSVD

Reserved: Set to 0.

System

Alignment Check Enable: In conjunction with the AM flag (bit 18) in CR0, the AC flag deter-
mines whether or not misaligned accesses to memory cause a fault. If AC is set, alignment faults
are enabled.

System

Virtual 8086 Mode: If set while in protected mode, the processor switches to virtual 8086 opera-
tion handling segment loads as the 8086 does, but generating exception 13 faults on privileged
opcodes. The VM bit can be set by the IRET instruction (if current privilege level is 0) or by task
switches at any privilege level.

Debug

Resume Flag: Used in conjunction with debug register breakpoints. RF is checked at instruction
boundaries before breakpoint exception processing. If set, any debug fault is ignored on the next
instruction.

RSVD

Reserved: Set to 0.

System

Nested Task: While executing in protected mode, NT indicates that the execution of the current
task is nested within another task.

13:12

IOPL

System

I/O Privilege Level: While executing in protected mode, IOPL indicates the maximum current
privilege level (CPL) permitted to execute I/O instructions without generating an exception 13
fault or consulting the I/O permission bit map. IOPL also indicates the maximum CPL allowing
alteration of the IF bit when new values are popped into the EFLAGS register.

Arithmetic

Overflow Flag: Set if the operation resulted in a carry or borrow into the sign bit of the result but
did not result in a carry or borrow out of the high-order bit. Also set if the operation resulted in a
carry or borrow out of the high-order bit but did not result in a carry or borrow into the sign bit of
the result.

Control

Direction Flag: When cleared, DF causes string instructions to auto-increment (default) the
appropriate index registers (ESI and/or EDI). Setting DF causes auto-decrement of the index
registers to occur.

System

Interrupt Enable Flag: When set, maskable interrupts (INTR input pin) are acknowledged and
serviced by the CPU.

Debug

Trap Enable Flag: Once set, a single-step interrupt occurs after the next instruction completes
execution. TF is cleared by the single-step interrupt.

Arithmetic

Sign Flag: Set equal to high-order bit of result (0 indicates positive, 1 indicates negative).

Arithmetic

Zero Flag: Set if result is zero; cleared otherwise.

RSVD

Reserved: Set to 0.

Arithmetic

Auxiliary Carry Flag: Set when a carry out of (addition) or borrow into (subtraction) bit position 3
of the result occurs; cleared otherwise.

RSVD

Reserved: Set to 0.

Arithmetic

Parity Flag: Set when the low-order 8 bits of the result contain an even number of ones; other-
wise PF is cleared.

RSVD

Reserved: Set to 1.

Arithmetic

Carry Flag: Set when a carry out of (addition) or borrow into (subtraction) the most significant bit
of the result occurs; cleared otherwise.

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

3.3.2

System Register Set

The System Register Set, shown in Table 3-5, consists of
registers not generally used by application programmers.
These registers are typically employed by system level
programmers who generate operating systems and mem-
ory management programs. Associated with the System
Register Set are certain tables and segments which are
listed in Table 3-5.

The Control Registers control certain aspects of the
GXLV processor such as paging, coprocessor functions,
and segment protection.

The Configuration Registers are used to define the
GXLV CPU setup including cache management.

The Debug Registers provide debugging facilities for the
GXLV processor and enable the use of data access
breakpoints and code execution breakpoints.

The Test Registers provide a mechanism to test the con-
tents of both the on-chip 16 KB cache and the Translation
Lookaside Buffer (TLB).

The Descriptor Table Register hold descriptors that
manage memory segments and tables, interrupts and
task switching. The tables are defined by corresponding
registers.

The two Task State Segment Tables defined by TSS reg-
ister are used to save and load the computer state when
switching tasks.

The ID Registers allow BIOS and other software to iden-
tify the specific CPU and stepping.

System Management Mode (SMM) control information is
stored in the SMM Registers.

Table 3-5 lists the system register sets along with their
size and function.

Table 3-5. System Register Set

Group

Name

Function

Width

(Bits)

Control
Registers

CR0

System Control
Register

CR2

Page Fault Linear
Address Register

CR3

Page Directory Base
Register

CR4

Time Stamp Counter

Configuration
Registers

CCRn

Configuration Control
Registers

Debug
Registers

DR0

Linear Breakpoint
Address 0

DR1

Linear Breakpoint
Address 1

DR2

Linear Breakpoint
Address 2

DR3

Linear Breakpoint
Address 3

DR6

Breakpoint Status

DR7

Breakpoint Control

Test
Registers

TR3

Cache Test

TR4

Cache Test

TR5

Cache Test

TR6

TLB Test Control

TR7

TLB Test Data

Descriptor
Tables

GDT

General Descriptor Table

IDT

Interrupt Descriptor
Table

LDT

Local Descriptor Table

Descriptor
Table
Registers

GDTR

GDT Register

IDTR

IDT Register

LDTR

LDT Register

Task State
Segment and
Registers

TSS

Task State Segment
Table

TSS Register Setup

ID
Registers

DIRn

Device Identification
Registers

SMM
Registers

SMARn

SMM Address Region
Registers

SMHRn

SMM Header Addresses

Performance
Registers

PCR0

Performance Control
Register

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

3.3.2.1

Control Registers

A map of the Control Registers (CR0, CR1, CR2, CR3,
and CR4) is shown in Table 3-6 and the bit definitions are
given in Table 3-7. (These registers should not be confused
with the CRRn registers.) CR0 contains system control bits
which configure operating modes and indicate the general
state of the CPU. The lower 16 bits of CR0 are referred to
as the Machine Status Word (MSW).

When operating in real mode, any program can read and
write the control registers. In protected mode, however,
only privilege level 0 (most-privileged) programs can read
and write these registers.

L1 Cache Controller
The GXLV processor contains an on-board 16 KB unified
data/instruction write-back L1 cache. With the memory
controller on-board, the L1 cache requires no external
logic to maintain coherency. All DMA cycles automatically
snoop the L1 cache.

The CD bit (Cache Disable, bit 30) in CR0 globally con-
trols the operating mode of the L1 cache. LCD and LWT,
Local Cache Disable and Local Write-through bits in the
Translation Lookaside Buffer, control the mode on a page-
by-page basis. Additionally, memory configuration control
can specify certain memory regions as non-cacheable.

If the cache is disabled, no further cache line fills occur.
However, data already present in the cache continues to
be used. For the cache to be completely disabled, the
cache must be invalidated with a WBINVD instruction
after the cache has been disabled.

Write-back caching improves performance by relieving
congestion on slower external buses. With four dirty bits,
the cache marks dirty locations on a double-word
(DWORD) basis. This further reduces the number of
DWORD write operations needed during a replacement or
flush operation.

The GXLV processor will cache SMM regions, reducing
system management overhead to allow for hardware
emulation such as VGA.

Table 3-6. Control Registers Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

CR4 Register

Control Register 4 (R/W)

RSVD

T
S

RSVD

CR3 Register

Control Register 3 (R/W)

PDBR (Page Directory Base Register)

RSVD

CR2 Register

Control Register 2 (R/W)

PFLA (Page Fault Linear Address)

CR1 Register

Control Register 1 (R/W)

RSVD

CR0 Register

Control Register 0 (R/W)

C
D

RSVD

R
S
V
D

RSVD

N
E

R
S
V
D

T
S

P
E

Machine Status Word (MSW)

Table 3-7. CR4-CR0 Bit Definitions

Bit

Name

Description

CR4 Register

Control Register 4 (R/W)

31:3

RSVD

Reserved: Set to 0 (always returns 0 when read).

TSC

Time Stamp Counter Instruction:
If = 1 RDTSC instruction enabled for CPL = 0 only; reset state.
If = 0 RDTSC instruction enabled for all CPL states.

1:0

RSVD

Reserved: Set to 0 (always returns 0 when read).

CR3 Register

Control Register 3 (R/W)

31:12

PDBR

Page Directory Base Register: Identifies page directory base address on a 4 KB page boundary.

11:0

RSVD

Reserved: Set to 0.

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

CR2 Register

Control Register 2 (R/W)

31:0

PFLA

Page Fault Linear Address: With paging enabled and after a page fault, PFLA contains the linear address of the
address that caused the page fault.

CR1 Register

Control Register 1 (R/W)

31:0

RSVD

Reserved

CR0 Register

Control Register 0 (R/W)

Paging Enable Bit: If PG = 1 and protected mode is enabled (PE = 1), paging is enabled. After changing the
state of PG, software must execute an unconditional branch instruction (e.g., JMP, CALL) to have the change
take effect.

Cache Disable: If CD = 1, no further cache line fills occur. However, data already present in the cache continues
to be used if the requested address hits in the cache. Writes continue to update the cache and cache invalida-
tions due to inquiry cycles occur normally. The cache must also be invalidated with a WBINVD instruction to com-
pletely disable any cache activity.

Not Write-Through: If NW = 1, the on-chip cache operates in write-back mode. In write-back mode, writes are
issued to the external bus only for a cache miss, a line replacement of a modified line, execution of a locked
instruction, or a line eviction as the result of a flush cycle. If NW = 0, the on-chip cache operates in write-through
mode. In write-through mode, all writes (including cache hits) are issued to the external bus. This bit cannot be
changed if LOCK_NW = 1 in CCR2.

28:19

RSVD

Reserved

Alignment Check Mask: If AM = 1, the AC bit in the EFLAGS register is unmasked and allowed to enable align-
ment check faults. Setting AM = 0 prevents AC faults from occurring.

RSVD

Reserved

Write Protect: Protects read-only pages from supervisor write access. WP = 0 allows a read-only page to be
written from privilege level 0-2. WP = 1 forces a fault on a write to a read-only page from any privilege level.

15:6

RSVD

Reserved

Numerics Exception: NE = 1 to allow FPU exceptions to be handled by interrupt 16. NE = 0 if FPU exceptions
are to be handled by external interrupts.

RSVD

Reserved: Do not attempt to modify, always 1.

Task Switched: Set whenever a task switch operation is performed. Execution of a floating point instruction with
TS = 1 causes a DNA fault. If MP = 1 and TS = 1, a WAIT instruction also causes a DNA fault.

Emulate Processor Extension: If EM = 1, all floating point instructions cause a DNA fault 7.

Monitor Processor Extension: If MP = 1 and TS = 1, a WAIT instruction causes Device Not Available (DNA)
fault 7. The TS bit is set to 1 on task switches by the CPU. Floating point instructions are not affected by the state
of the MP bit. The MP bit should be set to one during normal operations.

Protected Mode Enable: Enables the segment based protection mechanism. If PE = 1, protected mode is
enabled. If PE = 0, the CPU operates in real mode and addresses are formed as in an 8086-style CPU. Refer to
Section 3.9 "Protection" on page 91.

Table 3-7. CR4-CR0 Bit Definitions (Continued)

Bit

Name

Description

Table 3-8. Effects of Various Combinations of EM, TS, and MP Bits

CR0[3:1]

Instruction Type

WAIT

ESC

Execute

Fault 7

Execute

Fault 7

Execute

Fault 7

Execute

Fault 7

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

3.3.2.2

Configuration Registers

The Configuration Registers listed in Table 3-9 are CPU
registers and are selected by register index numbers. The
registers are accessed through I/O memory locations 22h
and 23h. Registers are selected for access by writing an
index number to I/O Port 22h using an OUT instruction
prior to transferring data through I/O Port 23h. This opera-
tion must be atomic. The CLI instruction must be executed
prior to accessing any of these registers.

Each data transfer through I/O Port 23h must be preceded
by a register index selection through I/O Port 22h; other-
wise, subsequent I/O Port 23h operations are directed off-
chip and produce external I/O cycles.

If MAPEN, bit 4 of CCR3 (Index C3h[4]) = 0, external I/O
cycles occur if the register index number is outside the
range C0h-CFh, FEh, and FFh. The MAPEN bit should
remain 0 during normal operation to allow system regis-
ters located at I/O Port 22h to be accessed (see Table 3-
11 on page 52).

Table 3-9. Configuration Register Summary

Index

Type

Name

Access

Controlled By*

Default

Value

Reference

(Bit Formats)

C1h

R/W

CCR1 -- Configuration Control 1

SMI_LOCK

00h

Table 3-11 on page 52

C2h

R/W

CCR2 -- Configuration Control 2

00h

Table 3-11 on page 52

C3h

R/W

CCR3 -- Configuration Control 3

SMI_LOCK

00h

Table 3-11 on page 52

E8h

R/W

CCR4 -- Configuration Control 4

MAPEN

85h

Table 3-11 on page 53

EBh

R/W

CCR7 -- Configuration Control 7

00h

Table 3-11 on page 53

20h

R/W

PCR -- Performance Control

MAPEN

07h

Table 3-11 on page 53

B0h

R/W

SMHR0 -- SMM Header Address 0

MAPEN

xxh

Table 3-11 on page 54

B1h

R/W

SMHR1 -- SMM Header Address 1

MAPEN

xxh

Table 3-11 on page 54

B2h

R/W

SMHR2 -- SMM Header Address 2

MAPEN

xxh

Table 3-11 on page 54

B3h

R/W

SMHR3 -- SMM Header Address 3

MAPEN

xxh

Table 3-11 on page 54

B8h

R/W

GCR -- Graphics Control Register

MAPEN

00h

Table 4-1 on page 97

B9h

R/W

VGACTL -- VGA Control Register

00h

Table 4-37 on page 163

BAh-BDh

R/W

VGAM0 -- VGA Mask Register

00h

Table 4-37 on page 163

CDh

R/W

SMAR0 -- SMM Address 0

SMI_LOCK

00h

Table 3-11 on page 54

CEh

R/W

SMAR1 -- SMM Address 1

SMI_LOCK

00h

Table 3-11 on page 54

CFh

R/W

SMAR2 -- SMM Address 2

SMI_LOCK

00h

Table 3-11 on page 54

FEh

DIR0 -- Device ID 0

4xh

Table 3-11 on page 54

FFh

DIR1 -- Device ID 1

xxh

Table 3-11 on page 54

Note:

*MAPEN = Index C3h[4] (CCR3) and SMI_LOCK = Index C3h[0] (CCR3).

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

Table 3-10. Configuration Register Map

Register

(Index)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Control Registers

CCR1 (C1h)

RSVD

SMAC

USE_SMI

RSVD

CCR2 (C2h)

USE_SUSP

RSVD

WT1

SUSP_HLT

LOCK_NW

RSVD

CCR3 (C3h)

LSS_34

LSS_23

LSS_12

MAPEN

SUSP_SMM

_EN

RSVD

NMI_EN

SMI_LOCK

CCR4 (E8h)

CPUID

SMI_NEST

FPU_FAST_

DTE_EN

MEM_BYP

IORT2

IORT1

IORT0

CCR7 (EBh)

RSVD

NMI

RSVD

EMMX

PCR (20h)

LSSER

RSVD

SMM Base Header Address Registers

SMHR0 (B0h)

SMHR1 (B1h)

A15

A14

A13

A12

A11

A10

SMHR2 (B2h)

A23

A22

A21

A20

A19

A18

A17

A16

SMHR3 (B3h)

A31

A30

A29

A28

A27

A26

A24

SMAR0 (CDh)

A31

A30

A29

A28

A27

A26

A25

A24

SMAR1 (CEh)

A23

A22

A21

A20

A19

A18

A17

A16

SMAR2 (CFh)

A15

A14

A13

A12

SIZE3

SIZE2

SIZE1

SIZE0

Device ID Registers

DIR0 (FEh)

DID3

DID2

DID1

DID0

MULT3

MULT2

MULT1

MULT0

DIR1 (FFh)

SID3

SID2

SID1

SID0

RID3

RID2

RID1

RID0

Graphics/VGA Related Registers

GCR (B8h)

RSVD

Scratchpad Size

Base Address Code

VGACTL (B9h)

RSVD

Enable SMI

for VGA

memory

B8000h to

BFFFFh

Enable SMI

for VGA

memory

B0000h to

B7FFFh

Enable SMI

for VGA

memory

A0000h to

AFFFFh

VGAM0 (BAh)

VGA Mask Register Bits [7:0]

VGAM1 (BBh)

VGA Mask Register Bits [15:8]

VGAM2 (BCh)

VGA Mask Register Bits [23:16]

VGAM3 (BDh)

VGA Mask Register Bits [31:24]

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

Table 3-11. Configuration Registers

Bit

Name

Description

Index C1h

CCR1 -- Configuration Control Register 1 (R/W)

Default Value = 00h

7:3

RSVD

Reserved: Set to 0.

2:1

SMAC

System Management Memory Access:

If = 00: SMM is disabled.
If = 01: SMI# pin is active to enter SMM. SMINT instruction is inactive.
If = 10: SMM is disabled.
If = 11: SMINT instruction is active to enter SMM. SMI# pin is inactive.

Note: SMI_LOCK (CCR3[0]) must = 0, or the CPU must be in SMI mode, to write this bit.

RSVD

Reserved: Set to 0.

Note: Bits 1 and 2 are cleared to zero at reset.

Index C2h

CCR2 -- Configuration Control Register 2 (R/W)

Default Value = 00h

USE_SUSP

Enable Suspend Pins:

If = 1: SUSP# input and SUSPA# output are enabled.
If = 0: SUSP# input is ignored.

RSVD

Reserved: This is a test bit that must be set to 0.

RSVD

Reserved: Set to 0.

WT1

Write-Through Region 1:

If = 1: Forces all writes to the address region between 640 KB to 1 MB that hit in the on-chip cache to
be issued on the external bus.

SUSP_HLT

Suspend on HALT:

If = 1: CPU enters Suspend mode following execution of a HALT instruction.

LOCK_NW

Lock NW Bit:

If = 1: Prohibits changing the state of the NW bit (CR0[29]) (refer to Table 3-7 on page 49).
Set to 1 after setting NW.

1:0

RSVD

Reserved: Set to 0.

Note: All bits are cleared to zero at reset.

Index C3h

CCR3 -- Configuration Control Register 3 (R/W)

Default Value = 00h

LSS_34

Load/Store Serialize 3 GB to 4 GB:

If = 1: Strong R/W ordering imposed in address range C0000000h to FFFFFFFFh.

LSS_23

Load/Store Serialize 2 GB to 3 GB:

If = 1: Strong R/W ordering imposed in address range 80000000h to BFFFFFFFh.

LSS_12

Load/Store Serialize 1 GB to 2 GB:

If = 1: Strong R/W ordering imposed in address range 40000000h to 7FFFFFFFh.

MAPEN

Map Enable:

If = 1: All configuration registers are accessible. All accesses to I/O Port 22h are trapped.
If = 0: Only configuration registers Index C1h-C3h, CDh-CFh FEh, FFh (CCRn, SMAR, DIRn) are
accessible. Other configuration registers (including PCR, SMHRn, GCR, VGACTL, VGAM0) are not
accessible.

SUSP_SMM_EN

Enable Suspend in SMM Mode:

If 0 = SUSP# ignored in SMM mode.
If 1 = SUSP# recognized in SMM mode.

RSVD

Reserved: Set to 0.

NMI_EN

NMI Enable:

If = 1: NMI is enabled during SMM.
If = 0: NMI is not recognized during SMM.

Note: SMI_LOCK (CCR3[0]) must = 0 or the CPU must be in SMI mode to write to this bit.

SMI_LOCK

SMM Register Lock:

If = 1: SMM Address Region Register (SMAR[31:0]), SMAC (CCR1[2]), USE_SMI (CCR1[1])
cannot be modified unless in SMM routine. Once set, SMI_LOCK can only be cleared by asserting
the RESET pin.

Note: All bits are cleared to zero at reset.

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

Index E8h

CCR4 -- Configuration Control Register 4 (R/W)

Default Value = 85h

CPUID

Enable CPUID Instruction:

If = 1: The ID bit in the EFLAGS register to be modified and execution of the CPUID instruction occurs
as documented in Section 7.2 "CPUID Instruction" on page 212.
If = 0: The ID bit can not be modified and execution of the CPUID instruction causes an invalid opcode
exception.

SMI_NEST

SMI Nest:

If = 1: SMI interrupts can occur during SMM mode. SMM service routines can optionally set
SMI_NEST high to allow higher-priority SMI interrupts while handling the current event

FPU_FAST_EN

FPU Fast Mode Enable:

If = 0: Disable FPU Fast Mode
If = 1: Enable FPU Fast Mode.

DTE_EN

Directory Table Entry Cache:

If = 1: Enables directory table entry to be cached.

Cleared to 0 at reset.

MEM_BYP

Memory Read Bypassing:

If = 1: Enables memory read bypassing.

Cleared to 0 at reset.

2:0

IORT(2:0)

I/O Recovery Time: Specifies the minimum number of bus clocks between I/O accesses:

000 = No clock delay

100 = 16-clock delay

001 = 2-clock delay

101 = 32-clock delay (default value after reset)

010 = 4-clock delay

110 = 64-clock delay

011 = 8-clock delay

111 = 128-clock delay

Note: MAPEN (CCR3[4]) must = 1 to read or write this register.

Index EBh

CCR7 -- Configuration Control Register 7 (R/W)

Default Value = 00h

7:3

RSVD

Reserved: Set to 0.

NMI

Generate NMI:

If 0 = Do nothing
If 1 = Generate NMI

In order to generate multiple NMIs, this bit must be set to zero between each setting of 1.

RSVD

Reserved: Set to 0.

EMMX

Extended MMX Instructions Enable:

If = 1: Extended MMX instructions are enabled

Index 20h

PCR -- Performance Control Register (R/W)

Default Value = 07h

LSSER

Load/Store Serialize Enable (Reorder Disable): LSSER should be set to ensure that memory
mapped I/O devices operating outside of the address range 640 KB to 1 MB will operate correctly. For
memory accesses above 1 GByte, refer to CCR3[7:5] (LSS_34, LSS_23, LSS_12.)

If = 1: All memory read and write operations will occur in execution order (load/store serializing
enabled, reordering disabled).

If = 0: Memory reads and write can be reordered for optimum performance (load/store serializing dis-
abled, reordering enabled).

Memory accesses in the address range 640 KB to 1 MB will always be issued in execution order.

RSVD

Reserved: Set to 0.

RSVD

Reserved: Set to 1.

4:0

RSVD

Reserved: Set to 0.

Note: MAPEN (CCR3[4]) must = 1 to read or write this register.

Table 3-11. Configuration Registers (Continued)

Bit

Name

Description

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

Index B0h, B1h, B2h, B3h

SMHR -- SMM Header Address Register (R/W)

Default Value = xxh

Index

SMHR Bits

SMM Header Address Bits [31:0]: SMHR address bits [31:0] contain the physical base address for
the SMM header space. For example, bits [31:24] correspond with Index B3h. Refer to Section 3.7.3
"SMM Configuration Registers" on page 85 for more information.

B3h
B2h
B1h
B0h

A[31:24]
A[23:16]
A[15:12]

A[7:0]

Note: MAPEN (CCR3[4]) must = 1 to read or write to this register.

Index CDh, CEh, CFh

SMAR -- SMM Address Region/Size Register (R/W)

Default Value = 00h

Index

SMAR Bits

SMM Address Region Bits [A31:A12]: SMAR address bits [31:12] contain the base address for the
SMM region. For example, bits [31:24] correspond with index CDh. Refer to Section 3.7.3 "SMM Con-
figuration Registers" on page 85 for more information.

CDh
CEh

CFh[7:4]

A[31:24]
A[23:16]
A[15:12]

CFh[3:0]

SIZE[3:0]

SMM Region Size Bits [3:0]: SIZE address bits contain the size code for the SMM region. During
access the lower 4-bits of Port 23h hold SIZE[3:0]. Index CFh allows simultaneous access to SMAR
address regions bits A[15:12] (see above) and size code bits SIZE[3:0].

0000 = SMM Disabled

0100 = 32 KB

1000 = 512 KB

1100 = 8 MB

0001 = 4 KB

0101 = 64 KB

1001 = 1 MB

1101 = 16 MB

0010 = 8 KB

0110 = 128 KB

1010 = 2 MB

1110 = 32 MB

0011 = 16 KB

0111 = 256 KB

1011 = 4 MB

1111 = 4 KB (same as 0001)

Notes:

SMI_LOCK (CCR3[0]) must = 0, or the CPU must be in SMI mode, to write these registers/bits.

Refer to Section 3.7.3 "SMM Configuration Registers" on page 85 for more information.

Index FEh

DIR0 -- Device Identification Register 0 (RO)

Default Value = 4xh

7:4

DID[3:0]

Device ID (Read Only): Identifies device as GXLV processor.

3:0

MULT[3:0]

Core Multiplier (Read Only): Identifies the core multiplier set by the CLKMODE[2:0] pins (see signal
descriptions page 31)

MULT[3:0]:
0000 = SYSCLK multiplied by 4 (Test mode only)
0001 = SYSCLK multiplied by 10
0010 = SYSCLK multiplied by 4
0011 = SYSCLK multiplied by 6
0100 = SYSCLK multiplied by 9
0101 = SYSCLK multiplied by 5
0110 = SYSCLK multiplied by 7
0111 = SYSCLK multiplied by 8
1xxx = Reserved

Index FFh

DIR1 -- Device Identification Register 1 (RO)

Default Value = xxh

7:0

DIR1

Device Identification Revision (Read Only): DIR1 indicates device revision number.

If DIR1 is 6xh = GXLV processor.

Table 3-11. Configuration Registers (Continued)

Bit

Name

Description

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

3.3.2.3

Debug Registers

Six debug registers (DR0-DR3, DR6 and DR7) support
debugging on the GXLV processor. Memory addresses
loaded in the debug registers, referred to as "breakpoints,"
generate a debug exception when a memory access of
the specified type occurs to the specified address. A
breakpoint can be specified for a particular kind of mem-
ory access such as a read or write operation. Code and
data breakpoints can also be set allowing debug excep-
tions to occur whenever a given data access (read or write
operation) or code access (execute) occurs. The size of
the debug target can be set to 1, 2, or 4 bytes. The debug
registers are accessed through MOV instructions that can
be executed only at privilege level 0 (real mode is always
privilege level 0).

The Debug Address Registers (DR0-DR3) each contain
the linear address for one of four possible breakpoints.
Each breakpoint is further specified by bits in the Debug
Control Register (DR7). For each breakpoint address in
DR0-DR3, there are corresponding fields L, R/W, and
LEN in DR7 that specify the type of memory access asso-
ciated with the breakpoint. DR6 is read only and reports
the results of the break.

The R/W field can be used to specify instruction execution
as well as data access breakpoints. Instruction execution
breakpoints are always acted upon before execution of
the instruction that matches the breakpoint. The Debug
Registers are mapped in Table 3-12, and the bit defini-
tions are given in Table 3-13 on page 56.

Table 3-12. Debug Registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DR7 Register

Debug Control Register 7 (R/W)

LEN3

R/W3

LEN2

R/W2

LEN1

R/W1

LEN0

R/W0

L
3

L
2

L
1

DR6 Register

Debug Status Register 6 (R/O)

B
T

B
S

B3 B2 B1 B0

DR3 Register

Debug Address Register 3 (R/W)

Breakpoint 3 Linear Address

DR2 Register

Debug Address Register 2 (R/W)

Breakpoint 2 Linear Address

DR1 Register

Debug Address Register 1 (R/W)

Breakpoint 1 Linear Address

DR0 Register

Debug Address Register 0 (R/W)

Breakpoint 0 Linear Address

Note: All bits marked as 0 or 1 are reserved and should not be modified.

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

The Debug Status Register (DR6) reflects conditions that
were in effect at the time the debug exception occurred.
The contents of the DR6 register are not automatically
cleared by the processor after a debug exception occurs,
and therefore should be cleared by software at the appro-
priate time. Code execution breakpoints may also be gen-

erated by placing the breakpoint instruction (INT3) at the
location where control is to be regained. The single-step
feature may be enabled by setting the TF flag (bit 8) in the
EFLAGS register. This causes the processor to perform a
debug exception after the execution of every instruction.

Table 3-13. DR7 and DR6 Bit Definitions

Field(s)

Number

of Bits

Description

DR7 Register

Debug Control Register (R/W)

R/Wn

Applies to the DRn breakpoint address register:

00 = Break on instruction execution only
01 = Break on data write operations only
10 = Not used
11 = Break on data reads or write operations

LENn

Applies to the DRn breakpoint address register:

00 = One-byte length
01 = Two-byte length
10 = Not used
11 = Four-byte length

If = 1: Breakpoint in DRn is globally enabled for all tasks and is not cleared by the processor as the
result of a task switch.

If = 1: Breakpoint in DRn is locally enabled for the current task and is cleared by the processor as the
result of a task switch.

Global disable of debug register access. GD bit is cleared whenever a debug exception occurs.

DR6 Register

Debug Status Register (RO)

Bn is set by the processor if the conditions described by DRn, R/Wn, and LENn occurred when the
debug exception occurred, even if the breakpoint is not enabled via the Gn or Ln bits.

BT is set by the processor before entering the debug handler if a task switch has occurred to a task with
the T bit in the TSS set.

BS is set by the processor if the debug exception was triggered by the single-step execution mode (TF
flag, bit 8, in EFLAGS set).

Note: n = 0, 1, 2, and 3

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

3.3.2.4

TLB Test Registers

Two test registers are used in testing the processor's
Translation Lookaside Buffer (TLB), TR6 and TR7. Table 3-
14 is a register map for the TLB Test Registers with their bit
definitions given in Table 3-15 on page 58. The test regis-
ters are accessed through MOV instructions that can be
executed only at privilege level 0 (real mode is always
privilege level 0).

The CPU TLB is a 32-entry, four-way set associative
memory. Each TLB entry consists of a 24-bit tag and 20-
bit data. The 24-bit tag represents the high-order 20 bits
of the linear address, a valid bit, and three attribute bits.
The 20-bit data portion represents the upper 20 bits of the
physical address that corresponds to the linear address.

The TLB Test Control Register (TR6) contains a com-
mand bit, the upper 20 bits of a linear address, a valid bit
and the attribute bits used in the test operation. The con-
tents of TR6 are used to create the 24-bit TLB tag during
both write and read (TLB lookup) test operations. The
command bit defines whether the test operation is a read
or a write.

The TLB Test Data Register (TR7) contains the upper 20
bits of the physical address (TLB data field), three LRU
bits, two replacement (REP) bits, and a control bit (PL).
During TLB write operations, the physical address in TR7
is written into the TLB entry selected by the contents of
TR6. During TLB lookup operations, the TLB data
selected by the contents of TR6 is loaded into TR7. Table
3-15 lists the bit definitions for TR7 and TR6.

Table 3-14. TLB Test Registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

TR7 Register

TLB Test Data Register (R/W)

Physical Address

TLB LRU

REP

TR6 Register

TLB Test Control Register (R/W)

Linear Address

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

Table 3-15. TR7-TR6 Bit Definitions

Bit

Name

Description

TR7 Register

TLB Test Data Register (R/W)

31:12

Physical
Address

Physical Address:

TLB lookup: Data field from the TLB.

TLB write: Data field written into the TLB.

11:10

RSVD

Reserved: Set to 0.

9:7

TLB LRU

LRU Bits:

TLB lookup: LRU bits associated with the TLB entry before the TLB lookup.

TLB write: Ignored.

6:5

RSVD

Reserved: Set to 0.

PL Bit:

TLB lookup: If PL = 1, read hit occurred. If PL = 0, read miss occurred.

TLB write: If PL = 1, REP field is used to select the set. If PL = 0, the pseudo-LRU replacement algorithm
is used to select the set.

3:2

REP

Set Selection:

TLB lookup: If PL = 1, this field indicates the set in which the tag was found. If PL = 0, undefined data.

TLB write: If PL = 1, this field selects one of the four sets for replacement. If PL = 0, ignored.

1:0

RSVD

Reserved: Set to 0.

TR6 Register

TLB Test Control Register (R/W)

31:12

Linear

Address

Linear Address:

TLB lookup: The TLB is interrogated per this address. If one and only one match occurs in the TLB, the
rest of the fields in TR6 and TR7 are updated per the matching TLB entry.

TLB write: A TLB entry is allocated to this linear address.

Valid Bit:

TLB write: If V = 1, the TLB entry contains valid data. If V = 0, target entry is invalidated.

10:9

8:7
6:5

D, D#
U, U#

R, R#

Dirty Attribute Bit and its Complement (D, D#):
User/Supervisor Attribute Bit and its Complement (U, U#):
Read/Write Attribute Bit and its Complement (R, R#):

Effect on TLB Lookup

Effect on TLB Write

00 =

Do not match

Undefined

01 =

Match if D, U, or R bit is a 0

Clear the bit

10 =

Match if D, U, or R bit is a 1

Set the bit

11 =

Match if D, U, or R bit is either a 1 or 0

Undefined

4:1

RSVD

Reserved: Set to 0.

Command Bit:

If C = 1: TLB lookup.
If C = 0: TLB write.

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

3.3.2.5

Cache Test Registers

Three test registers are used in testing the processor's on-
chip cache, TR3-TR5. Table 3-16 is a register map for the
Cache Test Registers with their bit definitions given in Table
3-17 on page 60. The test registers are accessed through
MOV instructions that can be executed only at privilege
level 0 (real mode is always privilege level 0).

The processor's 16 KB on-chip cache is a four-way set
associative memory that is configured as write-back
cache. Each cache set contains 256 entries. Each entry
consists of a 20-bit tag address, a 16-byte data field, a
valid bit, and four dirty bits.

The 20-bit tag represents the high-order 20 bits of the
physical address. The 16-byte data represents the 16
bytes of data currently in memory at the physical address

represented by the tag. The valid bit indicates whether the
data bytes in the cache actually contain valid data. The
four dirty bits indicate if the data bytes in the cache have
been modified internally without updating external mem-
ory (write-back configuration). Each dirty bit indicates the
status for one DWORD (4 bytes) within the 16-byte data
field.

For each line in the cache, there are three LRU bits that
indicate which of the four sets was most recently
accessed. A line is selected using bits [11:4] of the physi-
cal address. Using a 16-byte cache fill buffer and a 16-
byte cache flush buffer, cache reads and writes may be
performed.

Figure 3-1 illustrates the internal cache architecture.

Figure 3-1. Cache Architecture

D
E
C
O
D
E

255

254

.
.
0

A11-A4

Line

Address

= Cache Entry (153 bits)

Tag Address (20 bits)
Data (128 bits)
Valid Status (1 bit)
Dirty Status (4 bits)

Set 0

Set 1

Set 2

Set 3

LRU

.
.

152 --- 0

2 --- 0

Table 3-16. Cache Test Registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

TR5 Register (R/W)

RSVD

Line Selection

Set/

DWORD

Control

Bits

TR4 Register - Cache (R/W)

Cache Tag Address

l
i
d

Cache

LRU Bits

Dirty Bits

TR3 Register - Cache (R/W)

Cache Data

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

Table 3-17. TR5-TR3 Bit Definitions

Bit

Name

Description

TR5 Register (R/W)

31:12

RSVD

Reserved

11:4

Line Selection

Line Selection:

Physical address bits [11:4] used to select one of 256 lines.

3:2

Set/DWORD

Selection

Set/DWORD Selection:

Cache read: Selects which of the four sets in the cache is used as the source for data
transferred to the cache flush buffer.

Cache write: Selects which of the four sets in the cache is used as the destination for data transferred
from the cache fill buffer.

Flush buffer read: Selects which of the four DWORDs in the flush buffer is used during a TR3 read.

Fill buffer write: Selects which of the four DWORDs in the fill buffer is written during a TR3 write.

1:0

Control Bits

Control Bits:

00 = Flush read or fill buffer write.
01 = Cache write.
10 = Cache read.
11 = Cache flush.

TR4 Register (R/W)

31:12

Upper Tag

Address

Upper Tag Address:

Cache read: Upper 20 bits of tag address of the selected entry.

Cache write: Data written into the upper 20 bits of the tag address of the selected entry.

Valid Bit

Valid Bit:

Cache read: Valid bit for the selected entry.

Cache write: Data written into the valid bit for the selected entry.

9:7

LRU Bits

LRU Bits:

Cache read: The LRU bits for the selected line when scratchpad is disabled.
xx1 = Set 0 or Set 1 most recently accessed.
xx0 = Set 2 or Set 3 most recently accessed.
x1x = Most recent access to Set 0 or Set 1 was to Set 0.
x0x = Most recent access to Set 0 or Set 1 was to Set 1.
1xx = Most recent access to Set 2 or Set 3 was to Set 2.
0xx = Most recent access to Set 2 or Set 3 was to Set 3.

Cache write: Ignored.

6:3

Dirty Bits

Dirty Bits:

Cache read: The dirty bits for the selected entry (one bit per DWORD).

Cache write: Data written into the dirty bits for the selected entry.

2:0

RSVD

Reserved: Set to 0.

TR3 Register (R/W)

31:0

Cache Data

Cache Data:

Flush buffer read: Data accessed from the cache flush buffer.

Fill buffer write: Data to be written into the cache fill buffer.

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

There are five types of test operations that can be exe-
cuted:

· Flush buffer read
· Fill buffer write
· Cache write
· Cache read
· Cache flush

These operations are described in detail in Table 3-18. To
fill a cache line with data, the fill buffer must be written four

times. Once the fill buffer holds a complete cache line of
data (16 bytes), a cache write operation transfers the data
from the fill buffer to the cache.

To read the contents of a cache line, a cache read opera-
tion transfers the data in the selected cache line to the
flush buffer. Once the flush buffer is loaded, access the
contents of the flush buffer with four flush buffer read
operations.

Table 3-18. Cache Test Operations

Test Operation

Code Sequence

Action Taken

Flush Buffer Read

MOV TR5, 0h

MOV dest,TR3

Set DWORD = 0, control = 00 = flush buffer read.

Flush buffer (31:0) --> dest.

MOV TR5, 4h

MOV dest,TR3

Set DWORD = 1, control = 00 = flush buffer read.

Flush buffer (63:32) --> dest.

MOV TR5, 8h

MOV dest,TR3

Set DWORD = 2, control = 00 = flush buffer read.

Flush buffer (95:64) --> dest.

MOV TR5, Ch

MOV dest,TR3

Set DWORD = 3, control = 00 = flush buffer read.

Flush buffer (127:96) --> dest.

Fill Buffer Write

MOV TR5, 0h

MOV TR3, cache_data

Set DWORD = 0, control = 00 = fill buffer write.

Cache_data --> fill buffer (31:0).

MOV TR5, 4h

MOV TR3, cache_data

Set DWORD = 1, control = 00 = fill buffer write.

Cache_data --> fill buffer (63:32).

MOV TR5, 8h

MOV TR3, cache_data

Set DWORD = 2, control = 00 = fill buffer write.

Cache_data --> fill buffer (95:64).

MOV TR5, Ch

MOV TR3, cache_data

Set DWORD = 3, control = 00 = fill buffer write.

Cache_data --> fill buffer (127:96).

Cache Write

MOV TR4, cache_tag

Cache_tag --> tag address, valid and dirty bits.

MOV TR5, line+set+control=01

Fill buffer (127:0) --> cache line (127:0).

Cache Read

MOV TR5, line+set+control=10

MOV dest, TR4

Cache line (127:0) --> flush buffer (127:0).

Cache line tag address, valid/LRU/dirty bits --> dest.

Cache Flush

MOV TR5, 3h

Control = 11 = cache flush, all cache valid bits = 0.

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

3.3.3

Model Specific Register Set

The Model Specific Register (MSR) Set is used to monitor
the performance of the processor or a specific component
within the processor.

A MSR can be read using the RDMSR instruction, opcode
0F32h. During a MSR read, the contents of the particular
MSR, specified by the ECX register, is loaded into the
EDX:EAX registers.

A MSR can be written using the WRMSR instruction,
opcode 0F30h. During a MSR write, the contents of
EDX:EAX are loaded into the MSR specified in the ECX
register.

The RDMSR and WRMSR instructions are privileged
instructions.

The GXLV processor contains one 64-bit model specific
register (MSR10) the Time Stamp Counter (TSC).

3.3.4

Time Stamp Counter

The TSC, (MSR[10]), is a 64-bit counter that counts the
internal CPU clock cycles since the last reset. The TSC
uses a continuous CPU core clock and will continue to
count clock cycles unless the processor is in Suspend.

The TSC is read using a RDMSR instruction, opcode
0F32h, with the ECX register set to 10h. During a TSC
read, the contents of the TSC is loaded into the EDX:EAX
registers.

The TSC is written to using a WRMSR instruction, opcode
0F30h with the ECX register set to 10h. During a TSC
write, the contents of EDX:EAX are loaded into the TSC.

The RDMSR and WRMSR instructions are privileged
instructions.

In addition, the TSC can be read using the RDTSC
instruction, opcode 0F31h. The RDTSC instruction loads
the contents of the TSC into EDX:EAX. The use of the
RDTSC instruction is restricted by the TSC flag (bit 2) in
the CR4 register (refer to Tables 3-6 and 3-7 on page 48
for CR4 register information). When the TSC bit = 0, the
RDTSC instruction can be executed at any privilege level.
When the TSC bit = 1, the RDTSC instruction can only be
executed at privilege level 0.

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

3.4

ADDRESS SPACES

The GXLV processor can directly address either memory
or I/O space. Figure 3-2 illustrates the range of addresses
available for memory address space and I/O address
space. For the CPU, the addresses for physical memory
range between 0000 0000h and FFFFFFFFh (4 GB).
The accessible I/O address space ranges between
00000000h and 0000FFFFh (64 KB). The CPU does not
use coprocessor communication space in upper I/O space
between 8000 00F8h and 8000 00FFh as do the 386-style
CPUs. The I/O locations 22h and 23h are used for GXLV
processor configuration register access.

3.4.1

I/O Address Space

The CPU I/O address space is accessed using IN and
OUT instructions to addresses referred to as "ports." The
accessible I/O address space is 64 KB and can be
accessed as 8-, 16- or 32-bit ports.

The GXLV processor configuration registers reside within
the I/O address space at port addresses 22h and 23h and
are accessed using the standard IN and OUT instructions.

The configuration registers are modified by writing the
index of the configuration register to Port 22h, and then
transferring the data through Port 23h. Accesses to the
on-chip configuration registers do not generate external
I/O cycles. However, each operation on Port 23h must be
preceded by a write to Port 22h with a valid index value.
Otherwise, subsequent Port 23h operations will communi-
cate through the I/O port to produce external I/O cycles with-
out modifying the on-chip configuration registers. Write
operations to port 22h outside of the CPU index range
(C0h-CFh and FEh-FFh) result in external I/O cycles and
do not affect the on-chip configuration registers. Reading
Port 22h generates external I/O cycles.

I/O accesses to port address range 3B0h through 3DFh
can be trapped to SMI by the CPU if this option is enabled
in the BC_XMAP_1 register (see SMIB, SMIC, and SMID
bits in Table 4-9 on page 104). Figure 3-2 illustrates the
I/O address space.

Figure 3-2. Memory and I/O Address Spaces

Physical

Memory Space

Accessible

Programmed

I/O Space

FFFFFFFFh

0000FFFFh

00000000h

FFFFFFFFh

00000000h

Physical Memory

4 GB

Not

Accessible

64 KB

CPU General
Configuration
Register I/O
Space

00000023h
00000022h

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

3.4.2

Memory Address Space

The processor directly addresses up to 4 GB of physical
memory even though the memory controller addresses
only 256 MB of DRAM. Memory address space is
accessed as BYTES, WORDS (16 bits) or DWORDs (32
bits). WORDS and DWORDs are stored in consecutive
memory bytes with the low-order byte located in the low-
est address. The physical address of a WORD or DWORD
is the byte address of the low-order byte.

The processor allows memory to be addressed using nine
different addressing modes. These addressing modes are
used to calculate an offset address, often referred to as an
effective address. Depending on the operating mode of
the CPU, the offset is then combined, using memory man-
agement mechanisms, into a physical address that is
applied to the physical memory devices.

Memory management mechanisms consist of segmenta-
tion and paging. Segmentation allows each program to
use several independent, protected address spaces. Pag-
ing translates a logical address into a physical address
using translation lookup tables. Virtual memory is often
implemented using paging. Either or both of these mecha-
nisms can be used for management of the GXLV proces-
sor memory address space.

3.5

OFFSET, SEGMENT, AND PAGING

MECHANISMS

The mapping of address space into a sequence of mem-
ory locations (often cached) is performed by the offset,
segment, and paging mechanisms.

In general, the offset, segment and paging mechanisms
work in tandem as shown below:

instruction offset

offset mechanism

offset address

segment mechanism

linear address

paging mechanism

physical page.

As will be explained, the actual operations depend on sev-
eral factors such as the current operating mode and if
paging is enabled.

Note:

The paging mechanism uses part of the linear
address as an offset on the physical page.

3.5.1

Offset Mechanism

In all operating modes, the offset mechanism computes
an offset (effective) address by adding together up to
three values: a base, an index and a displacement. The
base, if present, is the value in one of eight general regis-
ters at the time of the execution of the instruction. The
index, like the base, is a value that is contained in one of
the general registers (except the ESP register) when the
instruction is executed. The index differs from the base in
that the index is first multiplied by a scale factor of 1, 2, 4
or 8 before the summation is made. The third component
added to the memory address calculation is the displace-
ment that is a value supplied as part of the instruction.
Figure 3-3 illustrates the calculation of the offset address.

Nine valid combinations of the base, index, scale factor
and displacement can be used with the CPU instruction
set. These combinations are listed in Table 3-19. The
base and index both refer to contents of a register as indi-
cated by [Base] and [Index].

In real mode operation, the CPU only addresses the low-
est 1 MB of memory and the offset contains 16-bits. In
protected mode the offset contains 32 bits. Initialization
and transition to protected mode is described in Section
3.9.4 "Initialization and Transition to Protected Mode" on
page 93.

Figure 3-3. Offset Address Calculation

Index

Base

Displacement

Scaling

x1, x2, x4, x8

Offset Address
(Effective Address)

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

3.5.2

Segment Mechanisms

Memory is divided into contiguous regions called "seg-
ments." The segments allow the partitioning of individual
elements of a program. Each segment provides a zero
address-based private memory for such elements as
code, data, and stack space.

The segment mechanisms select a segment in memory.
Memory is divided into an arbitrary number of segments,
each containing usually much less than the 2

byte (4

GB) maximum.

There are two segment mechanisms, one for real and vir-
tual 8086 operating modes, and one for protected mode.

3.5.2.1

Real Mode Segment Mechanism

In real mode operation, the CPU addresses only the low-
est 1 MB of memory. In this mode a selector located in
one of the segment registers is used to locate a segment.

To calculate a physical memory address, the 16-bit seg-
ment base address located in the selected segment regis-
ter is multiplied by 16 and then a 16-bit offset address is
added. The resulting 20-bit address is then extended with
twelve zeros in the upper address bits to create a 32-bit
physical address.

The value of the selector (the INDEX field) is multiplied by
16 to produce a base address (see Figure 3-4). The base
address is summed with the instruction offset value to pro-
duce a physical address.

3.5.2.2

Virtual 8086 Mode Segment Mechanism

In virtual 8086 mode the operation is performed as in real
mode except that a paging mechanism is added. When
paging is enabled, the paging mechanism translates the
linear address into a physical address using cached look-
up tables (refer to Section 3.5.4 "Paging Mechanism" on
page 77).

Figure 3-4. Real Mode Address Calculation

Offset Mechanism

Selected Segment

Offset Address

000h

X 16

Linear Address

(Physical Address)

Base Address

12 High Order Address Bits

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

3.5.2.3

Segment Mechanism in Protected Mode

The segment mechanism in protected mode is more com-
plex. Basically as in real and virtual 8086 modes the offset
address is added to the segment base address to pro-
duce a linear address (Figure 3-5). However, the calcula-
tion of the segment base address is based on the
contents of descriptor tables.

If paging is enabled the linear address is further pro-
cessed by the paging mechanism.

A more detailed look at the segment mechanisms for real
and virtual 8086 modes and protected modes is illustrated
in Figure 3-6 on page 68. In protected mode, the segment
selector is cached. This is illustrated in Figure 3-7 on page
69.

3.5.2.4

Segment Selectors

The segment registers are used to store segment selec-
tors. In protected mode, the segment selectors are

divided in to three fields: the RPL, TI and INDEX fields as
shown in Figure 3-6 on page 68.

The segments are assigned permission levels to prevent
application program errors from disrupting operating pro-
grams. The Requested Privilege Level (RPL) determines
the effective privilege level of an instruction. RPL = 0 indi-
cates the most privileged level, and RPL = 3 indicates the
least privileged level. Refer to Section 3.9 "Protection" on
page 91.

Descriptor tables hold descriptors that allow management
of segments and tables in address space while in pro-
tected mode. The Table Indicator Bit (TI) in the selector
selects either the General Descriptor Table (GDT) or one
Local Descriptor Table (LDT). If TI = 0, GDT is selected; if
TI =1, LDT is selected. The 13-bit INDEX field in the seg-
ment selector is used to index a GDT or LDT.

Figure 3-5. Protected Mode Address Calculation

Offset Mechanism

Selector Mechanism

Offset Address

Optional

Physical

Segment Base

Address

Paging Mechanism

Linear
Address

Memory

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

3.5.3

Descriptors

3.5.3.1

Global and Local Descriptor Table Registers

The GDT and LDT descriptor tables are defined by the
Global Descriptor Table Register (GDTR) and the Local
Descriptor Table Register (LDTR) respectively. Some texts
refer to these registers as GDT and LDT descriptors.

The following instructions are used in conjunction with the
GDT and LDT registers:

· LGDT - Load memory to GDTR
· LLDT - Load memory to LDTR
· SGDT - Store GDTR to memory
· SLDT - Store LDTR to memory

The GDTR is set up in real mode using the LGDT instruc-
tion. This is possible as the LGDT instruction is one of two
instructions that directly load a linear address (instead of
a segment relative address) in protected mode. (The other
instruction is the Load Interrupt Descriptor Table [LIDT]).

As shown in Table 3-20, the GDTR contains a BASE field
and a LIMIT field that define the GDTs. The Interrupt
Descriptor Table Register (IDTR) is described in Section
3.5.3.3 "Task, Gate, Interrupt, and Application and System
Descriptors" on page 71.

Also shown in Table 3-20, the LDTR is only two bytes wide
as it contains only a SELECTOR field. The contents of the
SELECTOR field point to a descriptor in the GDT.

3.5.3.2

Segment Descriptors

There are several types of descriptors. A segment
descriptor defines the base address, limit, and attributes
of a memory segment.

The GDT or LDT can hold several types of descriptors. In
particular, the segment descriptors are stored in either of
two registers, the GDT or the LDT. Either of these tables
can store as many as 8,192 (2

) 8-byte selectors taking

as much as 64 KB of memory.

The first descriptor in the GDT (location 0) is not used by
the CPU and is referred to as the "null descriptor."

Types of Segment Descriptors
The type of memory segments are defined by correspond-
ing types of segment descriptors:

· Code Segment Descriptors
· Data Segment Descriptors
· Stack Segment Descriptors
· LDT Segment Descriptors

Table 3-20. GDT, LDT and IDT Registers

16 15 14 13 12 11 10

GDT Register

Global Descriptor Table Register

BASE

LIMIT

IDT Register

Interrupt Descriptor Table Register

BASE

LIMIT

LDT Register

Local Descriptor Table Register

SELECTOR

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

3.5.3.3

Task, Gate, Interrupt, and Application and
System Descriptors

Besides segment descriptors there are descriptors used
in task switching, switching between tasks with different
priority and those used to control interrupt functions:

· Interrupt Descriptors
· Application and System Segment Descriptors
· Gate Descriptors
· Task State Segment Descriptors

All descriptors have some things in common. They are all
eight bytes in length and have three fields (BASE, LIMIT,
and TYPE). The BASE field defines the starting location
for the table or segment. The LIMIT field defines the size
and the TYPE field depends on the type of descriptor.
One of the main functions of the TYPE field is to define
the access rights to the associated segment or table.

Interrupt Descriptors
The Interrupt Descriptor Table is an array of 256 8-byte (4-
byte for real mode) interrupt descriptors, each of which is
used to point to an interrupt service routine. Every inter-
rupt that may occur in the system must have an associ-
ated entry in the IDT. The contents of the IDTR are
completely visible to the programmer through the use of
the SIDT instruction.

The IDT is defined by the Interrupt Descriptor Table Reg-
ister (IDTR). Some texts refer to this register as an IDT
descriptor.

The following instructions are used in conjunction with the
IDTR:

· LIDT - Load memory to IDTR
· SIDT - Store IDTR to memory

The IDTR is set up in real mode using the LIDT instruc-
tion. This is possible as the LIDT instruction is only one of
two instructions that directly load a linear address (instead
of a segment relative address) in protected mode (the
other instructions is LGDT).

As previously shown in Table 3-20 on page 70, the IDTR
contains a BASE ADDRESS field and a LIMIT field that
define the IDT tables.

Application and System Segment Descriptors
The bit structure and bit definitions for segment descrip-
tors are shown in Table 3-21 and Table 3-22 on page 72,
respectively. The explanation of the TYPE field is shown
in Table 3-23 on page 73.

Table 3-21. Application and System Segment Descriptors

31 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Memory Offset +4

BASE[31:24]

A
V

LIMIT[19:16]

DPL

TYPE

BASE[23:16]

Memory Offset +0

BASE[15:0]

LIMIT[15:0]

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

Table 3-22. Descriptors Bit Definitions

Bit

Memory

Offset

Name

Description

31:24

BASE

Segment Base Address: Three fields which collectively define the base location for the segment in
4 GB physical address space.

7:0

31:16

19:16

LIMIT

Segment Limit: Two fields that define the size of the segment based on the Segment Limit
Granularity Bit.

If G = 1: Limit value interpreted in units of 4 KB.
If G = 0: Limit value is interpreted in bytes.

15:0

Segment Limit Granularity Bit: Defines LIMIT multiplier.

If G = 1: Limit value interpreted in units of 4 KB. Segment size ranges from 4 KB to 4 GB.
If G = 0: Limit value is interpreted in bytes. Segment size ranges from 1 byte to 1 MB.

Default Length for Operands and Effective Addresses:

If D = 1: Code segment = 32-bit length for operands and effective addresses.
If D = 0: Code segment = 16-bit length for operands and effective addresses.
If D = 1: Data segment = Pushes, calls and pop instructions use 32-bit ESP register.
If D = 0: Data segment = Stack operations use 16-bit SP register.

AVL

Segment Available: This field is available for use by system software.

Segment Present:

If = 1: Segment is memory segment allocated.

If = 0: The BASE and LIMIT fields become available for use by the system. Also, If = 0, a segment-
not-present exception generated when selector for the descriptor is loaded into a segment register
allowing virtual memory management.

14:13

DPL

Descriptor Privilege Level:

If = 00: Highest privilege level
If = 11: Lowest privilege level

Descriptor Type:

If = 1: Code or data segment
If = 0: System segment

11:8

TYPE

Segment Type: Refer to Table 3-23 for TYPE bit definitions.

Bit 11 = Executable
Bit 10 = Conforming if Bit 12 = 1
Bit 10 = Expand Down if Bit 12 = 0
Bit 9 = Readable, if Bit 12 = 1
Bit 9 = Writable, if Bit 12 = 0
Bit 8 = Accessed

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

Table 3-23. Application and System Segment Descriptors TYPE Bit Definitions

TYPE

Bits [11:8]

System Segment and Gate Types

Bit 12 = 0

Application Segment Types

Bit 12 = 1

Num

SEWA

TYPE (Data Segments)

0000

Reserved

Data

Read-Only

0001

Available 16-Bit TSS

Data

Read-Only, accessed

0010

LDT

Data

Read/Write

0011

Busy 16-Bit TSS

Data

Read/Write accessed

0100

16-Bit Call Gate

Data

Read-Only, expand down

0101

Task Gate

Data

Read-Only, expand down, accessed

0110

16-Bit Interrupt Gate

Data

Read/Write, expand down

0111

16-Bit Trap Gate

Data

Read/Write, expand down, accessed

Num

SCRA

TYPE (Code Segments)

1000

Reserved

Code

Execute-Only

1001

Available 32-Bit TSS

Code

Execute-Only, accessed

1010

Reserved

Code

Execute/Read

1011

Busy 32-Bit TSS

Code

Execute/Read, accessed

1100

32-Bit Call Gate

Code

Execute/Read, conforming

1101

Reserved

Code

Execute/Read, conforming, accessed

1110

32-Bit Interrupt Gate

Code

Execute/Read-Only, conforming

1111

32-Bit Trap Gate

Code

Execute/Read-Only, conforming accessed

SEWA/SCRA:S = Code Segment (not Data Segment)

E = Expand Down
W = Write Enable
A = Accessed
C = Conforming Code Segment
R = Read Enable

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

Gate Descriptors
Four kinds of gate descriptors are used to provide protec-
tion during control transfers:
· Call gates
· Trap gates
· Interrupt gates
· Task gates

(For more information on protection refer to Section 3.9

"Protection" on page 91.)

Call Gate Descriptor (CGD). Call gates are used to
define legal entry points to a procedure with a higher priv-
ilege level. The call gates are used by CALL and JUMP
instructions in much the same manner as code segment
descriptors. When a decoded instruction refers to a call
gate descriptor in the GDT or LDT, the call gate is used to
point to another descriptor in the table that defines the
destination code segment.

The following privilege levels are tested during the transfer
through the call gate:
· CPL = Current Privilege Level
· RPL = Segment Selector Field
· DPL = Descriptor Privilege Level in the call gate

descriptor

· DPL = Descriptor Privilege Level in the destination

code segment

The maximum value of the CPL and RPL must be equal
or less than the gate DPL. For a JMP instruction the desti-
nation DPL equals the CPL. For a CALL instruction the
destination DPL is less than or equal to the CPL.

Conforming Code Segments. Transfer to a procedure
with a higher privilege level can also be accomplished by
bypassing the use of call gates, if the requested proce-
dure is to be executed in a conforming code segment.
Conforming code segments have the C bit set in the
TYPE field in their descriptor.

The bit structure and definitions for gate descriptors are
shown in Tables 3-24 and 3-25.

Table 3-24. Gate Descriptors

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Memory Offset +4

OFFSET[31:16]

DPL

TYPE

PARAMETERS

Memory Offset +0

SELECTOR[15:0]

OFFSET[15:0]

Table 3-25. Gate Descriptors Bit Definitions

Bit

Memory

Offset

Name

Description

31:16

OFFSET

Offset: Offset used during a call gate to calculate the branch target.

15:0

31:16

SELECTOR

Segment Selector

Segment Present

14:13

DPL

Descriptor Privilege Level

11:8

TYPE

Segment Type:

0100 = 16-bit call gate

1100 = 32-bit call gate

0101 = Task gate

1110 = 32-bit interrupt gate

0110 = 16-bit interrupt gate

1111 = 32-bit trap gate

0111 = 16-bit trap gate

4:0

PARAMETERS

Parameters: Number of parameters to copy from the caller's stack to the called proce-
dure's stack.

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

Task State Segments Descriptors
The CPU enables rapid task switching using JMP and
CALL instructions that refer to Task State Segment (TSS)
descriptors. During a switch, the complete task state of
the current task is stored in its TSS, and the task state of
the requested task is loaded from its TSS. The TSSs are
defined through special segment descriptors and gates.

The Task Register (TR) holds 16-bit descriptors that con-
tain the base address and segment limit for each task
state segment. The TR is loaded and stored via the LTR
and STR instructions, respectively. The TR can be
accessed only during protected mode and can be loaded
when the privilege level is 0 (most privileged). When the
TR is loaded, the TR selector field indexes a TSS descrip-
tor that must reside in the Global Descriptor Table (GDT).

Only the 16-bit selector of a TSS descriptor in the TR is
accessible. The BASE, TSS LIMIT and ACCESS RIGHT
fields are program invisible.

During task switching, the processor saves the current
CPU state in the TSS before starting a new task. The TSS
can be either a 386/486-type 32-bit TSS (see Table 3-26) or a
286-type 16-bit TSS (see Table 3-27).

Task Gate Descriptors. A task gate descriptor provides
controlled access to the descriptor for a task switch. The
DPL of the task gate is used to control access. The selec-
tor's RPL and the CPL of the procedure must be a higher
level (numerically less) than the DPL of the descriptor.
The RPL in the task gate is not used.

The I/O Map Base Address field in the 32-bit TSS points
to an I/O permission bit map that often follows the TSS at
location +68h.

Table 3-26. 32-Bit Task State Segment (TSS) Table

16 15

I/O Map Base Address

+64h

Selector for Task's LDT

+60h

+5Ch

+58h

+54h

+50h

+4Ch

+48h

EDI

+44h

ESI

+40h

EBP

+3Ch

ESP

+38h

EBX

+34h

EDX

+30h

ECX

+2Ch

EAX

+28h

EFLAGS

+24h

EIP

+20h

CR3

+1Ch

SS for CPL = 2

+18h

ESP for CPL = 2

+14h

SS for CPL = 1

+10h

ESP for CPL = 1

+Ch

SS for CPL = 0

+8h

ESP for CPL = 0

+4h

Back Link (Old TSS Selector)

+0h

Note: 0 = Reserved

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

3.5.4

Paging Mechanism

The paging mechanism translates a linear address to its
corresponding physical address. If the required page is
not currently present in RAM, an exception is generated.
When the operating system services the exception, the
required page can be loaded into memory and the instruc-
tion restarted. Pages are either 4 KB or 1 MB in size. The
CPU defaults to 4 KB pages that are aligned to 4 KB
boundaries.

A page is addressed by using two levels of tables as illus-
trated in Figure 3-8. Bits [31:22] of the 32-bit linear
address, the Directory Table Index (DTI), are used to
locate an entry in the page directory table. The page
directory table acts as a 32-bit master index to up to 1 KB
individual second-level page tables. The selected entry in
the page directory table, referred to as the directory table
entry (DTE), identifies the starting address of the second-
level page table. The page directory table itself is a page
and is therefore aligned to a 4 KB boundary. The physical
address of the current page directory table is stored in the

CR3 control register, also referred to as the Page Direc-
tory Base Register (PDBR).

Bits [21:12] of the 32-bit linear address, referred to as the
Page Table Index (PTI), locate a 32-bit entry in the sec-
ond-level page table. This page table entry (PTE) contains
the base address of the desired page frame. The second-
level page table addresses up to 1K individual page
frames. A second-level page table is 4 KB in size and is
itself a page. Bits [11:0] of the 32-bit linear address, the
Page Frame Offset (PFO), locate the desired physical
data within the page frame.

Since the page directory table can point to 1 KB page
tables, and each page table can point to 1 KB page
frames, a total of 1 MB page frames can be implemented.
Each page frame contains 4 KB, therefore, up to 4 GB of
virtual memory can be addressed by the CPU with a sin-
gle page directory table.

Figure 3-8. Paging Mechanism

Directory Table Index

(DTI)

Page Table Index

(PTI)

Page Frame Offset

(PFO)

22 21

12 11

Linear

Address

DTE Cache

2-Entry

Fully Associative

Main TLB

32-Entry

4-Way Set

Associative

DTE

4 KB

PTE

4 KB

Physical Page

4 GB

-4 KB

-0

External Memory

Directory Table

Page Table

Memory

CR3

Control

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

Along with the base address of the page table or the page
frame, each DTE or PTE contains attribute bits and a
present bit as illustrated in Table 3-28.

If the present bit (P) is set in the DTE, the page table is
present and the appropriate page table entry is read. If P
= 1 in the corresponding PTE (indicating that the page is
in memory), the accessed and dirty bits are updated, if
necessary, and the operand is fetched. Both accessed
bits are set (DTE and PTE), if necessary, to indicate that
the table and the page have been used to translate a linear
address. The dirty bit (D) is set before the first write is made
to a page.

The present bits must be set to validate the remaining bits
in the DTE and PTE. If either of the present bits are not
set, a page fault is generated when the DTE or PTE is
accessed. If P = 0, the remaining DTE/PTE bits are avail-
able for use by the operating system. For example, the
operating system can use these bits to record where on
the hard disk the pages are located. A page fault is also
generated if the memory reference violates the page pro-
tection attributes.

Translation Look-Aside Buffer
The translation look-aside buffer (TLB) is a cache for the
paging mechanism and replaces the two-level page table
lookup procedure for TLB hits. The TLB is a four-way set
associative 32-entry page table cache that automatically
keeps the most commonly used page table entries in the
processor. The 32-entry TLB, coupled with a 4 KB page
size, results in coverage of 128 KB of memory addresses.

The TLB must be flushed when entries in the page tables
are changed. The TLB is flushed whenever the CR3 regis-
ter is loaded. An individual entry in the TLB can be flushed
using the INVLPG instruction.

DTE Cache
The DTE cache caches the two most recent DTEs so that
future TLB misses only require a single page table read to
calculate the physical address. The DTE cache is dis-
abled following RESET and can be enabled by setting the
DTE_EN bit in CCR4[4] (see CCR4 register on page 53).

Table 3-28. Directory Table Entry (DTE) and Page Table Entry (PTE)

Bit

Name

Description

31:12

BASE

ADDRESS

Base Address: Specifies the base address of the page or page table.

11:9

AVAILABLE

Available: Undefined and available to the programmer.

8:7

RSVD

Reserved: Unavailable to programmer.

Dirty Bit:

PTE format -- If = 1: Indicates that a write access has occurred to the page.
DTE format -- Reserved.

Accessed Flag: If set, indicates that a read access or write access has occurred to the page.

4:3

RSVD

Reserved: Set to 0.

U/S

User/Supervisor Attribute:

If = 1: Page is accessible by User at privilege level 3.
If = 0: Page is accessible by Supervisor only when CPL

W/R

Write/Read Attribute:

If = 1: Page is writable.
If = 0: Page is read only.

Present Flag:

If = 1: The page is present in RAM and the remaining DTE/PTE bits are validated
If = 0: The page is not present in RAM and the remaining DTE/PTE bits are available for use by the pro-
grammer.

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

3.6

INTERRUPTS AND EXCEPTIONS

The processing of either an interrupt or an exception
changes the normal sequential flow of a program by trans-
ferring program control to a selected service routine.
Except for SMM interrupts, the location of the selected
service routine is determined by one of the interrupt vec-
tors stored in the interrupt descriptor table.

True interrupts are hardware interrupts and are generated
by signal sources external to the CPU. All exceptions
(including so-called software interrupts) are produced inter-
nally by the CPU.

3.6.1

Interrupts

External events can interrupt normal program execution
by using one of the three interrupt pins on the GXLV pro-
cessor:

· Non-maskable Interrupt (No pin, see note)
· Maskable Interrupt (INTR pin)
· SMM Interrupt (SMI# pin)

Note: There is not an NMI pin on the GXLV processor.
Generation of an NMI interrupt is not possible. However,
software can generate an NMI by setting bit 2 of CCR7.
(See the CCR7 register on page 53.)

For most interrupts, program transfer to the interrupt rou-
tine occurs after the current instruction has been com-
pleted. When the execution returns to the original
program, it begins immediately following the interrupted
instruction.

The NMI interrupt cannot be masked by software and
always uses interrupt vector two to locate its service rou-
tine. Since the interrupt vector is fixed and is supplied
internally, no interrupt acknowledge bus cycles are per-
formed. This interrupt is normally reserved for unusual sit-
uations such as parity errors and has priority over INTR
interrupts.

Once NMI processing has started, no additional NMIs are
processed until an IRET instruction is executed, typically
at the end of the NMI service routine. If the NMI is re-
asserted before execution of the IRET instruction, one
and only one NMI rising edge is stored and then pro-
cessed after execution of the next IRET.

During the NMI service routine, maskable interrupts may
be enabled. If an unmasked INTR occurs during the NMI
service routine, the INTR is serviced and execution
returns to the NMI service routine following the next IRET.
If a HALT instruction is executed within the NMI service
routine, the CPU restarts execution only in response to
RESET, an unmasked INTR or a System Management
Mode (SMM) interrupt. NMI does not restart CPU execu-
tion under this condition.

The INTR interrupt is unmasked when the Interrupt
Enable Flag (IF, bit 9) in the EFLAGS register is set to 1
(See the EFLAGS Register in Table 3-4 on page 46).
Except for string operations, INTR interrupts are acknowl-
edged between instructions. Long string operations have
interrupt windows between memory moves that allow
INTR interrupts to be acknowledged.

When an INTR interrupt occurs, the CPU performs an
interrupt-acknowledge bus cycle. During this cycle, the
CPU reads an 8-bit vector that is supplied by an external
interrupt controller. This vector selects which of the 256
possible interrupt handlers will be executed in response to
the interrupt.

The SMM interrupt has higher priority than either INTR or
NMI. After SMI# is asserted, program execution is passed
to an SMM service routine that runs in SMM address
space reserved for this purpose. The remainder of this
section does not apply to the SMM interrupts. SMM inter-
rupts are described in greater detail later in Section 3.7
"System Management Mode" on page 83.

3.6.2

Exceptions

Exceptions are generated by an interrupt instruction or a
program error. Exceptions are classified as traps, faults or
aborts depending on the mechanism used to report them
and the restartability of the instruction which first caused
the exception.

A Trap exception is reported immediately following the
instruction that generated the trap exception. Trap excep-
tions are generated by execution of a software interrupt
instruction (INTO, INT3, INTn, BOUND), by a single-step
operation or by a data breakpoint.

Software interrupts can be used to simulate hardware
interrupts. For example, an INTn instruction causes the
processor to execute the interrupt service routine pointed
to by the nth vector in the interrupt table. Execution of the
interrupt service routine occurs regardless of the state of
the IF flag (bit 9) in the EFLAGS register.

The one byte INT3, or breakpoint interrupt (vector 3), is a
particular case of the INTn instruction. By inserting this
one byte instruction in a program, the user can set break-
points in the code that can be used during debug.

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

Single-step operation is enabled by setting the TF bit (bit
8) in the EFLAGS register. When the TF is set, the CPU
generates a debug exception (vector 1) after the execution
of every instruction. Data breakpoints also generate a
debug exception and are specified by loading the debug
registers (DR0-DR3, see Table 3-12 on page 55) with the
appropriate values.

A Fault exception is reported before completion of the
instruction that generated the exception. By reporting the
fault before instruction completion, the CPU is left in a
state that allows the instruction to be restarted and the
effects of the faulting instruction to be nullified. Fault
exceptions include divide-by-zero errors, invalid opcodes,
page faults and coprocessor errors. Debug exceptions
(vector 1) are also handled as faults (except for data
breakpoints and single-step operations). After execution
of the fault service routine, the instruction pointer points to
the instruction that caused the fault.

An Abort exception is a type of fault exception that is
severe enough that the CPU cannot restart the program at
the faulting instruction. The double fault (vector 8) is the
only abort exception that occurs on the CPU.

3.6.3

Interrupt Vectors

When the CPU services an interrupt or exception, the cur-
rent program's instruction pointer and flags are pushed
onto the stack to allow resumption of execution of the
interrupted program. In protected mode, the processor
also saves an error code for some exceptions. Program
control is then transferred to the interrupt handler (also
called the interrupt service routine). Upon execution of an
IRET at the end of the service routine, program execution
resumes at the instruction pointer address saved on the
stack when the interrupt was serviced.

3.6.3.1

Interrupt Vector Assignments

Each interrupt (except SMI#) and exception are assigned
one of 256 interrupt vector numbers as shown in Table 3-
29. The first 32 interrupt vector assignments are defined
or reserved. INT instructions acting as software interrupts
may use any of interrupt vectors, 0 through 255.

The non-maskable hardware interrupt (NMI) is assigned
vector 2. Illegal opcodes including faulty FPU instructions
will cause an illegal opcode exception, interrupt vector 6.
NMI interrupts are enabled by setting bit 2 of the CCR7
register (Index EBh[2] = 1, see Table 3-11 on page 52 for
register format).

In response to a maskable hardware interrupt (INTR), the
CPU issues interrupt acknowledge bus cycles used to read
the vector number from external hardware. These vectors
should be in the range 32 to 255 as vectors 0 to 31 are pre-
defined.

3.6.3.2

Interrupt Descriptor Table

The interrupt vector number is used by the CPU to locate
an entry in the interrupt descriptor table (IDT). In real
mode, each IDT entry consists of a 4-byte far pointer to
the beginning of the corresponding interrupt service rou-
tine. In protected mode, each IDT entry is an 8-byte
descriptor. The Interrupt Descriptor Table Register (IDTR)
specifies the beginning address and limit of the IDT. Fol-
lowing RESET, the IDTR contains a base address of
00000000h with a limit of 3FFh.

The IDT can be located anywhere in physical memory as
determined by the IDTR register. The IDT may contain dif-
ferent types of descriptors: interrupt gates, trap gates and
task gates. Interrupt gates are used primarily to enter a
hardware interrupt handler. Trap gates are generally used
to enter an exception handler or software interrupt han-
dler. If an interrupt gate is used, the Interrupt Enable Flag
(IF) in the EFLAGS register is cleared before the interrupt
handler is entered. Task gates are used to make the tran-
sition to a new task.

Table 3-29. Interrupt Vector Assignments

Interrupt

Vector

Function

Exception

Type

Divide error

Fault

Debug exception

Trap/Fault*

NMI interrupt

---

Breakpoint

Trap

Interrupt on overflow

Trap

BOUND range exceeded

Fault

Invalid opcode

Fault

Device not available

Fault

Double fault

Abort

Reserved

---

Invalid TSS

Fault

Segment not present

Fault

Stack fault

Fault

General protection fault

Trap/Fault

Page fault

Fault

Reserved

---

FPU error

Fault

Alignment check exception

Fault

18:31

Reserved

---

32:55

Maskable hardware interrupts

Trap

0:255

Programmed interrupt

Trap

Note: *Data breakpoints and single steps are traps. All other

debug exceptions are faults.

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

3.6.4

Interrupt and Exception Priorities

As the CPU executes instructions, it follows a consistent
policy for prioritizing exceptions and hardware interrupts.
The priorities for competing interrupts and exceptions are
listed in Table 3-30. SMM interrupts always take prece-
dence. Debug traps for the previous instruction and next
instructions are handled as the next priority. When NMI
and maskable INTR interrupts are both detected at the
same instruction boundary, the GXLV processor services
the NMI interrupt first.

The CPU checks for exceptions in parallel with instruction
decoding and execution. Several exceptions can result
from a single instruction. However, only one exception is

generated upon each attempt to execute the instruction.
Each exception service routine should make the appropri-
ate corrections to the instruction and then restart the
instruction. In this way, exceptions can be serviced until
the instruction executes properly.

The CPU supports instruction restart after all faults,
except when an instruction causes a task switch to a task
whose Task State Segment (TSS) is partially not present.
A TSS can be partially not present if the TSS is not page
aligned and one of the pages where the TSS resides is
not currently in memory.

Table 3-30. Interrupt and Exception Priorities

Priority

Description

Notes

Reset.

Caused by the assertion of RESET.

SMM hardware interrupt.

SMM interrupts are caused by SMI# asserted and always have
highest priority.

Debug traps and faults from previous instruction.

Includes single-step trap and data breakpoints specified in the
debug registers.

Debug traps for next instruction.

Includes instruction execution breakpoints specified in the debug
registers.

Non-maskable hardware interrupt.

Caused by NMI asserted.

Maskable hardware interrupt.

Caused by INTR asserted and IF = 1.

Faults resulting from fetching the next instruction.

Includes segment not present, general protection fault and page
fault.

Faults resulting from instruction decoding.

Includes illegal opcode, instruction too long, or privilege violation.

WAIT instruction and TS = 1 and MP = 1.

Device not available exception generated.

ESC instruction and EM = 1 or TS = 1.

Device not available exception generated.

Floating point error exception.

Caused by unmasked floating point exception with NE = 1.

Segmentation faults (for each memory reference
required by the instruction) that prevent transferring
the entire memory operand.

Includes segment not present, stack fault, and general protection
fault.

Page Faults that prevent transferring the entire
memory operand.

Alignment check fault.

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

3.6.5

Exceptions in Real Mode

Many of the exceptions described in Table 3-29 "Interrupt
Vector Assignments" on page 80 are not applicable in real
mode. Exceptions 10, 11, and 14 do not occur in real
mode. Other exceptions have slightly different meanings
in real mode as listed in Table 3-31.

3.6.6

Error Codes

When operating in protected mode, the following exceptions
generate a 16-bit error code:

· Double Fault
· Alignment Check
· Invalid TSS
· Segment Not Present
· Stack Fault
· General Protection Fault
· Page Fault

The error code format and bit definitions are shown in
Table 3-32. Bits [15:3] (selector index) are not meaningful
if the error code was generated as the result of a page
fault. The error code is always zero for double faults and
alignment check exceptions.

Table 3-31. Exception Changes in Real Mode

Vector

Number

Protected Mode

Function

Real Mode

Function

Double fault.

Interrupt table limit overrun.

Invalid TSS.

Does not occur.

Segment not
present.

Does not occur.

Stack fault.

SS segment limit overrun.

General protection
fault.

CS, DS, ES, FS, GS seg-
ment limit overrun. In pro-
tected mode, an error code is
pushed. In real mode, no
error code is pushed.

Page fault.

Does not occur.

Table 3-32. Error Codes

Selector Index

Table 3-33. Error Code Bit Definitions

Fault
Type

Selector Index

(Bits 15:3)

S2 (Bit 2)

S1 (Bit 1)

S0 (Bit 0)

Page
Fault

Reserved.

Fault caused by:

0 = Not present page
1 = Page-level protection

violation

Fault occurred during:

0 = Read access
1 = Write access

Fault occurred during

0 = Supervisor access
1 = User access.

IDT Fault

Index of faulty IDT
selector.

Reserved

If = 1, exception occurred while
trying to invoke exception or
hardware interrupt handler.

Segment
Fault

Index of faulty
selector.

TI bit of faulty selector

If =1, exception occurred while
trying to invoke exception or
hardware interrupt handler.

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

3.7

SYSTEM MANAGEMENT MODE

System Management Mode (SMM) is an enhancement of
the standard x86 architecture. SMM is usually employed
for system power management or software-transparent
emulation of I/O peripherals. SMM is entered through a
hardware signal "System Management Interrupt" (SMI#
pin) that has a higher priority than any other interrupt,
including NMI. An SMM interrupt can also be triggered
from software using an SMINT instruction. Following an
SMM interrupt, portions of the CPU state are automati-
cally saved, SMM is entered, and program execution
begins at the base of SMM address space (Figure 3-9).

The GXLV processor extends System Management Mode
to support the virtualization of many devices, including
VGA video. The SMM mechanism can be triggered not
only by I/O activity, but by access to selected memory
regions. For example, SMM interrupts are generated
when VGA addresses are accessed. As will be described,
other SMM enhancements have reduced SMM overhead
and improved virtualization-software performance

Figure 3-9. System Management Memory Address Space

FFFFFFFFh

00000000h

Non-SMM

SMM

Potential

SMM Address

Space

Physical

Memory Space

FFFFFFFFh

00000000h

4 KB to 32 MB

Physical Memory

4 GB

Defined

SMM

Address

Space

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

3.7.1

SMM Operation

SMM execution flow is summarized in Figure 3-10. Enter-
ing SMM requires the assertion of the SMI# pin for at least
two SYSCLK periods or execution of the SMINT instruction.
For the SMI# signal or SMINT instruction to be recog-
nized, the following configuration registers must be pro-
grammed:

· SMAR (Index CDh-CFh) - The SMM Base address and

size.

· CCR1 (Index C1) - SMAC bit and/or USE_SMI bit.

These registers formats are given in Table 3-11 on page
52.

After triggering an SMM through the SMI# pin or a SMINT
instruction, selected CPU state information is automati-
cally saved in the SMM memory space header located at
the top of SMM memory space. After saving the header,
the CPU enters real mode and begins executing the SMM
service routine starting at the SMM memory region base
address.

The SMM service routine is user definable and may con-
tain system or power management software. If the power
management software forces the CPU to power down or if
the SMM service routine modifies more registers than are
automatically saved, the complete CPU state information
should be saved.

Figure 3-10. SMM Execution Flow

SMI# Sampled Active or

SMINT Instruction Executed

CPU State Stored in SMM

Address Space Header

Program Flow Transfers

to SMM Address Space

CPU Enters Real Mode

Execution Begins at SMM

Address Space Base Address

RSM Instruction Restores CPU
State Using Header Information

Normal Execution Resumes

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

3.7.2

SMI# Pin

External chipsets can generate an SMI based on numer-
ous asynchronous events, including power management
timers, I/O address trapping, external devices, audio FIFO
events, and others. Since SMI# is edge sensitive, the
chipset must generate an edge for each of the events
above, requiring arbitration and storage of multiple SMM
events. These functions are provided by the CS5530 I/O
companion device. The processor generates an SMI
when the external pin changes from high-to-low or when
an Resume (RSM) occurs if SMI# has not remained low
since the initiation of the previous SMI.

3.7.3

SMM Configuration Registers

The SMAR register specifies the base location of SMM
code region and its size limit.

The SMHR register specifies the 32-bit physical address
of the SMM header. The SMHR address must be 32-bit
aligned as the bottom two bits are ignored by the micro-
code. Hardware will detect write operations to SMAR, and
signal the microcode to recompute the header address.
Access to the SMAR and SMHR registers is enabled by
MAPEN (Index C3h[4] see bit details on page 52).

The SMAR register writes to the SMHR register when the
SMAR register is changed. For this reason, changes to
the SMAR register should be completed prior to setting up
the SMHR register. The configuration registers bit formats
are detailed in Table 3-11 beginning on page 52.

3.7.4

SMM Memory Space Header

Tables 3-34 and 3-35 show the SMM header. A memory
address field has been added to the end (offset -40h) of
the header for the GXLV processor. Memory data will be
stored overlapping the I/O data, since these events can-
not occur simultaneously. The I/O address is valid for both
IN and OUT instructions, and I/O data is valid only for
OUT. The memory address is valid for read and write
operations, and memory data is valid only for write opera-
tions.

With every SMI interrupt or SMINT instruction, selected
CPU state information is automatically saved in the SMM
memory space header located at the top of SMM address
space. The header contains CPU state information that is
modified when servicing an SMM interrupt. Included in
this information are two pointers. The Current IP points to
the instruction executing when the SMI was detected, but
it is valid only for an internal I/O SMI.

The Next IP points to the instruction that will be executed
after exiting SMM. The contents of Debug Register 7
(DR7), the Extended Flags Register (EFLAGS), and Con-
trol Register 0 (CR0) are also saved. If SMM has been
entered due to an I/O trap for a REP INSx or REP OUTSx
instruction, the Current IP and Next IP fields contain the
same addresses. In addition, the I and P fields contain
valid information.

If entry into SMM is the result of an I/O trap, it is useful for
the programmer to know the port address, data size and
data value associated with that I/O operation. This informa-
tion is also saved in the header and is valid only if SMI# is
asserted during an I/O bus cycle. The I/O trap information is
not restored within the CPU when executing a RSM instruction.

Table 3-34. SMM Memory Space Header

Mem.

Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

-04h

DR7

08h

EFLAGS

0Ch

CR0

10h

Current IP

14h

Next IP

18h

RSVD

CS Selector

1Ch

CS Descriptor [63:32]

20h

CS Descriptor [31:0]

24h

RSVD

28h

I/O Data Size

I/O Address [15:0]

2Ch

I/O or Memory Data [31:0]

30h

Restored ESI or EDI

34h

I/O or Memory Address [31:0]

Note:

Check the M bit at offset 24

h to determine if the data is memory or I/O.

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

Table 3-35. SMM Memory Space Header Description

Name

Description

Size

DR7

Debug Register 7: The contents of Debug Register 7.

4 Bytes

EFLAGS

Extended Flags Register: The contents of Extended Flags Register.

4 Bytes

CR0

Control Register 0: The contents of Control Register 0.

4 Bytes

Current IP

Current Instruction Pointer: The address of the instruction executed prior to servicing SMM
interrupt.

4 Bytes

Next IP

Next Instruction Pointer: The address of the next instruction that will be executed after exiting
SMM.

4 Bytes

CS Selector

Code Segment Selector: Code segment register selector for the current code segment.

2 Bytes

CS Descriptor

Code Segment Descriptor: Encoded descriptor bits for the current code segment.

8 Bytes

Nested SMI Status: Flag that determines whether an SMI occurred during SMM (i.e., nested).

1 Bit

SoftVGA SMI Status: SMI was generated by an access to VGA region.

1 Bit

External SMI Status:

If = 1: SMI generated by external SMI# pin.
If = 0: SMI internally generated by Internal Bus Interface Unit.

1 Bit

Memory or I/O Access: 0 = I/O access; 1 = Memory access.

1 Bit

Halt Status: Indicates that the processor was in a halt or shutdown prior to servicing the SMM
interrupt.

1 Bit

Software SMM Entry Indicator:

If = 1: Current SMM is the result of an SMINT instruction.
If = 0: Current SMM is not the result of an SMINT instruction.

1 Bit

REP INSx/OUTSx Indicator:

If = 1: Current instruction has a REP prefix.
If = 0: Current instruction does not have a REP prefix.

1 Bit

IN, INSx, OUT, or OUTSx Indicator:

If = 1: Current instruction performed is an I/O WRITE.
If = 0: Current instruction performed is an I/O READ.

1 Bit

CS Writable: Code Segment Writable

If = 1: CS is writable
If = 0: CS is not writable

1 Bit

I/O Data Size

Indicates size of data for the trapped I/O cycle:

01h = BYTE
03h = WORD
0Fh = DWORD

2 Bytes

I/O Address

Processor port used for the trapped I/O cycle

2 Bytes

I/O or Memory Data

Data associated with the trapped I/O or memory cycle

4 Bytes

Restored ESI or EDI

Restored ESI or EDI Value: Used when it is necessary to repeat a REP OUTSx or REP INSx
instruction when one of the I/O cycles caused an SMI# trap.

4 Bytes

Memory Address

Physical address of the operation that caused the SMI

4 Bytes

Note: INSx = INS, INSB, INSW or INSD instruction.

OUTSx = OUTS, OUTSB, OUTSW and OUTSD instruction.

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

3.7.5

SMM Instructions

The GXLV processor core automatically saves a minimal
amount of CPU state information when entering SMM
which allows fast SMM service routine entry and exit.
After entering the SMM service routine, the MOV, SVDC,
SVLDT and SVTS instructions can be used to save the
complete CPU state information. If the SMM service rou-
tine modifies more state information than is automatically
saved or if it forces the CPU to power down, the complete
CPU state information must be saved. Since the CPU is a
static device, its internal state is retained when the input
clock is stopped. Therefore, an entire CPU-state save is
not necessary before stopping the input clock.

The SMM instructions, listed in Table 3-36, can be exe-
cuted only if all the conditions listed below are met.

USE_SMI = 1.

SMAR size > 0.

Current Privilege Level = 0.

SMAC bit is high or the CPU is in an SMM service
routine.

If any one of the conditions above is not met and an
attempt is made to execute an SVDC, RSDC, SVLDT,
RSLDT, SVTS, RSTS, or RSM instruction, an invalid
opcode exception is generated. The SMM instructions can
be executed outside of defined SMM space provided the
conditions above are met.

The SMINT instruction can be used by software to enter
SMM. The SMINT instruction can only be used outside an
SMM routine if all the conditions listed below are true.

USE_SMI = 1

SMAR size > 0

Current Privilege Level = 0

SMAC = 1

If SMI# is asserted to the CPU during a software SMI, the
hardware SMI# is serviced after the software SMI has
been exited by execution of the RSM instruction.

All the SMM instructions (except RSM and SMINT) save
or restore 80 bits of data, allowing the saved values to
include the hidden portion of the register contents.

Table 3-36. SMM Instruction Set

Instruction

Opcode

Format

Description

SVDC

0F 78h [mod sreg3 r/m]

SVDC mem80, sreg3

Save Segment Register and Descriptor:

Saves reg (DS, ES, FS, GS, or SS) to mem80.

RSDC

0F 79h [mod sreg3 r/m]

RSDC sreg3, mem80

Restore Segment Register and Descriptor:

Restores reg (DS, ES, FS, GS, or SS) from mem80. Use RSM
to restore CS.

Note: Processing "RSDC CS, mem80" will produce an excep-

tion.

SVLDT

0F 7Ah [mod 000 r/m]

SVLDT mem80

Save LDTR and Descriptor:

Saves Local Descriptor Table (LDTR) to mem80.

RSLDT

0F 7Bh [mod 000 r/m]

RSLDT mem80

Restore LDTR and Descriptor:

Restores Local Descriptor Table (LDTR) from mem80.

SVTS

0F 7Ch [mod 000 r/m]

SVTS mem80

Save TSR and Descriptor:

Saves Task State Register (TSR) to mem80.

RSTS

0F 7Dh [mod 000 r/m]

RSTS mem80

Restore TSR and Descriptor:

Restores Task State Register (TSR) from mem80.

SMINT

0F 38h

SMINT

Software SMM Entry:

CPU enters SMM. CPU state information is saved in SMM
memory space header and execution begins at SMM base
address.

RSM

0F AAh

RSM

Resume Normal Mode:

Exits SMM. The CPU state is restored using the SMM memory
space header and execution resumes at interrupted point.

Note:

mem80 = 80-bit memory location.

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

3.7.6

SMM Memory Space

SMM memory space is defined by specifying the base
address and size of the SMM memory space in the SMAR
register. The base address must be a multiple of the SMM
memory space size. For example, a 32 KB SMM memory
space must be located at a 32 KB address boundary. The
memory space size can range from 4 KB to 32 MB. Execu-
tion of the interrupt begins at the base of the SMM memory
space.

SMM memory space accesses are always cacheable,
which allows SMM routines to run faster.

3.7.7

SMI Generation for Virtual VGA

The GXLV processor implements SMI generation for VGA
accesses. When enabled memory write operations in
regions A0000h to AFFFFh, B0000h to B7FFFh, and
B8000h to BFFFFh generate an SMI. Memory reads are
not trapped by the GXLV processor. When enabled, the
GXLV processor traps I/O addresses for VGA in the fol-
lowing regions: 3B0h to 3BFh, 3C0h to 3CFh, and 3D0h
to 3DFh. Memory-write trapping is performed during
instruction decode in the processor core. I/O read and
write trapping is implemented in the Internal Bus Interface
Unit of the GXLV processor.

The SMI-generation hardware requires two additional
configuration registers to control and mask SMI interrupts
in the VGA memory space: VGACTL and VGAM. The
VGACTL register has a control bit for each address range
shown above. The VGAM register has 32 bits that can
selectively disable 2 KB regions within the VGA memory.
The VGAM applies only to the A0000h to AFFFFh region.
If this region is not enabled in VGA_CTL, then the con-
tents of VGAM is ignored. The purpose of VGAM is to pre-
vent an SMI from occurring when non-displayed VGA
memory is accessed. This is an enhancement which
improves performance for double-buffered applications.
The format of each register is shown in Table 4-37 on
page 163.

3.7.8

SMM Service Routine Execution

Upon entry into SMM, after the SMM header has been
saved, the CR0, EFLAGS, and DR7 registers are set to
their reset values. The Code Segment (CS) register is
loaded with the base, as defined by the SMAR register,
and a limit of 4 GB. The SMM service routine then begins
execution at the SMM base address in real mode.

The programmer must save, restore the value of any reg-
isters not saved in the header that may be changed by the
SMM service routine. For data accesses immediately after
entering the SMM service routine, the programmer must
use CS as a segment override. I/O port access is possible
during the routine but care must be taken to save registers
modified by the I/O instructions. Before using a segment
register, the register and the register's descriptor cache con-
tents should be saved using the SVDC instruction.

Hardware interrupts, INTRs and NMIs, may be serviced
during an SMM service routine. If interrupts are to be ser-
viced while executing in the SMM memory space, the

SMM memory space must be within the address range of
0 to 1 MB to guarantee proper return to the SMM service
routine after handling the interrupt.

INTRs are automatically disabled when entering SMM
since the IF flag (EFLAGS register, bit 9) is set to its reset
value. Once in SMM, the INTR can be enabled by setting
the IF flag. An NMI event in SMM can be enabled by set-
ting NMI_EN high in the CCR3 register (Index C3h[1]). If
NMI is not enabled while in SMM, the CPU latches one
NMI event and services the interrupt after NMI has been
enabled or after exiting SMM through the RSM instruction.
Upon entering SMM, the processor is in real mode, but it
may exit to either real or protected mode depending on its
state when SMM was initiated. The SMM header indicates
to which state it will exit.

Within the SMM service routine, protected mode may be
entered and exited as required, and real or protected
mode device drivers may be called.

To exit the SMM service routine, an RSM instruction,
rather than an IRET, is executed. The RSM instruction
causes the GXLV processor core to restore the CPU state
using the SMM header information and resume execution
at the interrupted point. If the full CPU state was saved by
the programmer, the stored values should be reloaded
before executing the RSM instruction using the MOV,
RSDC, RSLDT and RSTS instructions.

3.7.8.1

SMI Nesting

The SMI mechanism supports nesting of SMI interrupts
through the SMM service routine the SMI_NEST bit in the
CCR4 register (Index E8h[6]), and the Nested SMI Status
bit (bit N in the SMM header, see Table 3-35 "SMM Mem-
ory Space Header Description" on page 86). Nesting is an
important capability in allowing high-priority events, such
as audio virtualization, to interrupt lower-priority SMI code
for VGA virtualization or power management. SMI_NEST
controls whether SMI interrupts can occur during SMM.
SMM service routines can optionally set SMI_NEST high
to allow higher-priority SMI interrupts while handling the
current event.

The SMM service routine is responsible for managing the
SMM header data for nested SMI interrupts. The SMM
header must be saved before SMI_NEST is set high, and
SMI_NEST must be cleared and its header information
restored before an RSM instruction is executed.

The Nested SMI Status bit has been added to the SMM
header to show whether the current SMI is nested. The
processor sets Nested SMI Status high if the processor
was in SMM when the SMI was taken. The processor
uses Nested SMI Status on exit to determine whether the
processor should stay in SMM.

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

When SMI nesting is disabled, the processor holds off
external SMI interrupts until the currently executing SMM
code exits. When SMI nesting is enabled, the processor
can proceed with the SMI. The SMM service routine will
guarantee that no internal SMIs are generated in SMM, so
the processor ignores such events. If the internal and
external SMI signals are received simultaneously, then the
internal SMI is given priority to avoid losing the event.

The state diagram of the SMI_NEST and Nested SMI Sta-
tus bits are shown in Figure 3-11 with each state
explained next.

When the processor is outside of SMM, Nested SMI
Status is always clear and SMI_NEST is set high.

The first-level SMI interrupt is received by the
processor. The microcode clears SMI_NEST, sets
Nested SMI Status high and saves the previous value
of Nested SMI Status (0) in the SMM header.

The first-level SMM service routine saves the header
and sets SMI_NEST high to re-enable SMI interrupts
from SMM.

A second-level (nested) SMI interrupt is received by
the processor. This SMI is taken even though the
processor is in SMM because the SMI_NEST bit is
set high. The microcode clears SMI_NEST, sets

Nested SMI Status high and saves the previous value
of Nested SMI Status (1) in the SMM header.

The second-level SMM service routine saves the
header and sets SMI_NEST to re-enable SMI inter-
rupts within SMM. Another level of nesting could
occur during this period.

The

second-level

SMM

service

routine

clears

SMI_NEST to disable SMI interrupts, then restores its
SMM header.

The second-level SMM service routine executes an
RSM. The microcode sets SMI_NEST, and restores
the Nested SMI Status (1) based on the SMM
header.

The first-level SMM service routine clears SMI_NEST
to disable SMI interrupts, then restores its SMM
header.

The first-level SMM service routine executes an
RSM. The microcode sets SMI_NEST high and
restores the

Nested SMI Status (0) based on the

SMM header.

When the processor is outside of SMM, Nested SMI Sta-
tus is always clear and SMI_NEST is set high.

Figure 3-11. SMI Nesting State Machine

SMI_NEST

Nested SMI Status

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

3.7.8.2

CPU States Related to SMM and Suspend
Mode

The state diagram shown in Figure 3-12 illustrates the var-
ious CPU states associated with SMM and Suspend
mode. While in the SMM service routine, the GXLV pro-
cessor core can enter Suspend mode either by (1) execut-
ing a halt (HLT) instruction or (2) by asserting the SUSP#
input.

During SMM operations and while in SUSP#-initiated
Suspend mode, an occurrence of either NMI or INTR is

latched. (In order for INTR to be latched, the IF flag,
EFLAGS register bit 9, must be set.) The INTR or NMI is
serviced after exiting Suspend mode.

If Suspend mode is entered through a HLT instruction
from the operating system or application software, the
reception of an SMI# interrupt causes the CPU to exit
Suspend mode and enter SMM. If Suspend mode is
entered through the hardware (SUSP# = 0) while the
operating system or application software is active, the
CPU latches one occurrence of INTR, NMI, and SMI#.

Figure 3-12. SMM and Suspend Mode State Diagram

Suspend Mode
(SUSPA# = 0)

NMI or INTR

HLT*

IRET*

RSM*

SMI# = 0

SMINT*

SUSP# = 1

SUSP# = 0

Interrupt Service

Routine

Interrupt Service

Routine

OS/Application

Software

SMM Service Routine

(SMI# = 0)

NMI or INTR

RESET

SMI# = 0

(INTR, NMI and SMI# latched)

Non-SMM Operations

SMM Operations

Interrupt Service

Routine

Suspend Mode
(SUSPA# = 0)

(INTR and NMI latched)

NMI or INTR

IRET*

SUSP# = 0

SUSP# = 1

IRET*

HLT*

NMI or INTR

*Instructions

SMM Service Routine

(SMI# = 0)

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

3.8

HALT AND SHUTDOWN

The halt instruction (HLT) stops program execution and
generates the Halt bus cycle on the PCI bus. The GXLV
processor core then drives out a Stop Grant bus cycle and
enters a low-power Suspend mode if the SUSP_HLT bit in
CCR2 (Index C2h[3]) is set. SMI#, NMI, INTR with inter-
rupts enabled (IF bit in EFLAGS = 1), or RESET forces
the CPU out of the halt state. If the halt state is inter-
rupted, the saved code segment and instruction pointer
specify the instruction following the HLT.

Shutdown occurs when a severe error is detected that
prevents further processing. The most common severe
error is the triple fault, a fault event while handling a dou-
ble fault. Setting the IDT limit to zero or the GDT limit to
zero will cause a triple fault when in protected mode.

A RESET brings the processor out of shutdown. An NMI
will work if the IDT limit is large enough, at least 000Fh, to
contain the NMI interrupt vector and if the stack has
enough room. The stack must be large enough to contain
the vector and flag information (the stack pointer must be
greater than 0005h).

3.9

PROTECTION

Segment protection and page protection are safeguards
built into the GXLV processor's protected-mode architec-
ture that deny unauthorized or incorrect access to
selected memory addresses. These safeguards allow
multitasking programs to be isolated from each other and
from the operating system. This section concentrates on
segment protection.

Selectors and descriptors are the key elements in the seg-
ment protection mechanism. The segment base address,
size, and privilege level are established by a segment
descriptor. Privilege levels control the use of privileged
instructions, I/O instructions and access to segments and
segment descriptors. Selectors are used to locate seg-
ment descriptors.

Segment accesses are divided into two basic types, those
involving code segments (e.g., control transfers) and
those involving data accesses. The ability of a task to
access a segment depends on the:

· Segment type
· Instruction requesting access
· Type of descriptor used to define the segment
· Associated privilege levels (described next)

Data stored in a segment can be accessed only by code
executing at the same or a more privileged level. A code
segment or procedure can only be called by a task exe-
cuting at the same or a less privileged level.

3.9.1

Privilege Levels

The values for privilege levels range between 0 and 3.
Level 0 is the highest privilege level (most privileged), and
level 3 is the lowest privilege level (least privileged). The
privilege level in real mode is zero.

The Descriptor Privilege Level (DPL) is the privilege
level defined for a segment in the segment descriptor. The
DPL field specifies the minimum privilege level needed to
access the memory segment pointed to by the descriptor.

The Current Privilege Level (CPL) is defined as the cur-
rent task's privilege level. The CPL of an executing task is
stored in the hidden portion of the code segment register
and essentially is the DPL for the current code segment.

The Requested Privilege Level (RPL) specifies a selec-
tor's privilege level. RPL is used to distinguish between
the privilege level of a routine actually accessing memory
(the CPL), and the privilege level of the original requester
(the RPL) of the memory access. The lesser of the RPL
and CPL is called the Effective Privilege Level (EPL). There-
fore, if RPL = 0 in a segment selector, the EPL is always
determined by the CPL. If RPL = 3, the EPL is always 3
regardless of the CPL. If the level requested by RPL is
less than the CPL, the RPL level is accepted and the EPL
is changed to the RPL value. If the level requested by RPL
is greater than CPL, the CPL overrides the requested RPL
and EPL becomes the CPL value.

For a memory access to succeed, the EPL must be at
least as privileged as the Descriptor Privilege Level (EPL

DPL). If the EPL is less privileged than the DPL (EPL >

DPL), a general protection fault is generated. For exam-
ple, if a segment has a DPL = 2, an instruction accessing
the segment only succeeds if executed with an EPL

3.9.2

I/O Privilege Levels

The I/O Privilege Level (IOPL) allows the operating sys-
tem executing at CPL = 0 to define the least privileged
level at which IOPL-sensitive instructions can uncondition-
ally be used. The IOPL-sensitive instructions include CLI,
IN, OUT, INS, OUTS, REP INS, REP OUTS, and STI.
Modification of the IF bit in the EFLAGS register is also
sensitive to the I/O privilege level.

The IOPL is stored in the EFLAGS register (bits [31:12]).
An I/O permission bit map is available as defined by the
32-bit Task State Segment (TSS). Since each task can
have its own TSS, access to individual I/O ports can be
granted through separate I/O permission bit maps.

If CPL

IOPL, IOPL-sensitive operations can be per-

formed. If CPL > IOPL, a general protection fault is gener-
ated if the current task is associated with a 16-bit TSS. If
the current task is associated with a 32-bit TSS and CPL
> IOPL, the CPU consults the I/O permission bitmap in the
TSS to determine on a port-by-port basis whether or not I/O
instructions (IN, OUT, INS, OUTS, REP INS, REP OUTS)
are permitted. The remaining IOPL-sensitive operations
generate a general protection fault.

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

3.9.3

Privilege Level Transfers

A task's CPL can be changed only through intersegment
control transfers using gates or task switches to a code
segment with a different privilege level. Control transfers
result from exception and interrupt servicing and from
execution of the CALL, JMP, INT, IRET and RET instruc-
tions.

There are five types of control transfers that are summa-
rized in Table 3-37. Control transfers can be made only
when the operation causing the control transfer references

the correct descriptor type. Any violation of these descriptor
usage rules causes a general protection fault.

Any control transfer that changes the CPL within a task
results in a change of stack. The initial values for the stack
segment (SS) and stack pointer (ESP) for privilege levels
0, 1, and 2 are stored in the TSS. During a JMP or CALL
control transfer, the SS and ESP are loaded with the new
stack pointer and the previous stack pointer is saved on
the new stack. When returning to the original privilege
level, the RET or IRET instruction restores the SS and
ESP of the less-privileged stack.

Table 3-37. Descriptor Types Used for Control Transfer

Type of Control Transfer

Operation Types

Descriptor

Referenced

Descriptor

Table

Intersegment within the same privilege
level.

JMP, CALL, RET, IRET*

Code Segment

GDT or LDT

Intersegment to the same or a more
privileged level. Interrupt within task
(could change CPL level).

CALL

Gate Call

GDT or LDT

Interrupt Instruction, Exception,
External Interrupt

Trap or Interrupt Gate

IDT

Intersegment to a less privileged level
(changes task CPL).

RET, IRET*

Code Segment

GDT or LDT

Task Switch via TSS

CALL, JMP

Task State Segment

GDT

Task Switch via Task Gate

CALL, JMP

Task Gate

GDT or LDT

IRET**, Interrupt Instruction,
Exception, External Interrupt

Task Gate

IDT

Note:

*NT = 0 (Nested Task bit in EFLAGS, bit 14)
**NT =1 (Nested Task bit in EFLAGS, bit 14)

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

3.9.3.1

Gates

Gate descriptors described in Section "Gate Descriptors"
on page 74, provide protection for privilege transfers
among executable segments. Gates are used to transition
to routines of the same or a more privileged level. Call
gates, interrupt gates and trap gates are used for privilege
transfers within a task. Task gates are used to transfer
between tasks.

Gates conform to the standard rules of privilege. In other
words, gates can be accessed by a task if the effective
privilege level (EPL) is the same or more privileged than
the gate descriptor's privilege level (DPL).

3.9.4

Initialization and Transition to Protected Mode

The GXLV processor core switches to real mode immedi-
ately after RESET. While operating in real mode, the sys-
tem tables and registers should be initialized. The GDTR
and IDTR must point to a valid GDT and IDT, respectively. The
size of the IDT should be at least 256 bytes, and the GDT
must contain descriptors that describe the initial code and
data segments.

The processor can be placed in protected mode by setting
the PE bit (CR0 register bit 0). After enabling protected
mode, the CS register should be loaded and the instruc-
tion decode queue should be flushed by executing an
intersegment JMP. Finally, all data segment registers
should be initialized with appropriate selector values.

3.10 VIRTUAL 8086 MODE

Both real mode and virtual 8086 (V86) modes are sup-
ported by the GXLV processor, allowing execution of 8086
application programs and 8086 operating systems. V86
mode allows the execution of 8086-type applications, yet
still permits use of the paging and protection mechanisms.
V86 tasks run at privilege level 3. Before entry, all seg-
ment limits must be set to FFFFh (64K) as in real mode.

3.10.1 Memory Addressing
While in V86 mode, segment registers are used in an
identical fashion to real mode. The contents of the Seg-
ment register are multiplied by 16 and added to the offset
to form the Segment Base Linear Address. The GXLV pro-
cessor permits the operating system to select which pro-
grams use the V86 address mechanism and which
programs use protected mode addressing for each task.

The GXLV processor also permits the use of paging when
operating in V86 mode. Using paging, the 1 MB address
space of the V86 task can be mapped to any region in the
4 GB linear address space.

The paging hardware allows multiple V86 tasks to run
concurrently, and provides protection and operating sys-
tem isolation. The paging hardware must be enabled to
run multiple V86 tasks or to relocate the address space of
a V86 task to physical address space other than 0.

3.10.2 Protection
All V86 tasks operate with the least amount of privilege
(level 3) and are subject to all CPU protected mode protec-
tion checks. As a result, any attempt to execute a privi-
leged instruction within a V86 task results in a general
protection fault.

In V86 mode, a slightly different set of instructions are
sensitive to the I/O privilege level (IOPL) than in protected
mode. These instructions are: CLI, INT n, IRET, POPF,
PUSHF, and STI. The INT3, INTO and BOUND variations
of the INT instruction are not IOPL sensitive.

3.10.3 Interrupt Handling
To fully support the emulation of an 8086-type machine,
interrupts in V86 mode are handled as follows. When an
interrupt or exception is serviced in V86 mode, program
execution transfers to the interrupt service routine at privi-
lege level 0 (i.e., transition from V86 to protected mode
occurs). The VM bit in the EFLAGS register (bit 17) is
cleared. The protected mode interrupt service routine
then determines if the interrupt came from a protected
mode or V86 application by examining the VM bit in the
EFLAGS image stored on the stack. The interrupt service
routine may then choose to allow the 8086 operating sys-
tem to handle the interrupt or may emulate the function of
the interrupt handler. Following completion of the interrupt
service routine, an IRET instruction restores the EFLAGS
register (restores VM = 1) and segment selectors and
control returns to the interrupted V86 task.

3.10.4 Entering and Leaving Virtual 8086 Mode
V86 mode is entered from protected mode by either exe-
cuting an IRET instruction at CPL = 0 or by task switching.
If an IRET is used, the stack must contain an EFLAGS
image with VM = 1. If a task switch is used, the TSS must
contain an EFLAGS image containing a 1 in the VM bit
position. The POPF instruction cannot be used to enter
V86 mode since the state of the VM bit is not affected.
V86 mode can only be exited as the result of an interrupt
or exception. The transition out must use a 32-bit trap or
interrupt gate that must point to a non-conforming privi-
lege level 0 segment (DPL = 0), or a 32-bit TSS. These
restrictions are required to permit the trap handler to IRET
back to the V86 program.

www.national.com

Revision 1.3

Processor Programming (

Continued

)

odeTM

r
o

ries

3.11 FLOATING POINT UNIT OPERATIONS

The GXLV processor contains an FPU that is x87 and
MMX instruction-set compatible and adheres to the IEEE-
754 standard. Because most applications that contain
FPU instructions intermix with integer instructions, the
GXLV processor's FPU achieves high performance by
completing integer and FPU operations in parallel.

3.11.1 FPU Register Set
The FPU provides the user eight data registers, a control
register, and a status register. The CPU also provides a
data register tag word that improves context switching and
stack performance by maintaining empty/non-empty sta-
tus for each of the eight data registers. Two additional,
registers contain pointers to (a) the memory location con-
taining the current instruction word and (b) the memory
location containing the operand associated with the cur-
rent instruction word (if any).

3.11.2 FPU Tag Word Register
The FPU maintains a tag word register that is divided into
eight tag word fields. These fields assume one of four val-
ues depending on the contents of their associated data
registers: Valid (00), Zero (01), Special (10), and Empty
(11). Note: Denormal, Infinity, QNaN, SNaN and unsup-
ported formats are tagged as "Special". Tag values are
maintained transparently by the CPU and are only avail-
able to the programmer indirectly through the FSTENV and
FSAVE instructions. The tag word with TAG fields for each
associated physical register, TAG(n), is shown in Table 3-
38.

3.11.3 FPU Status Register
The FPU communicates status information and operation
results to the CPU through the FPU status register, whose
fields are detailed in Table 3-38. These fields include infor-
mation related to exception status, operation execution
status, register status, operand class, and comparison
results. This register is continuously accessible to the
CPU regardless of the state of the Control or Execution
Units.

3.11.4 FPU Mode Control Register
The FPU Mode Control Register, shown in Table 3-38, is
used by the GXLV processor to specify the operating
mode of the FPU. The register fields include information
related to the rounding mode selected, the amount of pre-
cision to be used in the calculations, and the exception
conditions which should be reported to the GXLV proces-
sor using traps. The user controls precision, rounding,
and exception reporting by setting or clearing appropriate
bits.

Revision 1.3

www.national.com

Processor Programming (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

Table 3-38. FPU Registers

Bit

Name

Description

FPU Tag Word Register (R/W) (Note)

15:14

TAG7

TAG7: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

13:12

TAG6

TAG6: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

11:10

TAG5

TAG5: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

9:8

TAG4

TAG4: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

7:6

TAG3

TAG3: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

5:4

TAG2

TAG2: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

3:2

TAG1

TAG1: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

1:0

TAG0

TAG0: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

FPU Status Register (R/W) (Note)

Copy of ES bit (bit 7 this register)

Condition code bit 3

13:11

Top-of-Stack: Register number that points to the current TOS.

10:8

C[2:0]

Condition code bits [2:0]

Error indicator: Set to 1 if unmasked exception detected.

Stack Full: FPU Status Register: or invalid register operation bit.

Precision error exception bit

Underflow error exception bit

Overflow error exception bit

Divide-by-zero exception bit

Denormalized-operand error exception bit

Invalid operation exception bit

FPU Mode Control Register (R/W) (Note)

15:12

RSVD

Reserved: Set to 0

11:10

Rounding control bits:
00 = Round to nearest or even
01 = Round towards minus infinity
10 = Round towards plus infinity
11 = Truncate

9:8

Precision control bits:
00 = 24-bit mantissa
01 = Reserved
10 = 53-bit mantissa
11 = 64-bit mantissa

7:6

RSVD

Reserved: Set to 0

Precision error exception bit

Underflow error exception bit

Overflow error exception bit

Divide-by-zero exception bit

Denormalized-operand error exception bit

Invalid-operation exception bit

Note: R/W only through the environment at store and restore commands.

www.national.com

Revision 1.3

odeTM

r
o

ries

4.0

Integrated Functions

The integrated functions in the Geode GXLV processor
are:

· Internal bus interface

· SDRAM memory controller

· High-performance 2D graphics accelerator

· Display controller with separate CRT and TFT data

paths

· PCI bridge

The design organizes the memory controller, graphics
pipeline and display controller into a Unified Memory
Architecture (UMA). UMA simplifies system designs and
significantly reduces overall system costs associated with

high chip count, small footprint designs. Performance deg-
radation in traditional UMA systems is reduced through
the use of National Semiconductor's Display Compression
Technology (DCT) architecture.

Figure 4-1 shows the major functional blocks of the GXLV
processor and how the Internal Bus Interface Unit oper-
ates as the interface between the processor's core units
and the integrated functions.

This section details how the integrated functions and
Internal Bus Interface Unit operate and their respective
registers.

Figure 4-1. Internal Block Diagram

Write-Back

Unit

FPU

Internal Bus Interface Unit

Graphics

Memory

Display

PCI

SDRAM Port

CS5530

PCI Bus

Integer

Cache Unit

Integrated

Functions

MMU

(CRT/LCD TFT)

X-Bus

Pipeline

Controller

C-Bus

Revision 1.3

www.national.com

Integrated Functions (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

4.1

INTEGRATED FUNCTIONS PROGRAMMING INTERFACE

The GXLV processor's integrated functions programming
interface is a memory mapped space. The control regis-
ters for the graphics pipeline, display controller, and mem-
ory controller are located in this space, as well as all the
graphics memory: frame buffer, compression buffer etc.
This memory address space is referred to as the GXLV
processor memory space.

4.1.1

Graphics Control Register

The base address for these memory mapped registers is
programmed in the Graphics Configuration Register
(GCR, Index B8h, bits[1:0]), shown in Table 4-1. The GCR
only specifies address bits [31:30] of physical memory.
The remaining address bits [29:0] are fixed to zero. The
GCR is I/O mapped because it must be accessed before
memory mapping can be enabled. Refer to Section
3.3.2.2 "Configuration Registers" on page 50 for informa-
tion on how to access this register.

The GXLV processor incorporates graphics functions that
require registers to implement and control them. Most of
these registers are memory mapped and physically
located in the logical units they control. The mapping of
these units is controlled by the GCR register.

Figure 4-2 shows the complete memory address map for
the GXLV processor. When accessing the GXLV proces-
sor memory space, address bits [29:24] must be zero.
This means that the GXLV processor accesses a linear
address space with a total of 16 MB. Address bit 23
divides this space into 8 MB for control (bit 23 = 0) and 8
MB for graphics memory (bit 23 = 1). In control space, bits
[22:16] are not decoded, so the programmer should set
them to zero. Address bit 15 divides the remaining 64 KB
address space into scratchpad RAM and PCI access (bit
15 = 0) and control registers (bit 15 = 1). Note that
scratchpad RAM is placed here by programming the tags
appropriately.

Device drivers are responsible for performing physical-to-
virtual memory-address translation, including allocation of
selectors that point to the GXLV processor. All memory
decoded by the processor may be accessed in protected
mode by creating a selector with the physical address
equal to the GXLV Base Address which is shown in Table
4-1, and a limit of 16 MB. Additionally, a selector with only
a 64 KB limit is large enough to access all of the GXLV
processor's registers and scratchpad RAM.

Table 4-1. GCR Register

Bit

Name

Description

Index B8h

GCR Register (R/W)

Default Value = 00h

7:4

RSVD

Reserved: Set to 0.

3:2

Scratchpad Size: Specifies the size of the scratchpad cache.

00 = 0 KB; Graphics instruction disabled (see Section 4.1.5 "Display Driver Instructions" on page 102).
01 = 2 KB
10 = 3 KB
11 = 4 KB

1:0

GXLV Base Address: Specifies the physical address for the base (GX_BASE) of the scratchpad RAM, the
graphics memory (frame buffer, compression buffer, etc.) and the other memory mapped registers.

00 = Scratchpad RAM, graphics subsystem, and memory-mapped configuration registers are disabled.
01 = Scratchpad RAM and control registers start at GX_BASE = 40000000h.
10 = Scratchpad RAM and control registers start at GX_BASE = 80000000h.
11 = Scratchpad RAM and control registers start at GX_BASE = C0000000h.

www.national.com

Revision 1.3

Integrated Functions (

Continued

)

odeTM

r
o

ries

Figure 4-2. GXLV Processor Memory Space

Conventional Memory

UMBs and Expansion ROMs

Video BIOS

System BIOS

Extended Memory

Scratchpad RAM

VGA/MDA

Frame Buffers

(Soft VGA and/or PCA/ISA)

Internal Bus IF Unit Registers

Graphics Pipeline Registers

SMM System Code

(Frame Buffer, etc.)

PCI Access

ROM Access

(256 KB)

A0000h (640 KB)

C0000h

E0000h

100000h (1 MB)

E8000h

GX_BASE+8000h

GX_BASE+9000h

GX_BASE+400000h

GX_BASE+800000h

GX_BASE+8800000h

FFFC0000h

FFFFFFFFh (4 GB)

Extended Memory

Graphics Memory

(Frame Buffer, etc.)

A0000h (640 KB)

C0000h

E0000h

100000h (1 MB)

E8000h

Shadowed Video BIOS

Shadowed System BIOS

SMM System Code

Physical Address Map

DRAM Map

MAX

*GBADD or Top of DRAM

*Top of DRAM

PCI Access

Display Controller Registers

Memory Controller Registers

Graphics Memory

* See BC_DRAM_TOP in Table 4-8 on page 104 or MC_GBASE_ADD in Table 4-15 on page 116.

(See Table 4-28 on page 141)

(See Table 4-23 on page 129)

(See Table 4-8 on page 104)

FFFF FFFFh

MAX

Conventional Memory

UMBs and

Expansion ROMs

GX_BASE+8500h

GX_BASE+8400h

(See Table 4-14 on page 112)

GX_BASE+8300h

GX_BASE+8100h

(See Table 4-3 on page 100)

GX_BASE+1000h

Power Management Registers

(See Table 5-1 on page 181)

GX_BASE

Available to the system

PCI Access

Available to the system

Revision 1.3

www.national.com

Integrated Functions (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

4.1.2

Control Registers

The control registers for the GXLV processor use 32 KB of
the memory map, starting at GX_BASE+8000h (see Fig-
ure 4-2). This area is divided into internal bus interface
unit, graphics pipeline, display controller, memory control-
ler, and power management sections:

· The internal bus interface unit maps 100h locations

starting at GX_BASE+8000h.

· The graphics pipeline maps 200h locations starting at

GX_BASE+8100h.

· The display controller maps 100h locations starting at

GX_BASE+8300h.

· The memory controller maps 100h locations starting at

GX_BASE+8400h

· GX_BASE+8500h-8FFFh is dedicated to power

management registers for the serial packet transmis-
sion control, the user-defined power management
address space, Suspend Refresh, and SMI status for
Suspend/Resume.

The register descriptions are contained in the individual
subsections of this chapter. Accesses to undefined regis-
ters in the GXLV processor control register space will not
cause a hardware error.

4.1.3

Graphics Memory

Graphics memory is allocated from system DRAM by the
system BIOS. The GXLV processor's graphics memory is
mapped into 4 MB starting at GX_BASE+800000h. This
area includes the frame buffer memory and storage for
internal display controller state. The size of the frame
buffer is a linear map whose size depends on the user's
requirements (i.e., resolution, color depth, video buffer,
compression buffer, font caching, etc.). Frame buffer scan
lines are not contiguous in many resolutions, so software
that renders to the frame buffer must use a skip count to
advance between scan lines. The display controller can
use the graphics memory that lies between scan lines for
the compression buffer. A

ccessing graphics memory

between the end of a scan line and the start of another
can cause display problems. The skip count for all sup-
ported resolutions is shown in Table 4-2.

The graphics memory size is programmed by setting the
graphics memory base address in the memory controller
(see Table 4-15 on page 113). Display drivers communi-
cate with system BIOS about resolution changes, to
ensure that the correct amount of graphics memory is
allocated. Since no mechanism exists to recover system
DRAM from the operating system without rebooting

when

a graphics resolution change requires an increased
amount of graphics memory, the system must be reboo-
ted!

Table 4-2. Display Resolution Skip Counts

Screen

Resolution

Pixel

Depth

Skip

Count

640x480

8 bits

1024

640x480

16 bits

2048

800x600

8 bits

1024

800x600

16 bits

2048

1024x768

8 bits

1024

1024x768

16 bits

2048

1280x1024

8 bits

2048

www.national.com

100

Revision 1.3

Integrated Functions (

Continued

)

odeTM

r
o

ries

4.1.4

Scratchpad RAM

To improve software performance for specific applications,
part of the L1 cache (2, 3, or 4 KB) can be programed to
operate as a scratchpad RAM. This scratchpad RAM
operates at L1 speed which can speed up time-critical
software operations. The scratchpad RAM is taken from
set 0 of the L1 cache. Setting aside this RAM makes the
L1 cache smaller by the scratchpad RAM size. The
scratchpad RAM size is controlled by bits in the GCR reg-
ister (Index B8h, bits[3:2]). See Table 4-1 on page 97.

The scratchpad RAM is usually memory mapped by BIOS
to the upper memory region defined by the GCR register
(Index B8h, bits [1:0]). Once enabled, the valid bits for the
scratchpad RAM will always be true and the scratchpad
RAM locations will never be flushed to external memory.
The scratchpad RAM serves as a general purpose high
speed RAM and as a BLT buffer for the graphics pipeline.

4.1.4.1

Initialization of Scratchpad RAM

The scratchpad RAM must be initialized before the L1
cache is enabled. To initialize the scratchpad RAM after a
cold boot:

Initialize the tags of the scratchpad RAM using the
test registers TR4 and TR5 as outlined in Section
3.3.2.4 "TLB Test Registers". The tags are normally
programmed with an address value equivalent to
GX_BASE (GCR register).

Enable the scratchpad RAM to the desired size (GCR
register). This action will also lock down the tags.

Enable the L1 cache. Section 3.3.2.1 "Control Regis-
ters".

4.1.4.2

Scratchpad RAM Utilization

Use of scratchpad RAM by applications and drivers must
be tightly controlled. To avoid conflicts, application soft-
ware and third-party drivers should generally avoid
accesses to the scratchpad RAM area. The scratchpad

RAM is used by the graphics pipeline BLT buffers, and
National-supplied display drivers and virtualization soft-
ware. Table 4-3 describes the 2 KB, 3 KB, and 4 KB
scratchpad RAM organization used by National developed
software.

The BLT

buffers

are programmed using

CPU_READ/CPU_WRITE instructions described in Sec-
tion 4.1.6 on page 102. If the graphics pipeline or National
software is used, and it is desirable to use scratchpad
RAM by software other than that supplied by National,
please contact your local National Semiconductor techni-
cal support representative.

4.1.4.3

BLT Buffer

Address registers, BitBLT, have been added to the front
end of the L1 cache to enable the graphics pipeline to
directly access a portion of the scratchpad RAM as a BLT
buffer. Table 4-4 summarizes these registers. These regis-
ters do not have default values and must be initialized
before use. Table 4-5 gives the register/bit formats. A 16-
byte line buffer dedicated to the graphics pipeline BLT
operations has been added to minimize accesses to the
L1 cache.

When the BLT operation begins, the graphics pipeline
generates a 32 bit data BLT request to the L1 cache. This
request goes through the BitBLT registers to produce an
address

into

the

scratchpad

RAM.

The

L1_BBx_POINTER

automatically

increments

after each access. A BLT operation generates many
accesses to the BLT buffer to complete a BLT transfer. At
the end of the BLT operation the graphics pipeline gener-
ates a signal to reload the L1_BBx_POINTER register
with the L1_BBx_BASE register. This allows the BLT
buffer to be used over and over again with a minimum of
software overhead.

See Section 4.4 "Graphics Pipeline" on page 125 on pro-
gramming the graphics pipeline to generate a BLT.

Table 4-3. Scratchpad Organization

2 KB Configuration

3 KB Configuration

4 KB Configuration

Description

Offset

Size

Offset

Size

Offset

Size

GX_BASE + 0EE0h

288 bytes

GX_BASE + 0EE0h

288 bytes

GX_BASE + 0EE0h

288 bytes

SMM scratchpad

GX_BASE + 0E60h

128 bytes

GX_BASE + 0E60h

128 bytes

GX_BASE + 0E60h

128 bytes

Driver scratchpad

GX_BASE + 0800h

816 bytes

GX_BASE + 0400h

1328 bytes

GX_BASE + 0h

1840 bytes

BLT Buffer 0

GX_BASE + 0B30h

816 bytes

GX_BASE + 0930h

1328 bytes

GX_BASE + 730h

1840 bytes

BLT Buffer 1

Revision 1.3

101

www.national.com

Integrated Functions (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

Table 4-4. L1 Cache BitBLT Register Summary

Mnemonic Name

Function

L1_BB0_BASE
L1 Cache BitBLT 0 Base Address

Contains the L1 set 0 address to the first byte of BLT Buffer 0.

L1_BB0_POINTER
L1 Cache BitBLT 0 Pointer

Contains the L1 set 0 address offset to the current line of BLT Buffer 0.

L1_BB1_BASE
L1 Cache BitBLT 1 Base Address

Contains the L1 set 0 address to the first byte of BLT Buffer 1.

L1_BB1_POINTER
L1 Cache BitBLT 1 Pointer

Contains the L1 set 0 address offset to the current line of BLT Buffer 1.

Notes: 1. For information on accessing these registers, refer to Section 4.1.6 "CPU_READ/CPU_WRITE Instruc-

tions" on page 102.

2. The L1 cache locations accessed by the BitBLT registers must be enabled as scratchpad RAM prior to

use.

Table 4-5. L1 Cache BitBLT Registers

Bit

Name

Description

L1_BB0_BASE Register (R/W)

Default Value = None

15:12

RSVD

Reserved: Set to 0.

11:4

INDEX

BitBLT 0 Base Index: The index to the starting cache line of set 0 in L1 of BLT Buffer 0.

3:0

BYTE

BitBLT 0 Starting Byte: Determines which byte of the starting line is the beginning of BLT Buffer 0.

L1_BB0_POINTER Register (R/W)

Default Value = None

15:12

RSVD

Reserved: Set to 0.

11:4

INDEX

BitBLT 0 Pointer Index: The index to the current cache line of set 0 in L1 of BLT Buffer 0.

3:0

RSVD

Reserved: Set to 0.

L1_BB1_Base Register (R/W)

Default Value = None

15:12

RSVD

Reserved: Set to 0.

11:4

INDEX

BitBLT 1 Base Index: The index to the starting cache line of set 0 in L1 of BLT Buffer 1.

3:0

BYTE

BitBLT 1 Starting Byte: Determines which byte of the starting line is the beginning of BLT Buffer 1.

L1_BB1_POINTER Register (R/W)

Default Value = None

15:12

RSVD

Reserved: Set to 0.

11:4

INDEX

BitBLT 1 Pointer Index: The index to the current cache line of set 0 in L1 of BLT Buffer 1.

3:0

RSVD

Reserved: Set to 0.

www.national.com

102

Revision 1.3

Integrated Functions (

Continued

)

odeTM

r
o

ries

4.1.5

Display Driver Instructions

While the majority of the GXLV's integrated function inter-
face is memory mapped, a few integrated function regis-
ters are accessed via four GXLV specific instructions.
Table 4-6 shows these instructions.

Adding CPU instructions does not create a compatibility
problem for applications that may depend on receiving
illegal opcode traps. The solution is to make these instruc-
tions generate an illegal opcode trap unless a compatibil-
ity bit is explicitly set. The GXLV processor uses the
scratchpad size field (bits [3:2] in GCR, Index B8h) to
enable or disable all of the graphics instructions.

Note:

If the scratchpad size bits are zero, meaning that
none of the cache is defined as scratchpad, then
hardware will assume that the graphics controller
is not being used and the graphics instructions
will be disabled.

Any other scratchpad size will enable all of the new
instructions. Note that the base address of the memory
map in the GCR register can still be set up to allow access
to the memory controller registers

4.1.6

CPU_READ/CPU_WRITE Instructions

The GXLV processor has several internal registers that
control the BLT buffer and power management circuitry in
the dedicated cache subsystem. To avoid adding addi-
tional instructions to read and write these registers, the
GXLV processor has a general mechanism to access
internal CPU registers with reasonable performance. The
GXLV processor has two special instructions to read and
write CPU registers: CPU_READ and CPU_WRITE. Both
instructions fetch a 32-bit register address from

EBX as

shown in Table 4-6 and Table 4-7

. CPU_WRITE uses EAX

for the source data, and CPU_READ uses

EAX as the

destination. Both instructions always transfer 32 bits of
data.

These instructions work by initiating a special I/O transac-
tion where the high address bit is set. This provides a very
large address space for internal CPU registers.

The BLT buffer base registers define the starting physical
addresses of the BLT buffers located within the dedicated
L1 cache. The dedicated cache can be configured for up
to 4 KB, so 12 address bits are required for each base
address.

Table 4-6. Display Driver Instructions

Syntax

Opcode

Registers

Description

BB0_RESET

0F3A

N/A

Reset the BLT Buffer 0 pointer to the base.

BB1_RESET

0F3B

N/A

Reset the BLT Buffer 1 pointer to the base.

CPU_WRITE

0F3C

EBX = Register Address (see Table 4-7)
EAX = Source Data

Write data to CPU internal register.

CPU_READ

0F3D

EBX = Register Address (see Table 4-7)
EAX = Destination Data

Read data from CPU internal register.

Table 4-7. Address Map for CPU-Access Registers

Register

EBX Address

Description

L1_BB0_BASE

FFFFFF0Ch

BLT Buffer 0 base address (see Table 4-5 on page 101).

L1_BB1_BASE

FFFFFF1Ch

BLT Buffer 1 base address (see Table 4-5 on page 101).

L1_BB0_POINTER

FFFFFF2Ch

BLT Buffer 0 pointer address (see Table 4-5 on page 101).

L1_BB1_POINTER

FFFFFF3Ch

BLT Buffer 1 pointer address (see Table 4-5 on page 101).

PM_BASE

FFFFFF6Ch

Power management base address (see Table 5-3 on page 183).

PM_MASK

FFFFFF7Ch

Power management address mask (see Table 5-3 on page 183).

Revision 1.3

103

www.national.com

Integrated Functions (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

4.2

INTERNAL BUS INTERFACE UNIT

The GXLV processor's internal bus interface unit provides
control and interface functions to the C-Bus and X-Bus.
The functions on C-Bus include: processor core, FPU,
graphics pipeline, and L1 cache. The functions on X-Bus
include: PCI controller, display controller, memory control-
ler, and graphics accelerator. It provides attribute control
for several sections of memory, and plays an important
part in the Virtual VGA function.

The internal bus interface unit performs functions which
previously required the external pins IGNNE# and A20M#.

The internal bus interface unit provides configuration con-
trol for up to 20 different regions within system memory.
This includes a top-of-memory register and 19 config-
urable memory regions in the address space between 640
KB and 1 MB. Each region has separate control for read
access, write access, cacheability, and external PCI mas-
ter access.

In support of VGA emulation, three of the memory regions
are configurable for use by the graphics pipeline and three
I/O ranges can be programmed to generate SMIs.

4.2.1

FPU Error Support

The FERR# (floating point error) and IGNNE# (ignore
numeric error) pins of the 486 microprocessor have been
replaced with an IRQ13 (interrupt request 13) pin. In DOS
systems, FPU errors are reported by the external vector
13. Emulation of this mode of operation is specified by
clearing the NE bit (bit 5) in the CR0 register. If the NE bit
is active, the IRQ13 output of the GXLV processor is
always driven inactive. If the NE bit is cleared, the GXLV
processor drives IRQ13 active when the ES bit (bit 7) in
the FPU Status Register is set high. Software must
respond to this interrupt with an OUT instruction contain-
ing an 8-bit operand to F0h or F1h. When the OUT cycle
occurs, the IRQ13 pin is driven inactive and the FPU
starts ignoring numeric errors. When the ES bit is cleared,
the FPU resumes monitoring numeric errors.

4.2.2

A20M Support

The GXLV processor provides an A20M bit in the
BC_XMAP_1 Register (GX_BASE+ 8004h[21]) to replace
the A20M# pin on the 486 microprocessor. When the
A20M bit is set high, all non-SMI accesses will have
address bit 20 forced to zero. External hardware must do
an SMI trap on I/O locations that toggle the A20M# pin.
The SMI software can then change the A20M bit as
desired.

This will maintain compatibility with software that depends
on wrapping the address at bit 20.

4.2.3

SMI Generation

The Internal Bus Interface Unit can generate SMI inter-
rupts whenever an I/O cycle is in the VGA address ranges
of 3B0h to 3BFh, 3C0h to 3CFh and/or 3D0h to 3DFh. If
an external VGA card is present, the Internal Bus Inter-
face reset values will not generate an interrupt on VGA
accesses. (Refer to Section 4.6.3 "VGA Configuration
Registers" on page 162 for instructions on how to config-
ure the registers to enable the SMI interrupt.)

4.2.4

640 KB to 1 MB Region

There are 19 configurable memory regions located
between 640 KB and 1 MB. Three of the regions, A0000h
to AFFFFh, B0000h to B7FFFh, and B8000h to BFFFFh,
are typically used by the graphics subsystem in VGA emu-
lation mode. Each of the these regions has a VGA control
bit that can cause the graphics pipeline to handle
accesses to that section of memory (see Table 4-37 on
page 163). The area between C0000h and FFFFFh is
divided into 16 KB segments to form the remaining 16
regions. All 19 regions have four control bits to allow any
combination of read-access, write-access, cache, and
external PCI Bus Master access capabilities (see Table 4-
10 on page 106).

www.national.com

104

Revision 1.3

Integrated Functions (

Continued

)

odeTM

r
o

ries

4.2.5

Internal Bus Interface Unit Registers

The Internal Bus Interface Unit maps 100h bytes starting
at GX_BASE+8000h. However only 16 bytes (four 32-bit
registers) are defined. Refer to Section 4.1.2 "Control
Registers" on page 99 for instructions on accessing these
registers.

Table 4-8 summarizes the four 32-bit registers contained
in the Internal Bus Interface Unit and Table 4-9 gives the
register/bit formats.

Table 4-8. Internal Bus Interface Unit Register Summary

GX_BASE+

Memory Offset

Type

Name/Function

Default

Value

8000h-8003h

R/W

BC_DRAM_TOP

Top of DRAM -- Contains the highest available address of system memory not
including the memory that is set aside for graphics memory, which corresponds to
1 GB of memory. The largest possible value for the register is 3FFFFFFFh.

3FFFFFFFh

8004h-8007h

R/W

BC_XMAP_1

Memory X-Bus Map Register 1 (A and B Region Control) -- Contains the region
control of the A and B regions and the SMI controls required for VGA emulation.
PCI access to internal registers and the A20M function are also controlled by this
register.

00000000h

8008h-800Bh

R/W

BC_XMAP_2

Memory X-Bus Map Register 2 (C and D Region Control) -- Contains region con-
trol fields for eight regions in the address range C0h through DCh.

00000000h

800Ch-800Fh

R/W

BC_XMAP_3

Memory X-Bus Map Register 3 (E and F Region Control) -- Contains the region
control fields for memory regions in the address range E0h through FCh.

00000000h

Table 4-9. Internal Bus Interface Unit Registers

Bit

Name

Description

GX_BASE+8000h-8003h

BC_DRAM_TOP Register (R/W)

Default Value = 3FFFFFFFh

31:28

RSVD

Reserved: Set to 0.

27:17

TOP OF

DRAM

Top of DRAM:

000h = Minimum top or 0001FFFFh (128 KB).

7FFh = Maximum top or 0FFFFFFFh (256 MB).

16:0

RSVD

Reserved: Set to 1.

GX_BASE+8004h-8007h

BC_XMAP_1 Register (R/W)

Default Value = 00000000h

31:29

RSVD

Reserved: Set to 0.

GEB8

Graphics Enable for B8 Region: Allow memory R/W operations for address range B8000h to BFFFFh
be directed to the graphics pipeline: 0 = Disable; 1 = Enable. If enabled, the GEB8 region is always non-
cacheable. In the region control field (B8) the cache enable bit (bit 2) is ignored.

(Used for VGA emulation.)

27:24

B8 Region: Region control field for address range B8000h to BFFFFh.

Note: Refer to Table 4-10 on page 106 for decode.

RSVD

Reserved: Set to 0.

PRAE

PCI Register Access Enable: Allow PCI Slave to access internal registers on the X-Bus:
0 = Disable; 1 = Enable.

A20M

Address Bit 20 Mask: Address bit 20 is always forced to a zero except for SMI accesses:
0 = Disable; 1 = Enable.

GEB0

Graphics Enable for B0 Region: Allow memory R/W operations for address range B8000h to BFFFFh
be directed to the graphics pipeline: 0 = Disable; 1 = Enable. If enabled, the GEB0 region is always non-
cacheable. In the region control field (B0) the cache enable bit (bit 2) is ignored.

(Used for VGA emulation.)

19:16

B0 Region: Region control field for address range B0000h to B7FFFh.

Note: Refer to Table 4-10 on page 106 for decode.

SMID

SMID: All I/O accesses for address range 3D0h to 3DFh generate an SMI: 0 = Disable; 1 = Enable.

(Used for VGA virtualization.)

Revision 1.3

105

www.national.com

Integrated Functions (

Continued

)

Ge
odeTM

XL
V
P

r
o

ce
ssor

r
ies

SMIC

SMIC: All I/O accesses for address range 3C0h to 3CFh generate an SMI: 0 = Disable; 1 = Enable.

(Used for VGA virtualization.)

SMIB

SMIB: All I/O accesses for address range 3B0h to 3BFh generate an SMI: 0 = Disable; 1 = Enable

(Used for VGA virtualization.)

12:8

RSVD

Reserved: Set to 0.

XPD

X-Bus Pipeline: The address for the next cycle can be driven on the X-Bus before the completion of the
data phase of the current cycle.

0 = Enable
1 = Disable

GNWS

X-Bus Graphics Pipe No Wait State: Data driven on the X-Bus from the graphics pipeline:
0 = 1 full clock before X_DSX is asserted
1 = On the same clock in which X_RDY is asserted

XNWS

X-Bus No Wait State: Data driven on the X-Bus from the internal bus interface unit:
0 = 1 full clock before X_DSX is asserted
1 = On the same clock in which X_RDY is asserted

GEA

Graphics Enable for A Region: Allow memory R/W operations for address range B8000h to BFFFFh
be directed to the graphics pipeline: 0 = Disable; 1 = Enable. If enabled, the GEA region is always non-
cacheable. In the region control field (A0) the cache enable bit (bit2) is ignored.

(Used for VGA emulation.)

3:0

A0 Region: Region control field for address range A0000h to AFFFFh.

Note: Refer to Table 4-10 on page 106 for decode.

GX_BASE+8008h-800Bh

BC_XMAP_2 Register (R/W)

Default Value = 00000000h