TL H 12323
LM1291
Video
PLL
System
for
Continuous-Sync
Monitors
June 1995
LM1291
Video PLL System for Continuous-Sync Monitors
General Description
The LM1291 is an integrated horizontal time base solution
specifically designed to operate in continuous-sync video
monitors It automatically synchronizes to any H frequency
from 22 kHz to 125 kHz and provides the drive pulse to the
high power deflection circuit
Available sync processing includes a vertical sync separator
and a composite video sync stripper An internal sync selec-
tion scheme gives highest priority to separate H and V sync
then composite sync and finally sync on video no external
switching between sync sources is necessary The LM1291
provides polarity-normalized H HV and V sync outputs
along with logic flags which show the respective input polar-
ities
The design uses an on-chip FVC (Frequency-to-Voltage
Converter) to set the center frequency of the VCO (Voltage-
Controlled Oscillator) This technique allows autosync oper-
ation over the entire frequency range using just one opti-
mized set of external components
The system includes a second phase detector which com-
pensates for storage time variation in the horizontal output
transistor the picture's horizontal position is thus indepen-
dent of temperature and component variance
The LM1291 provides DC control pins for H Drive duty cycle
and flyback phase
Features
Y
Wide continuous autosync range
22 kHz to 125 kHz
(1 5 7) with no component switching or external adjust-
ments
Y
No manufacturing trims required
internal VCO capaci-
tor trimmed on chip
Y
No costly high-precision components needed
Y
Low phase jitter (1 3 ns at 100 kHz)
Y
DC controlled H phase and duty cycle
Y
Video mute pulse for blanking during H frequency
transitions
Y
Input sync prioritization
Y
Clamp pulse position and width control
Y
Continuous clamp pulse output even with no sync input
Y
Resistor-programmable minimum and maximum VCO
frequency
Y
X-ray input disables H drive and mutes video until V
CC
powered down
Y
H drive disabled for V
CC
k
9 5V
Y
Horizontal output transistor protected against accidental
turn-on during flyback
Y
Capacitor-programmable frequency ramping df
VCO
dt
protects H output transistor during scanning mode
changes
Connection Diagram
TL H 12323 1
FIGURE 1
Order Number LM1291N
See NS Package Number N28B
C1995 National Semiconductor Corporation
RRD-B30M115 Printed in U S A
Absolute Maximum Ratings
(Notes 1
3)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
14V
Input Voltage V
DC
Pins 15 23
5V
Pins 4 5
8V
Pins 8 28
10V
Pins 1 9 12 14 16 18
V
CC
Power Dissipation (P
D
)
2 5W
(Above 25 C Derate Based on i
JA
and T
J
)
Thermal Resistance (i
JA
)
50 C W
Junction Temperature (T
J
)
150 C
ESD Susceptibility (Note 5)
2 kV
Storage Temperature
b
65 C to
a
150 C
Lead Temperature (Soldering 10 sec )
265 C
Operating Ratings
(Note 2)
Operating Temperature Range
b
20 C to
a
80 C
Supply Voltage (V
CC
)
10 8V
s
V
CC
s
13 2V
Electrical Characteristics
See Test Circuit
(Figure 2) T
A
e
25 C V
CC
e
12V
Parameter
Conditions
Typical
Limit
Units
(Note 6)
(Note 7)
Supply Current
30
40
mA (max)
Jitter
H Sync frequency
e
100 kHz
1 3
ns p-p
(Note 8)
Minimum composite video
Pin 9 cap coupled (0 01 mF)
0 14
V
PP
(min)
input voltage
sync tip to black level
DC clamp level composite
2 0
V
DC
video input
Clamp charging current
1
mA
composite video input
H HV sync input amplitude (Pin 12)
Cap coupled 10% duty cycle
1 0
V
PP
(min)
V sync input amplitude (Pin 8)
Cap coupled 1% duty cycle
1 0
V
PP
(min)
High level output voltage V
OH
I
OH
e b
100 mA
4 3
4 0
V
DC
(min)
(Pins 2 11 13 17 19)
Low level output voltage V
OL
I
OL
e
1 6 mA
0 25
0 4
V
DC
(max)
(Pins 2 11 13 17 19)
Video Mute low level output
I
OL
e
2 mA
0 4
V
DC
(max)
voltage (Pin 3)
Mute detection voltage
D
V
l
FVC Cap 1
b
FVC Cap 2
l
100
mV
threshold
for Mute Output low
Flyback input threshold (Pin 18)
Positive-going flyback pulse
1 4
V
Under-voltage lockout (Pin 7)
V
CC
below threshold
9 5
V
H Drive Output open (unlatched)
Frequency to voltage gain
22 kHz
s
f
H
s
125 kHz
0 047
V kHz
VCO gain constant
f
VCO
e
100 kHz
1 34
c
10
5
Rad s V
PD1 Phase Detector gain constant
f
VCO
e
100 kHz
130
f
VCO
e
60 kHz
78 1
m
A Radian
f
VCO
e
22 kHz
28 6
Frequency to voltage linearity
22 kHz
s
f
H
s
125 kHz
1 0
%
VCO linearity
22 kHz
s
f
VCO
s
125 kHz
1 0
%
2
Electrical Characteristics
See Test Circuit
(Figure 2) T
A
e
25 C V
CC
e
12V (Continued)
Parameter
Conditions
Typical
Limit
Units
(Note 6)
(Note 7)
H Drive duty cycle control
DC input 0V 4V 30% 70%
0 1
T
H
V
gain
allowed
H Drive Phase control gain
(Note 9)
47
V
PD1 Phase detector leakage current
1
m
A (max)
a
VCO input bias current (Pin 28)
H Drive low level output voltage
I
OL
e
100 mA
0 8
V (max)
(Pin 20)
H Drive EN low level input voltage
H Drive output active
0 8
V (max)
(Pin 15)
H Drive EN high level input voltage
H Drive output open (unlatched)
2 0
V (min)
(Pin 15)
X-ray Shutdown threshold voltage
Above threshold
1 72
1 65
V (min)
(Pin 16)
H Drive Output Open (Latched)
1 8
V(max)
H HV Sync out
H HV in vs Comp Video in
32
ns
propagation delay change
Clamp Pulse width
(back porch) R
SET
e
15k V
SET
e
0V
0 4
m
s
(back porch) R
SET
e
15k V
SET
e
1 5V
1 4
m
s
(sync tip) R
SET
e
15k V
SET
e
4V
0 6
m
s
Clamp Pulse Delay
(back porch) Trailing edge H HV Sync In
0 1
m
s
to leading edge clamp pulse
(sync tip) Leading edge H HV Sync In
0 025 T
H
s
to leading edge clamp pulse
Internal Ref voltage at pin 6
No load
8 2
V
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur
Note 2
Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits For guaranteed specifications
and test conditions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some performance characteristics
may degrade when the device is not operated under the listed test conditions
Note 3
All voltages are measured with respect to GND unless otherwise specified
Note 4
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
Jmax
i
JA
and the ambient temperature T
A
The maximum
allowable power dissipation at any elevated temperature is P
D
e
(T
Jmax
b
T
A
) i
JA
or the number given in the Absolute Maximum Ratings whichever is lower For
this device T
Jmax
e
150 C The typical thermal resistance (i
JA
) of these parts when board mounted follow LM1291N 50 C W
Note 5
Human Body model 100 pF capacitor discharged through a 1 5 kX resistor
Note 6
Typicals are at T
A
e
T
J
e
25 C and represent most likely parametric norm
Note 7
Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level)
Note 8
Measured with HP 53310A Modulation Domain Analyzer 50 ms sample window
Note 9
Phase limits
b
0 15
k
w
k
0 35
b
t
DFB
T
H
J
expressed as a fraction of the horizontal period T
H
where t
DFB
is the horizontal output transistor turn-off
delay from the rising edge of H Drive to the FBP peak A positive phase value represents a phase lead of the FBP peak with reference to the leading edge of H
sync
3
Test Circuit
TLH12323
2
FIGURE
2
4
Block Diagram
TL H 12323 3
FIGURE 3
Pin Descriptions
See
Figures 4 through 15 for input and output schematics
Pin 1 - CLAMP CNTL
This low-impedance current-mode
input pin is internally biased to 2V The direction of current
sets the pulse position (back porch or sync-tip) while the
current magnitude sets the pulse width In a typical applica-
tion a control voltage of 0V 4V is applied to this pin
through a 15 kX resistor A voltage below 2V positions the
pulse on the back porch of the horizontal sync pulse and
decreasing voltage narrows the pulse A voltage above 2V
sets the pulse on the H sync-tip (slightly delayed from the
leading edge) and increasing voltage narrows the pulse At
the boundary of the switchover between the two modes
there is a narrow region of uncertainty resulting in oscilla-
tion which should be no problem in most applications
When there is no H sync in sync-tip mode the clamp pulse
is generated by the VCO at the frequency preset by pin 5
(f
MIN
) This feature is intended for use in On Screen Display
systems
Pin 2 - CLAMP PULSE
Active-low clamp pulse output See
Figure 4 for the output schematic
Pin 3 - VIDEO MUTE
This NPN open-collector output pro-
duces an active-low pulse when triggered by a step change
of H sync frequency See
Figure 5 for the output schematic
Pin 4 - f
MAX
A resistor from this pin to ground sets the
upper frequency limit of the VCO f
MAX
is approximately
1 8
c
10
9
(R
MAX
a
500)
Hz
Pin 5 - f
MIN
A resistor from this pin to ground sets the lower
frequency limit of the VCO f
MIN
is approximately
7 5
c
10
3
a
5 6
c
10
8
(R
MIN
a
500)
Hz
Pin 6 - V
REF
CAP
This is the decoupling pin for the internal
8 2V reference It should be decoupled to pin 21 (GND) via
a short path with a cap of at least 470 mF
Pin 7 - V
CC
12V nominal power supply pin This pin should
be decoupled to pin 21 (GND) via a short path with a cap of
at least 47 mF
Pin 8 - V SYNC IN
This pin accepts AC-coupled V sync of
either polarity The pin is internally biased at 5 2V its input
resistance is approximately 50 kX For best noise immunity
a resistor of 2 kX or less should be connected from the
input side of the coupling cap to ground See
Figure 6 for
the input schematic
Pin 9 - COMP VIDEO IN
The composite video sync stripper
is active only when no signal is present at pin 12 (H HV IN)
The signal to pin 9 must have negative-going sync tips
which are at least 0 14V below black level For best noise
immunity a resistor of 2 kX or less should be connected
from the input side of the coupling cap to ground See
Fig-
ure 7 for the input schematic
Pin 10 - H HV CAP
A capacitor is connected from this pin
to ground for detecting the polarity and existence of H HV
sync at pin 12
5
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