TL H 6750

LM1893LM2893

Carrier-Current

Transceiver

April 1995

LM1893 LM2893 Carrier-Current Transceiver

General Description

Carrier-current systems use the power mains to transfer in-
formation between remote locations This bipolar carrier-
current chip performs as a power line interface for half-du-
plex (bi-directional) communication of serial bit streams of
virtually any coding In transmission a sinusoidal carrier is
FSK modulated and impressed on most any power line via a
rugged on-chip driver In reception a PLL-based demodula-
tor and impulse noise filter combine to give maximum range
A complete system may consist of the LM1893 a COPS

controller and discrete components

Features

Noise resistant FSK modulation

User-selected impulse noise filtering

Up to 4 8 kBaud data transmission rate

Strings of 0's or 1's in data allowed

Sinusoidal line drive for low RFI

Output power easily boosted 10-fold

50 to 300 kHz carrier frequency choice

TTL and MOS compatible digital levels

Regulated voltage to power logic

Drives all conventional power lines

Applications

Energy management systems

Home convenience control

Inter-office communication

Appliance control

Fire alarm systems

Security systems

Telemetry

Computer terminal interface

Typical Application

TL H 6750 � 1

FIGURE 1 Block diagram of carrier

current chip with a complement of discrete components making a complete

125 kHz f

DATA

360 Baud transceiver Use caution with this circuit

dangerous line voltage is present

BI-LINE

and COPS

are trademarks of National Semiconductor Corp

Carrier-Current Transceivers are also called Power Line Carrier (PLC) transceivers

C1995 National Semiconductor Corporation

RRD-B30M115 Printed in U S A

Absolute Maximum Ratings

If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications

Supply voltage

30 V

Voltage on pin 12

55 V

Voltage on pin 10 (Note 1)

41 V

Voltage on pins 5 and 17

40 V

5 6 V DC zener current

100 mA

Junction temperature

transmit mode

150 C

receive mode

125 C

Electro-Static Discharge (120 pF 1500X)

1KV

Maximum continuous dissipation T

25 C

plastic DIP N (Note 2)

transmit mode

1 66 W

receive mode

1 33 W

Operating ambient temp range

40 to 85 C

Storage temperature range

65 to 150 C

Lead temp soldering 7 seconds

260 C

Note

Absolute maximum ratings indicate limits beyond

which damage to the device may occur Electrical specifica-
tions are not ensured when operating the device above
guaranteed limits but below absolute maximum limits but
there will be no device degradation

General Electrical Characteristics

(Note 3) The test conditions are V

18V and F

125 kHz unless otherwise noted

Test

Design

Limit

Parameter

Conditions

Typical

Limit

Units

(Note 4)

(Note 5)

5 6 V Zener voltage V

Pin 11 I

2 mA

5 6

5 2

V min

5 9

V max

5 6 V Zener resistance R

Pin 11 R

10 mAbV

1 mA) (10 mAb1 mA)

Carrier I O peak survivable

Pin 10 discharge 1 mF cap charged to V

V max

transient voltage V

thru

Carrier I O clamp voltage V

Pin 10 I

10 mA RX mode

V min

2N2222 diode pin 8 to 9

V max

Carrier I O clamp resistance R

Pin 10 I

10 mA

TX RX low input voltage V

Pin 5

1 8

0 8

V max

TX RX high input voltage V

Pin 5 (Note 9)

2 2

2 8

V min

TX RX low input current I

Pin 5 at 0 8 V

A min

A max

TX RX high input current I

Pin 5 at 40 V

A min

A max

RXbTX switch-over time T

Time to develop 63% of full current drive thru pin 10

TXbRX switch-over time T

1 bit time T

1 (2F

DATA

) Time T

is user

bit

controlled with C

see Apps Info

ICO initial accuracy of F

TX mode R

6 65 kX C

560 pF

125

113

kHz min

) 2

137

kHz max

ICO temperature coefficient of F

TX or RX mode (F

OMAX

OMIN

) (T

JMAX

JMIN

)

100

PPM C

Temperature drift of F

TX or RX mode b40

JMAX

2 0

5 0

% max

Transmitter Electrical Characteristics

(Note 3) The test conditions are V

18 V and F

125 kHz

unless otherwise noted The transmit center frequency is F

FSK low is F

and FSK high is F

Test

Design

Limit

Parameter

Conditions

Typical

Limit

Units

(Note 4)

(Note 5)

Supply voltage V

range

Meets test 17 spec at T

25 C and

V min

14V bF

18V ) F

18V

0 01

V max

24V bF

18V ) F

18V

0 01

Total supply current I

Pin 15 Pin 12 high I

is I

through

mA max

pin 15 and the average current I

ODC

of the

Carrier I O through pin 10

Carrier I O output current I

100X load on pin 10

mApp min

Carrier I O lower swing limit V

ALC

Pin 10 Set internally be ALC

4 7

4 0

V min

2N2222 diode pin 8 to 9

5 7

V max

THD of I

(Note 6)

Q of 10 tank driving 10X line

0 6

5 0

% max

100X load no tank

5 5

% max

FSK deviation F

) ( F

4 4

3 7

% min

5 2

% max

Data In low input voltage V

Pin 17

1 7

0 8

V max

Data In high input voltage V

Pin 17 (Note 9)

2 1

2 8

V min

Data In low input current I

Pin 17 at 0 8 V

A min

A max

Data In high input current I

Pin 17 at 40 V

A min

A max

Receiver Electrical Characteristics

(Note 3) The test conditions are V

18 V F

125 kHz

2 2%

deviation FSK F

DATA

2 4 kHz V

100 mVpp in the receive mode unless otherwise noted

Test

Design

Limit

Parameter

Conditions

Typical

Limit

Units

(Note 4)

(Note 5)

Supply voltage V

range

Functional receiver (Note 7)

13 5

V min

V max

Supply current I

is pin 15 (V

) plus pin 10

mA min

(Carrier I O) current 2 4 kX Pin 13 to GND

mA max

Carrier I O input resistance R

Pin 10

19 5

kX min

kX max

Max data rate F

Functional receiver (Note 7) C

100 pF

4 8

2 4

kBaud

0X no tank

2 4 kHze4 8 kBaud

PLL capture range F

100 pF R

0 X

% min

PLL lock range F

100 pF R

0 X

% min

Receiver input sensitivity S

For a functional receiver (Note 8)
Referred to chip side (pin 10)

1 8

RMS

of the line-coupling XFMR F

50 kHz

2 0

RMS

300 kHz

1 4

RMS

Referred to line side of XFMR

0 26

RMS

(assuming a 7 07 1 XFMR) F

50 kHz

0 29

RMS

300 kHz

0 20

RMS

Tolerable input dc voltage offset

Pin 10 lower than pin 15 by V

INDC

0 1

V max

range V

INDC

Data Out breakdown voltage

Pin 12 leakage I

20 mA

V min

Data Out low output V

Pin 12 sat voltage at I

2 mA

0 15

0 4

V max

Impulse noise filter current I

Pin 13 charge and discharge current

A min

A max

Offset hold cap bias voltage V

Pin 6

2 0

1 3

V min

3 5

V max

Offset hold capacitor max drive

Pin 6 V(pin 3)bV(pin 4)e

250 mV

A min

current I

MCM

A max

Offset hold bias current I

OHB

Pin 6 TX mode Bias pin 6 as it self-

0 5

nA min

biased during test 31

nA max

Phase comparator current I

Bias pins 3 and 4 at 8 5 V

100

A min

I(pin 3) a I(pin 4) TX mode

200

A max

Phase detector output resistance

Pins 3 and 4

kX min

(V 100mAbV 50mA) (50mA)

kX max

Phase detector demodulated output

Pin 3 to 4 measured after filtering

100

mVpp min

voltage V

out the 2F

component

180

mVpp max

Fast offset cancel voltage ``window''

PIN3

PIN4

WINDOW

DC offset

0 95

0 70

V V min

-to-V

ratio V

Drive for

1 mA pin 6 current

1 20

V V max

Power supply rejection PSRR

0 1 mF PSRR e CMRR 120 Hz

dB min

Note 1

More accurately the maximum voltage allowed on pin 10 is V

and V

ranges from 41 to 50V Also transients may reach above 60V see the transient

peak voltage characteristic curve

Note 2

The maximum power dissipation rating should be derated for device operation above 25 C to insure that the junction temperature remains below the

maximum rating Use a i

of 75 C W for the N package using a socket in still air (which is the worst case) Consult the Application Information section for more

detail

Note 3

The boldface values apply over the full junction temperature range for the specified supply voltage range All other numbers apply at T

25 C Pin

numbers refer to LM1893 LM2893 tested by shorting Carrier In to Carrier Out and testing it as an LM1893

Note 4

Guaranteed and 100% production tested

Note 5

Guaranteed (but not 100% production tested) over the temperature and supply voltage ranges These limits are not used to calculate outgoing quality

levels

Note 6

Total harmonic distortion is measured using THD

RMS

(all components at or above 2F

)

RMS

(fundamental)

Note 7

Receiver function is defined as the error-free passage of 1 cycle of 50% duty-cycle 2 4 kHz square-wave data (2 sequential 208 mS bits) with the first bit

being a ``1 '' All of the data transitions (edges) must fall within

10% (

20 8 ms) of their noise-free positions RX time delay is minimized by using no impulse noise

filter cap C

for this test

Note 8

During the sensitivity check note 7 requirements are followed with these exceptions (1) data rate F

DATA

1 2 kHz (2) all of the data transitions must fall

within

20% (

41 6 ms) of their noise-free positions and (3) a time-domain filter capacitor (C

) is used The time delay of C

bit or 208 ms (C

approximately 6200 pF)

Note 9

For TTL compatibility use a pull-up resistor to increase min V

to above 2 8 V

Электронный компонент: LM1893