LM2642
Two-Phase Synchronous Step-Down Switching
Controller
General Description
The LM2642 consists of two current mode synchronous
buck regulator controllers with a switching frequency of
300kHz.
The two switching regulator controllers operate 180 out of
phase. This feature reduces the input ripple RMS current,
thereby significantly reducing the required input capacitance.
The two switching regulator outputs can also be paralleled to
operate as a dual-phase single output regulator.
The output of each channel can be independently adjusted
from 1.3 to V
IN
maximum duty cycle. An internal 5V rail is
also available externally for driving bootstrap circuitry.
Current-mode feedback control assures excellent line and
load regulation and a wide loop bandwidth for excellent
response to fast load transients. Current is sensed across
either the Vds of the top FET or across an external current-
sense resistor connected in series with the drain of the top
FET. Current limit is independently adjustable for each chan-
nel.
The LM2642 features analog soft-start circuitry that is inde-
pendent of the output load and output capacitance. This
makes the soft-start behavior more predictable and control-
lable than traditional soft-start circuits.
A PGOOD1 pin is provided to monitor the dc output of
channel 1. Over-voltage protection is available for both out-
puts. A UV-Delay pin is also available to allow delayed shut
off time for the IC during an output under-voltage event.
Features
n
Two synchronous buck regulators
n
180 out of phase operation
n
4.5V to 30V input range
n
Power good function monitors Ch.1
n
37A Shutdown current
n
0.04% (typical) line and load regulation error
n
Current mode control with or without a sense resistor
n
Independent enable/soft-start pins allow simple
sequential startup configuration.
n
Configurable for single output parallel operation. (See
Figure 2).
n
Adjustable cycle-by-cycle current limit
n
Input under-voltage lockout
n
Output over-voltage latch protection
n
Output under-voltage protection with delay
n
Thermal shutdown
n
Self discharge of output capacitors when the regulator is
OFF
n
TSSOP package
Applications
n
Embedded computer systems
n
High end gaming systems
n
Set-top boxes
n
WebPAD
Block Diagram
20046201
May 2003
LM2642
T
wo-Phase
Synchronous
Step-Down
Switching
Controller
2003 National Semiconductor Corporation
DS200462
www.national.com
Connection Diagram
TOP VIEW
20046202
28-Lead TSSOP (MTC)
Order Number LM2642MTC
See NS Package Number MTC28
Pin Descriptions
KS1 (Pin 1): The positive (+) Kelvin sense for the internal
current sense amplifier of Channel 1. Use a separate trace to
connect this pin to the current sense point. It should be
connected to VIN as close as possible to the node of the
current sense resistor. When no current-sense resistor is
used, connect as close as possible to the drain node of the
upper MOSFET.
ILIM1 (Pin 2): Current limit threshold setting for Channel 1. It
sinks a constant current of 10 A, which is converted to a
voltage across a resistor connected from this pin to VIN. The
voltage across the resistor is compared with either the VDS
of the top MOSFET or the voltage across the external cur-
rent sense resistor to determine if an over-current condition
has occurred in Channel 1.
COMP1 (Pin 3): Compensation pin for Channel 1. This is the
output of the internal transconductance amplifier. The com-
pensation network should be connected between this pin
and the signal ground, SGND (Pin 8).
FB1 (Pin 4): Feedback input for channel 1. Connect to
VOUT through a voltage divider to set the channel 1 output
voltage.
PGOOD1 (Pin 5): An open-drain power-good output for
Channel 1. It is 'LOW' (low impedance to ground) whenever
the output voltage of Channel 1 falls outside of a +15% to
-9% window. PGOOD1 stays latched in a 'LOW' state during
OVP or UVP on either channel. It will recover to a 'HIGH'
state (high impedance to ground) after a Channel 1 output
under-voltage event (
<
91%) when the output returns to
within 6% of its nominal value. See Operation Descriptions
for details.
UV_DELAY (Pin 6): A capacitor from this pin to ground sets
the delay time for UVP. The capacitor is charged from a 5A
current source. When UV_DELAY charges to 2.3V (typical),
the system immediately latches off. Connecting this pin to
ground will disable the output under-voltage protection.
VLIN5 (Pin 7): The output of an internal 5V LDO regulator
derived from VIN. It supplies the internal bias for the chip and
supplies the bootstrap circuitry for gate drive. Bypass this pin
to signal ground with a minimum of 4.7F capacitor.
SGND (Pin 8): The ground connection for the signal-level
circuitry. It should be connected to the ground rail of the
system.
ON/SS1 (Pin 9): Channel 1 enable pin. This pin is internally
pulled up to one diode drop above VLIN5. Pulling this pin
below 1.2V (open-collector type) turns off Channel 1. If both
ON/SS1 and ON/SS2 pins are pulled below 1.2V, the whole
chip goes into shut down mode. Adding a capacitor to this
pin provides a soft-start feature that minimizes inrush current
and output voltage overshoot.
ON/SS2 (Pin 10): Channel 2 enable pin. See the description
for Pin 9, ON/SS1. May be connected to ON/SS1 for simul-
taneous startup or for parallel operation.
FB2 (Pin 11): Feedback input for channel 2. Connect to
VOUT through a voltage divider to set the Channel 2 output
voltage.
COMP2 (Pin 12): Compensation pin for Channel 2. This is
the output of the internal transconductance amplifier. The
compensation network should be connected between this
pin and the signal ground SGND (Pin 8).
ILIM2 (Pin 13): Current limit threshold setting for Channel 2.
See ILIM1 (Pin 2).
KS2 (Pin 14): The positive (+) Kelvin sense for the internal
current sense amplifier of Channel 2. See KS1 (Pin 1).
RSNS2 (Pin 15): The negative (-) Kelvin sense for the
internal current sense amplifier of Channel 2. Connect this
pin to the low side of the current sense resistor that is placed
between VIN and the drain of the top MOSFET. When the
Rds of the top MOSFET is used for current sensing, connect
this pin to the source of the top MOSFET. Always use a
separate trace to form a Kelvin connection to this pin.
LM2642
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2
Pin Descriptions
(Continued)
SW2 (Pin 16): Switch-node connection for Channel 2, which
is connected to the source of the top MOSFET of Channel 2.
It serves as the negative supply rail for the top-side gate
driver, HDRV2.
HDRV2 (Pin 17): Top-side gate-drive output for Channel 2.
HDRV is a floating drive output that rides on the correspond-
ing switching-node voltage.
CBOOT2 (Pin 18): Bootstrap capacitor connection. It serves
as the positive supply rail for the Channel 2 top-side gate
drive. Connect this pin to VDD2 (Pin 19) through a diode,
and connect the low side of the bootstrap capacitor to SW2
(Pin16).
VDD2 (Pin 19): The supply rail for the Channel 2 low-side
gate drive. Connected to VLIN5 (Pin 7) through a 4.7
resistor and bypassed to power ground with a ceramic ca-
pacitor of at least 1F. Tie this pin to VDD1 (Pin 24).
LDRV2 (Pin 20): Low-side gate-drive output for Channel 2.
PGND (Pin 21): The power ground connection for both
channels. Connect to the ground rail of the system.
VIN (Pin 22): The power input pin for the chip. Connect to
the positive (+) input rail of the system. This pin must be
connected to the same voltage rail as the top FET drain (or
the current sense resistor when used).
LDRV1 (Pin 23): Low-side gate-drive output for Channel 1.
VDD1 (Pin 24): The supply rail for Channel 1 low-side gate
drive. Tie this pin to VDD2 (Pin 19).
CBOOT1 (Pin 25): : Bootstrap capacitor connection. It
serves as the positive supply rail for Channel 1 top-side gate
drive. See CBOOT2 (Pin 18).
HDRV1 (Pin 26): Top-side gate-drive output for Channel 1.
See HDRV2 (Pin 17).
SW1 (Pin 27): Switch-node connection for Channel 1. See
SW2 (Pin16).
RSNS1 (Pin 28): The negative (-) Kelvin sense for the
internal current sense amplifier of Channel 1. See RSNS2
(Pin 15).
LM2642
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3
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltages from the indicated pins to SGND/PGND:
VIN, ILIM1, ILIM2, KS1, KS2
-0.3V to 32V
SW1, SW2, RSNS1, RSNS2
-0.3 to (V
IN
+
0.3)V
FB1, FB2, VDD1, VDD2
-0.3V to 6V
PGOOD, COMP1, COMP2, UV
Delay
-0.3V to (VLIN5
+0.3)V
ON/SS1, ON/SS2 (Note 2)
-0.3V to (VLIN5
+0.6)V
CBOOT1 to SW1, CBOOT2 to SW2
-0.3V to 7V
LDRV1, LDRV2
-0.3V to
(VDD+0.3)V
HDRV1 to SW1, HDRV2 to SW2
-0.3V
HDRV1 to CBOOT1, HDRV2 to
CBOOT2
+0.3V
Power Dissipation (T
A
= 25C),
(Note 3)
1.1W
Ambient Storage Temperature
Range
-65C to +150C
Soldering Dwell Time, Temperature
(Note 4)
Wave
Infrared
Vapor Phase
4 sec, 260C
10sec, 240C
75sec, 219C
ESD Rating (Note 5)
2kV
Operating Ratings
(Note 1)
VIN (VLIN5 tied to VIN)
4.5V to 5.5V
VIN (VIN and VLIN5 separate)
5.5V to 30V
Junction Temperature
-40C to +125C
Electrical Characteristics
Unless otherwise specified, V
IN
= 15V, GND = PGND = 0V, VLIN5 = VDD1 = VDD2. Limits appearing in boldface type apply
over the specified operating junction temperature range, (-20C to +125C, if not otherwise specified). Specifications appearing
in plain type are measured using low duty cycle pulse testing with T
A
= 25C (Note 6), (Note 7). Min/Max limits are guaranteed
by design, test, or statistical analysis.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
System
V
OUT
/V
OUT
Load Regulation
VIN = 15V, V
compx
= 0.5V to 1.5V
0.04
%
V
OUT
/V
OUT
Line Regulation
5.5V
VIN 30V, V
compx
=1.25V
0.04
%
V
FB1_FI2
Feedback Voltage
5.5V
VIN 30V
1.215
1.238
1.260
V
0C to 125C
1.217
1.259
-40C to 125C
1.212
1.261
I
VIN
Input Supply Current
V
ON_SSx
>
2V
5.5V
VIN 30V
1.0
2.0
mA
Shutdown (Note 8)
V
ON_SS1
= V
ON_SS2
= 0V
37
110
A
VLIN5
VLIN5 Output Voltage
IVLIN5 = 0 to 25mA,
5.5V
VIN 30V
4.70
5
5.30
V
-40C to 125C
4.68
5.30
V
CLos
Current Limit
Comparator Offset
(VILIMX -VRSNSX)
2
7.0
mV
I
CL
Current Limit Sink
Current
9
10
11
A
-40C to 125C
8.67
11
I
ss_SC1
,
I
ss_SC2
Soft-Start Source
Current
V
ON_ss1
= V
ON_ss2
= 1.5V (on)
0.5
2
5.0
A
I
ss_SK1
,
I
ss_SK2
Soft-Start Sink Current
V
ON_ss1
= V
ON_ss2
= 2V
2
5.2
10
A
V
ON_SS1
,
V
ON_SS2
Soft-Start On Threshold
0.7
1.12
1.4
V
V
SSTO
Soft-Start Timeout
Threshold
(Note 9)
3.3
V
I
sc_uvdelay
UV_DELAY Source
Current
UV-DELAY = 2V
2
5
9
A
LM2642
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4
Electrical Characteristics
(Continued)
Unless otherwise specified, V
IN
= 15V, GND = PGND = 0V, VLIN5 = VDD1 = VDD2. Limits appearing in boldface type apply
over the specified operating junction temperature range, (-20C to +125C, if not otherwise specified). Specifications appearing
in plain type are measured using low duty cycle pulse testing with T
A
= 25C (Note 6), (Note 7). Min/Max limits are guaranteed
by design, test, or statistical analysis.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
I
sk_uvdelay
UV_DELAY Sink Current
UV-DELAY = 0.4V
0.2
0.48
1.2
mA
V
UVDelay
UV_DELAY Threshold
Voltage
2.3
V
V
UVP
FB1, FB2, Under
Voltage Protection Latch
Threshold
As a percentage of nominal output
voltage (falling edge)
75
80
86
%
Hysteresis
4
%
V
OVP
V
OUT
Overvoltage
Shutdown Latch
Threshold
As a percentage measured at V
FB1
,
V
FB2
107
113
122
%
V
pwrbad
Regulator Window
Detector Thresholds
(PGOOD1 from High to
Low)
As a percentage of output voltage
86.5
90.3
94.5
%
V
pwrgd
Regulator Window
Detector Thresholds
(PGOOD1 from Low to
High)
91.5
94
97.0
%
S
wx_R
SW1, SW2
ON-Resistance
V
SW1
= V
SW2
= 2V
420
480
535
Gate Drive
I
CBOOT
CBOOTx Leakage
Current
V
CBOOT1
= V
CBOOT2
= 7V
10
nA
I
SC_DRV
HDRVx and LDRVx
Source Current
V
CBOOT1
= V
CBOOT2
= 5V, VSWx=0V,
HDRVx=LDRVx=2.5V
0.5
A
I
sk_HDRV
HDRVx Sink Current
V
CBOOTx
= VDDx = 5V, V
SWx
= 0V,
HDRVX = 2.5V
0.8
A
I
sk_LDRV
LDRVx Sink Current
V
CBOOTx
= VDDx = 5V, V
SWx
= 0V,
LDRVX = 2.5V
1.1
A
R
HDRV
HDRV1 & 2 Source
On-Resistance
V
CBOOT1
= V
CBOOT2
= 5V,
V
SW1
= V
SW2
= 0V
3.1
HDRV1 & 2 Sink
On-Resistance
1.5
R
LDRV
LDRV1 & 2 Source
On-Resistance
V
CBOOT1
= V
CBOOT2
= 5V,
V
SW1
= V
SW2
= 0V
V
DD1
= V
DD1
= 5V
3.1
LDRV1 & 2 Sink
On-Resistance
1.1
Oscillator
F
osc
Oscillator Frequency
260
300
340
kHz
-40C to 125C
257.5
340
Don_max
Maximum On-Duty Cycle
V
FB1
= V
FB2
= 1V, Measured at pins
HDRV1 and HDRV2
96
98
%
-40C to 125C
95.64
T
on_min
Minimum On-Time
166
ns
SS
OT_delta
HDRV1 and HDRV2
Delta On Time
ON/SS1 = ON/SS2 = 2V
20
150
ns
Error Amplifier
LM2642
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