LM2700
600kHz/1.25MHz, 2.5A, Step-up PWM DC/DC Converter
General Description
The LM2700 is a step-up DC/DC converter with a 3.6A,
80m
internal switch and pin selectable operating fre-
quency. With the ability to produce 500mA at 8V from a
single Lithium Ion battery, the LM2700 is an ideal part for
biasing LCD displays. The LM2700 can be operated at
switching frequencies of 600kHz and 1.25MHz allowing for
easy filtering and low noise. An external compensation pin
gives the user flexibility in setting frequency compensation,
which makes possible the use of small, low ESR ceramic
capacitors at the output. The LM2700 features continuous
switching at light loads and operates with a switching quies-
cent current of 2.0mA at 600kHz and 3.0mA at 1.25MHz. The
LM2700 is available in a low profile 14-lead TSSOP package
or a 14-lead LLP package.
Features
n
3.6A, 0.08
, internal switch
n
Operating input voltage range of 2.2V to 12V
n
Input undervoltage protection
n
Adjustable output voltage up to 17.5V
n
600kHz/1.25MHz pin selectable frequency operation
n
Over temperature protection
n
Small 14-Lead TSSOP or LLP package
Applications
n
LCD Bias Supplies
n
Handheld Devices
n
Portable Applications
n
GSM/CDMA Phones
n
Digital Cameras
Typical Application Circuit
20012301
600 kHz Operation
October 2001
LM2700
600kHz/1.25MHz,
2.5A,
Step-up
PWM
DC/DC
Converter
2001 National Semiconductor Corporation
DS200123
www.national.com
Connection Diagram
Top View
20012304
14-Lead TSSOP or LLP
Ordering Information
Order Number
Package Type
NSC Package Drawing
Supplied As
LM2700MT-ADJ
TSSOP-14
MTC14
94 Units, Rail
LM2700MTX-ADJ
TSSOP-14
MTC14
2500 Units, Tape and Reel
LM2700LD-ADJ
LLP-14
LDA14A
1000 Units, Tape and Reel
LM2700LDX-ADJ
LLP-14
LDA14A
4500 Units, Tape and Reel
Pin Description
Pin
Name
Function
1
V
C
Compensation network connection. Connected to the output of the voltage error amplifier.
2
FB
Output voltage feedback input.
3
SHDN
Shutdown control input, active low.
4
AGND
Analog ground.
5
PGND
Power ground. PGND pins must be connected together directly at the part.
6
PGND
Power ground. PGND pins must be connected together directly at the part.
7
PGND
Power ground. PGND pins must be connected together directly at the part.
8
SW
Power switch input. Switch connected between SW pins and PGND pins.
9
SW
Power switch input. Switch connected between SW pins and PGND pins.
10
SW
Power switch input. Switch connected between SW pins and PGND pins.
11
NC
Pin not connected internally.
12
V
IN
Analog power input.
13
FSLCT
Switching frequency select input. V
IN
= 1.25MHz. Ground = 600kHz.
14
NC
Connect to ground.
LM2700
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2
Block Diagram
20012303
Detailed Description
The LM2700 utilizes a PWM control scheme to regulate the
output voltage over all load conditions. The operation can
best be understood referring to the block diagram and
Figure
1 of the Operation section. At the start of each cycle, the
oscillator sets the driver logic and turns on the NMOS power
device conducting current through the inductor, cycle 1 of
Figure 1 (a). During this cycle, the voltage at the V
C
pin
controls the peak inductor current. The V
C
voltage will in-
crease with larger loads and decrease with smaller. This
voltage is compared with the summation of the SW voltage
and the ramp compensation. The ramp compensation is
used in PWM architectures to eliminate the sub-harmonic
oscillations that occur during duty cycles greater than 50%.
Once the summation of the ramp compensation and switch
voltage equals the V
C
voltage, the PWM comparator resets
the driver logic turning off the NMOS power device. The
inductor current then flows through the schottky diode to the
load and output capacitor, cycle 2 of
Figure 1 (b). The NMOS
power device is then set by the oscillator at the end of the
period and current flows through the inductor once again.
The LM2700 has dedicated protection circuitry running dur-
ing normal operation to protect the IC. The Thermal Shut-
down circuitry turns off the NMOS power device when the
die temperature reaches excessive levels. The UVP com-
parator protects the NMOS power device during supply
power startup and shutdown to prevent operation at voltages
less than the minimum input voltage. The OVP comparator is
used to prevent the output voltage from rising at no loads
allowing full PWM operation over all load conditions. The
LM2700 also features a shutdown mode decreasing the
supply current to 5A.
LM2700
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3
Absolute Maximum Ratings
(Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
IN
12V
SW Voltage
18V
FB Voltage
7V
V
C
Voltage
0.965V
V
C
1.565V
SHDN Voltage (Note 1)
7V
FSLCT (Note 1)
12V
Maximum Junction Temperature
150C
Power Dissipation(Note 3)
Internally Limited
Lead Temperature
300C
Vapor Phase (60 sec.)
215C
Infrared (15 sec.)
220C
ESD Susceptibility (Note 4)
Human Body Model
2kV
Machine Model
200V
Operating Conditions
Operating Junction
Temperature Range
(Note 5)
-40C to +125C
Storage Temperature
-65C to +150C
Supply Voltage
2.2V to 12V
SW Voltage
17.5V
Electrical Characteristics
Specifications in standard type face are for T
J
= 25C and those with boldface type apply over the full Operating Tempera-
ture Range (T
J
= -40C to +125C) Unless otherwise specified. V
IN
=2.2V and I
L
= 0A, unless otherwise specified.
Symbol
Parameter
Conditions
Min
(Note 5)
Typ
(Note 6)
Max
(Note 5)
Units
I
Q
Quiescent Current
FB = 2.2V (Not Switching)
FSLCT = 0V
1.2
2
mA
FB = 2.2V (Not Switching)
FSLCT = V
IN
1.3
2
mA
V
SHDN
= 0V
5
20
A
V
FB
Feedback Voltage
1.2285
1.26
1.2915
V
I
CL
(Note 7)
Switch Current Limit
V
IN
= 2.7V (Note 8)
2.55
3.6
4.3
A
%V
FB
/
V
IN
Feedback Voltage Line
Regulation
2.2V
V
IN
12.0V
0.02
0.07
%/V
I
B
FB Pin Bias Current
(Note 9)
0.5
40
nA
V
IN
Input Voltage Range
2.2
12
V
g
m
Error Amp Transconductance
I = 5A
40
155
290
mho
A
V
Error Amp Voltage Gain
135
V/V
D
MAX
Maximum Duty Cycle
FSLCT = Ground
78
85
%
D
MIN
Minimum Duty Cycle
FSLCT = Ground
15
%
FSLCT = V
IN
30
f
S
Switching Frequency
FSLCT = Ground
480
600
720
kHz
FSLCT = V
IN
1
1.25
1.5
MHz
I
SHDN
Shutdown Pin Current
V
SHDN
= V
IN
0.008
1
A
V
SHDN
= 0V
-0.5
-1
I
L
Switch Leakage Current
V
SW
= 18V
0.02
20
A
R
DSON
Switch R
DSON
(Note 10)
V
IN
= 2.7V, I
SW
= 2A
80
150
m
Th
SHDN
SHDN Threshold
Output High
0.9
0.6
V
Output Low
0.6
0.3
V
UVP
On Threshold
1.95
2.05
2.2
V
Off Threshold
1.85
1.95
2.1
V
JA
Thermal Resistance
(Note 11)
TSSOP, package only
150
C/W
LLP, package only
45
Note 1: This voltage should never exceed V
IN
.
Note 2: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to
be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics.
LM2700
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4
Electrical Characteristics
(Continued)
Note 3: The maximum allowable power dissipation is a function of the maximum junction temperature, T
J
(MAX), the junction-to-ambient thermal resistance,
JA
,
and the ambient temperature, T
A
. See the Electrical Characteristics table for the thermal resistance. The maximum allowable power dissipation at any ambient
temperature is calculated using: P
D
(MAX) = (T
J(MAX)
- T
A
)/
JA
. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown.
Note 4: The human body model is a 100 pF capacitor discharged through a 1.5k
resistor into each pin. The machine model is a 200pF capacitor discharged
directly into each pin.
Note 5: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100% tested
or guaranteed through statistical analysis. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
All limits are used to calculate Average Outgoing Quality Level (AOQL).
Note 6: Typical numbers are at 25C and represent the most likely norm.
Note 7: Duty cycle affects current limit due to ramp generator.
Note 8: Current limit at 0% duty cycle. See TYPICAL PERFORMANCE section for Switch Current Limit vs. V
IN
Note 9: Bias current flows into FB pin.
Note 10: Does not include the bond wires. Measured directly at the die.
Note 11: Refer to National's packaging website for more detailed thermal information and mounting techniques for the LLP and TSSOP packages.
Typical Performance Characteristics
Efficiency vs. Load Current
(V
OUT
= 8V, f
S
= 600 kHz)
Efficiency vs. Load Current
(V
OUT
= 8V, f
S
= 1.25 MHz)
20012326
20012325
Efficiency vs. Load Current
(V
OUT
= 5V, f
S
= 600 kHz)
Efficiency vs. Load Current
(V
OUT
= 12V, f
S
= 600 kHz)
20012334
20012335
LM2700
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