LM5100A/LM5101A
3.0 Amp High Voltage High Side and Low Side Driver
General Description
The LM5100A/LM5101A High Voltage Gate Drivers are de-
signed to drive both the high side and the low side
N-Channel MOSFETs in a synchronous buck or a half bridge
configuration. The floating high-side driver is capable of
operating with supply voltages up to 100V. The outputs are
independently controlled with CMOS input thresholds
(LM5100A) or TTL input thresholds (LM5101A). An inte-
grated high voltage diode is provided to charge the high side
gate drive bootstrap capacitor. A robust level shifter operates
at high speed while consuming low power and providing
clean level transitions from the control logic to the high side
gate driver. Under-voltage lockout is provided on both the
low side and the high side power rails. This device is avail-
able in the standard SOIC-8 pin and the LLP-10 pin pack-
ages.
Features
n
3.0A Sink/Source current gate drive
n
Drives both a high side and low side N-Channel
MOSFET
n
Independent high and low driver logic inputs (TTL for
LM5101A or CMOS for LM5100A)
n
Bootstrap supply voltage range up to 118V DC
n
Fast propagation times (25 ns typical)
n
Drives 1000 pF load with 8 ns rise and fall times
n
Excellent propagation delay matching (3 ns typical)
n
Supply rail under-voltage lockouts
n
Low power consumption
n
Pin compatible with HIP2100/HIP2101 and
LM5100/LM5101
Typical Applications
n
Current Fed push-pull converters
n
Half and Full Bridge power converters
n
Synchronous buck converters
n
Two switch forward power converters
n
Forward with Active Clamp converters
Package
n
SOIC-8
n
LLP-10 (4 mm x 4 mm)
Simplified Block Diagram
20124003
FIGURE 1.
March 2005
LM5100A/LM5101A
3.0
Amp
High
V
oltage
High
Side
and
Low
Side
Driver
2005 National Semiconductor Corporation
DS201240
www.national.com
Connection Diagrams
Ordering Information
Ordering Number
Package Type
NSC Package Drawing
Supplied As
LM5100A/01A M
SOIC-8
M08A
Shipped in anti static rails
LM5100A/01A MX
SOIC-8
M08A
2500 shipped as Tape & Reel
LM5100A/01A SD
LLP-10
SDC10A
1000 shipped as Tape & Reel
LM5100A/01A SDX
LLP-10
SDC10A
4500 shipped as Tape & Reel
Pin Description
Pin #
Name
Description
Application Information
SO-8
LLP-10
1
1
V
DD
Positive gate drive supply
Locally decouple to V
SS
using low ESR/ESL capacitor located
as close to IC as possible.
2
2
HB
High side gate driver
bootstrap rail
Connect the positive terminal of the bootstrap capacitor to HB
and the negative terminal to HS. The Bootstrap capacitor
should be place as close to IC as possible.
3
3
HO
High side gate driver output
Connect to gate of high side MOSFET with a short low
inductance path.
4
4
HS
High side MOSFET source
connection
Connect to bootstrap capacitor negative terminal and the
source of the high side MOSFET.
5
7
HI
High side driver control input
The LM5100A inputs have CMOS type thresholds. The
LM5101A inputs have TTL type thresholds. Unused inputs
should be tied to ground and not left open.
6
8
LI
Low side driver control input
The LM5100A inputs have CMOS type thresholds. The
LM5101A inputs have TTL type thresholds. Unused inputs
should be tied to ground and not left open.
7
9
V
SS
Ground return
All signals are referenced to this ground.
8
10
LO
Low side gate driver output
Connect to the gate of the low side MOSFET with a short low
inductance path.
Note: For LLP-10 package, it is recommended that the exposed pad on the bottom of the LM5100A / LM5101A be soldered to ground plane on the PC
board, and the ground plane should extend out from beneath the IC to help dissipate the heat. Pins 5 and 6 have no connection.
20124001
20124002
FIGURE 2.
LM5100A/LM5101A
www.national.com
2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
DD
to V
SS
-0.3V to +18V
V
HB
to V
HS
-0.3V to +18V
LI or HI Inputs
-0.3V to V
DD
+0.3V
LO Output
-0.3V to V
DD
+0.3V
HO Output
V
HS
-0.3V to V
HB
+0.3V
V
HS
to V
SS
-1V to +100V
V
HB
to V
SS
118V
Junction Temperature
+150C
Storage Temperature Range
-55C to +150C
ESD Rating HBM (Note 2)
2 KV
Recommended Operating
Conditions
V
DD
+9V to +14V
HS
-1V to 100V
HB
V
HS
+8V to V
HS
+14V
HS Slew Rate
<
50 V/ns
Junction Temperature
-40C to +125C
Electrical Characteristics
Specifications in standard typeface are for T
J
= +25C, and those in boldface type apply over the full operating junction tem-
perature range. Unless otherwise specified, V
DD
= V
HB
= 12V, V
SS
= V
HS
= 0V, No Load on LO or HO .
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SUPPLY CURRENTS
I
DD
V
DD
Quiescent Current
LI = HI = 0V (LM5100A)
0.1
0.2
mA
LI = HI = 0V (LM5101A)
0.25
0.4
I
DDO
V
DD
Operating Current
f = 500 kHz
2.0
3
mA
I
HB
Total HB Quiescent Current
LI = HI = 0V
0.06
0.2
mA
I
HBO
Total HB Operating Current
f = 500 kHz
1.6
3
mA
I
HBS
HB to V
SS
Current, Quiescent
V
HS
= V
HB
= 100V
0.1
10
A
I
HBSO
HB to V
SS
Current, Operating
f = 500 kHz
0.4
mA
INPUT PINS
V
IL
Input Voltage Threshold (LM5100A)
Rising Edge
4.5
5.4
6.3
V
V
IL
Input Voltage Threshold (LM5101A)
Rising Edge
1.3
1.8
2.3
V
V
IHYS
Input Voltage Hysteresis (LM5101A)
50
mV
V
IHYS
Input Voltage Hysteresis (LM5100A)
500
mV
R
I
Input Pulldown Resistance
100
200
400
k
UNDER VOLTAGE PROTECTION
V
DDR
V
DD
Rising Threshold
6.0
6.8
7.4
V
V
DDH
V
DD
Threshold Hysteresis
0.5
V
V
HBR
HB Rising Threshold
5.7
6.6
7.1
V
V
HBH
HB Threshold Hysteresis
0.4
V
BOOT STRAP DIODE
V
DL
Low-Current Forward Voltage
I
VDD-HB
= 100 A
0.52
0.85
V
V
DH
High-Current Forward Voltage
I
VDD-HB
= 100 mA
0.80
1.0
V
R
D
Dynamic Resistance
I
VDD-HB
= 100 mA
1.0
1.65
LO GATE DRIVER
V
OLL
Low-Level Output Voltage
I
LO
= 100 mA
0.12
0.25
V
V
OHL
High-Level Output Voltage
I
LO
= -100 mA,
V
OHL
= V
DD
V
LO
0.24
0.45
V
I
OHL
Peak Pullup Current
V
LO
= 0V
3.0
A
I
OLL
Peak Pulldown Current
V
LO
= 12V
3.0
A
HO GATE DRIVER
V
OLH
Low-Level Output Voltage
I
HO
= 100 mA
0.12
0.25
V
V
OHH
High-Level Output Voltage
I
HO
= -100 mA
V
OHH
= V
HB
V
HO
0.24
0.45
V
I
OHH
Peak Pullup Current
V
HO
= 0V
3.0
A
I
OLH
Peak Pulldown Current
V
HO
= 12V
3.0
A
LM5100A/LM5101A
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3
Electrical Characteristics
(Continued)
Specifications in standard typeface are for T
J
= +25C, and those in boldface type apply over the full operating junction tem-
perature range. Unless otherwise specified, V
DD
= V
HB
= 12V, V
SS
= V
HS
= 0V, No Load on LO or HO .
Symbol
Parameter
Conditions
Min
Typ
Max
Units
HO GATE DRIVER
THERMAL RESISTANCE
JA
Junction to Ambient
SOIC-8
170
C/W
LLP-10 (Note 3)
40
Switching Characteristics
Specifications in standard typeface are for T
J
= +25C, and those in boldface type apply over the full operating junction tem-
perature range. Unless otherwise specified, V
DD
= V
HB
= 12V, V
SS
= V
HS
= 0V, No Load on LO or HO.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LM5100A
t
LPHL
Lower Turn-Off Propagation Delay (LI
Falling to LO Falling)
20
45
ns
t
HPHL
Upper Turn-Off Propagation Delay (HI
Falling to HO Falling)
20
45
ns
t
LPLH
Lower Turn-On Propagation Delay (LI
Rising to LO Rising)
20
45
ns
t
HPLH
Upper Turn-On Propagation Delay (HI
Rising to HO Rising)
20
45
ns
t
MON
Delay Matching: Lower Turn-On and
Upper Turn-Off
1
10
ns
t
MOFF
Delay Matching: Lower Turn-Off and
Upper Turn-On
1
10
ns
t
RC
, t
FC
Either Output Rise/Fall Time
C
L
= 1000 pF
8
ns
t
R
, t
F
Either Output Fall Time
(3V to 9V)
C
L
= 0.1 F
0.26
s
Either Output Rise Time
(3V to 9V)
C
L
= 0.1 F
0.43
t
PW
Minimum Input Pulse Width that
Changes the Output
50
ns
t
BS
Bootstrap Diode Turn-Off Time
I
F
= 100 mA,
I
R
= 100 mA
38
ns
LM5101A
t
LPHL
Lower Turn-Off Propagation Delay (LI
Falling to LO Falling)
22
56
ns
t
HPHL
Upper Turn-Off Propagation Delay (HI
Falling to HO Falling)
22
56
ns
t
LPLH
Lower Turn-On Propagation Delay (LI
Rising to LO Rising)
26
56
ns
t
HPLH
Upper Turn-On Propagation Delay (HI
Rising to HO Rising)
26
56
ns
t
MON
Delay Matching: Lower Turn-On and
Upper Turn-Off
4
10
ns
t
MOFF
Delay Matching: Lower Turn-Off and
Upper Turn-On
4
10
ns
t
RC
, t
FC
Either Output Rise/Fall Time
C
L
= 1000 pF
8
ns
t
R
, t
F
Either Output Fall Time
(3V to 9V)
C
L
= 0.1 F
0.26
s
Either Output Rise Time
(3V to 9V)
C
L
= 0.1 F
0.43
LM5100A/LM5101A
www.national.com
4
Switching Characteristics
(Continued)
Specifications in standard typeface are for T
J
= +25C, and those in boldface type apply over the full operating junction tem-
perature range. Unless otherwise specified, V
DD
= V
HB
= 12V, V
SS
= V
HS
= 0V, No Load on LO or HO.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LM5101A
t
PW
Minimum Input Pulse Width that
Changes the Output
50
ns
t
BS
Bootstrap Diode Turn-Off Time
I
F
= 100 mA,
I
R
= 100 mA
38
ns
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5k
resistor into each pin. 2 KV for all pins except Pin 2, Pin 3 and Pin 4 which are
rated at 1000V.
Note 3: 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power
planes embedded in PCB. See Application Note AN-1187.
Note 4: Min and Max limits are 100% production tested at 25C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National's Average Outgoing Quality Level (AOQL).
Note 5: The
JA
is not a given constant for the package and depends on the printed circuit board design and the operating environment.
LM5100A/LM5101A
www.national.com
5
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