LP3878
Micropower 800mA Low Noise "Ceramic Stable" Voltage
Regulator for Low Voltage Applications
Designed for Use with Very Low ESR Output Capacitors
General Description
The LP3878 is a 800 mA fixed-output voltage regulator
designed to provide high performance and low noise in
applications requiring output voltages between 1.0V and
1.2V.
Output noise can be reduced to 18V (typical) by connecting
an external 10 nF capacitor to the bypass pin.
Using an optimized VIP
TM
(Vertically Integrated PNP) pro-
cess, the LP3878 delivers superior performance:
Ground Pin Current: Typically 5 mA
@
800 mA load, and
180 A
@
100 A load.
Sleep Mode: The LP3878 draws less than 2.0 A quiescent
current when shutdown pin is pulled low.
Precision Output: Guaranteed output voltage accuracy is
1% at room temperature.
Features
n
Standard output voltage: 1.00V
n
Custom voltages available from 1.0V to 1.2V (50 mV
increments)
n
Input voltage: 2.2 to 6.0V
n
1% initial output accuracy
n
Guaranteed 800 mA continuous output current
n
Designed for use with low ESR ceramic capacitors
n
Very low output noise with external capacitor
n
Sense option improves load regulation
n
8 Lead LLP surface mount package
n
<
2.0 A quiescent current in shutdown
n
Low ground pin current at all loads
n
High peak current capability (1200 mA typical)
n
Overtemperature/overcurrent protection
n
0C to +125C junction temperature range
Applications
n
ASIC Power Supplies In:
- Desktops, Notebooks and Graphic Cards
- Set Top Boxes, Printers and Copiers
n
DSP and FPGA Power Supplies
n
SMPS Post-Regulator
Basic Application Circuit
20086803
*Capacitance values shown are minimum required to assure stability, but may be increased without limit. Larger output capacitor provides improved dynamic
response. Output capacitor must meet ESR requirements (see Application Hints).
**Shutdown must be actively terminated (see App. Hints). Tie to INPUT (Pin4) if not used.
VIP
TM
is a trademark of National Semiconductor Corporation.
November 2004
LP3878
Micropower
800mA
Low
Noise
"Ceramic
Stable"
V
oltage
Regulator
for
Low
V
oltage
Applications
Designed
for
Use
with
V
ery
Low
ESR
Output
Capacitors
2004 National Semiconductor Corporation
DS200868
www.national.com
Block Diagram
20086801
LP3878
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2
Connection Diagram
8 Lead LLP Surface Mount Package (SD)
20086850
Top View
See NS Package Number SDC08A
Ordering Information
TABLE 1. Package Marking and Ordering Information
Output Voltage*
Grade
Order Information
Supplied as:
8 Lead LLP
1.0
STD
LP3878SD-1.0
1000 Units on Tape and Reel
1.0
STD
LP3878SDX-1.0
4500 Units on Tape and Reel
* For other voltages between 1.0V and 1.2V, contact National Semiconductor sales office.
Pin Description
PIN
NAME
APPLICATION INFORMATION
1
BYPASS
Optional low noise feature. A small value capacitor connected between
BYPASS and GROUND lowers output noise voltage level (100pF -
10nF).
2
N/C
DO NOT CONNECT. This pin is used for post package test and should
be left floating.
3
GROUND
Device ground.
4
INPUT
Input source voltage.
5
OUTPUT
Regulated output voltage.
6
SENSE
Remote sense. Tie directly to output or remotely at point of load for best
regulation.
7
N/C
No internal connection.
8
SHUTDOWN
Enabled above turn-on threshold voltage. Pull to ground to disable.
LLP
DAP
SUBSTRATE
The exposed die attach pad should be connected to a thermal pad at
ground potential. For additional information on using National
Semiconductor's No Pull Back LLP package, please refer to LLP
application note AN-1187.
LP3878
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3
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range
-65C to +150C
Operating Junction
Temperature
Range
-40C to +125C
Lead Temperature
(Soldering, 5
seconds)
260C
ESD Rating (Note 2)
2 kV
Power Dissipation (Note 3)
Internally Limited
Input Supply Voltage
(Survival)
-0.3V to +16V
Input Supply Voltage
(Operating)
2.2V to 6V
Sense Pin
-0.3V to 6V
Output Voltage
(Survival)
(Note 4)
-0.3V to 6V
I
OUT
(Survival)
Short Circuit
Protected
Input-Output Voltage
(Survival)
(Note 5)
-0.3V to +16V
Electrical Characteristics
Limits in standard typeface are for T
J
= 25C, and limits in boldface type apply over the junction temperature range of 0C to
125C. Unless otherwise specified: V
IN
= 3.3V, I
L
= 1 mA, C
OUT
= 10 F, C
IN
= 4.7 F, V
S/D
= 2V.
Symbol
Parameter
Conditions
Min
(Note 6)
Typical
(Note 7)
Max
(Note 6)
Units
V
O
Output Voltage
Tolerance
-1.0
1.0
%V
NOM
1 mA
<
I
L
<
800 mA
3.0V
V
IN
6V
-2.0
2.0
-3.0
3.0
Output Voltage Line
Regulation
3.0V
V
IN
6V
0.005
0.014
%/V
0.032
V
IN
(min)
Minimum Input
Voltage Required To
Maintain Output
Regulation
I
L
= 800 mA
V
OUT
V
OUT(NOM)
- 1%
2.2
2.75
V
I
GND
Ground Pin Current
I
L
= 100 A
180
200
A
225
I
L
= 200 mA
1
2
mA
2.5
I
L
= 800 mA
5
8
10
I
O
(PK)
Peak Output Current
V
OUT
V
O
(NOM) - 5%
1200
mA
I
O
(MAX)
Short Circuit Current
R
L
= 0 (Steady State)
(Note 8)
1400
e
n
Output Noise Voltage
(RMS)
BW = 100 Hz to 100 kHz
C
BYPASS
= 10 nF
C
BYPASS
= 0
18
85
V(RMS)
Ripple Rejection
f = 1 kHz
70
dB
SHUTDOWN INPUT
V
S/D
S/D Input Voltage
V
H
= O/P ON
1.4
1.6
V
V
L
= O/P OFF
I
IN
2 A
0.1
0.50
I
S/D
S/D Input Current
V
S/D
= 0
0.001
-1
A
V
S/D
= 5V
5
15
LP3878
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4
Electrical Characteristics
(Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply when operating the
device outside of its rated operating conditions.
Note 2: ESD testing was performed using Human Body Model, a 100 pF capacitor discharged through a 1.5 k
resistor. The ESD rating of pin 8 is 1kV.
Note 3: The maximum allowable power dissipation is a function of the maximum junction temperature, T
J
(MAX), the junction-to-ambient thermal resistance,
J-A
,
and the ambient temperature, T
A
. The maximum allowable power dissipation at any ambient temperature is calculated using:
The value
J-A
for the LLP (SD) package is specifically dependent on PCB trace area, trace material, and the number of layers and thermal vias. For improved
thermal resistance and power dissipation for the LLP package, refer to Application Note AN-1187. Exceeding the maximum allowable power dissipation will cause
excessive die temperature, and the regulator will go into thermal shutdown.
Note 4: If used in a dual-supply system where the regulator load is returned to a negative supply, the LP3878 output must be diode-clamped to ground.
Note 5: The output PNP structure contains a diode between the V
IN
and V
OUT
terminals that is normally reverse-biased. Forcing the output above the input will turn
on this diode and may induce a latch-up mode which can damage the part (see Application Hints).
Note 6: Limits are guaranteed through testing, statistical correlation, or design.
Note 7: Typical numbers reperesent the most likely parametric norm for 25C operation.
Note 8: See Typical Performance Characteristics curves.
LP3878
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