LP38842-ADJ
1.5A Ultra Low Dropout Adjustable Linear Regulators
Stable with Ceramic Output Capacitors
General Description
The LP38842-ADJ is a high current, fast response regulator
which can maintain output voltage regulation with minimum
input to output voltage drop. Fabricated on a CMOS process,
the device operates from two input voltages: Vbias provides
voltage to drive the gate of the N-MOS power transistor,
while Vin is the input voltage which supplies power to the
load. The use of an external bias rail allows the part to
operate from ultra low Vin voltages. Unlike bipolar regula-
tors, the CMOS architecture consumes extremely low quies-
cent current at any output load current. The use of an
N-MOS power transistor results in wide bandwidth, yet mini-
mum external capacitance is required to maintain loop sta-
bility.
The fast transient response of these devices makes them
suitable for use in powering DSP, Microcontroller Core volt-
ages and Switch Mode Power Supply post regulators. The
parts are available in the PSOP package.
Dropout Voltage: 115 mV (typ)
@
1.5A load current.
Quiescent Current: 30 mA (typ) at full load.
Shutdown Current: 30 nA (typ) when S/D pin is low.
Precision Reference Voltage: 1.5% room temperature ac-
curacy.
Features
n
Ideal for conversion from 1.8V or 1.5V inputs
n
Designed for use with low ESR ceramic capacitors
n
Ultra low dropout voltage (115mV
@
1.5A typ)
n
0.56V to 1.5V adjustable output range
n
Load regulation of 0.1%/A (typ)
n
30nA quiescent current in shutdown (typ)
n
Low ground pin current at all loads
n
Over temperature/over current protection
n
Available in 8 lead PSOP package
n
-40C to +125C junction temperature range
n
UVLO disables output when V
BIAS
<
3.8V
Applications
n
ASIC Power Supplies In:
- Desktops, Notebooks, and Graphics Cards, Servers
- Gaming Set Top Boxes, Printers and Copiers
n
Server Core and I/O Supplies
n
DSP and FPGA Power Supplies
n
SMPS Post-Regulators
Typical Application Circuit
20117601
* Minimum value required if Tantalum capacitor is used (see Application Hints).
February 2005
LP38842-ADJ
1.5A
Ultra
Low
Dropout
Linear
Regulators
Stable
with
Ceramic
Output
Capacitors
2005 National Semiconductor Corporation
DS201176
www.national.com
Connection Diagram
20117635
PSOP-8, Top View
Pin Description
Pin Name
Description
BIAS
The bias pin is used to provide the low current bias voltage to the chip which operates the internal
circuitry and provides drive voltage for the N-FET.
OUTPUT
The regulated output voltage is connected to this pin.
GND
This is both the power and analog ground for the IC. Note that both pin three and the tab of the
TO-220 and TO-263 packages are at ground potential. Pin three and the tab should be tied together
using the PC board copper trace material and connected to circuit ground.
INPUT
The high current input voltage which is regulated down to the nominal output voltage must be
connected to this pin. Because the bias voltage to operate the chip is provided seperately, the input
voltage can be as low as a few hundered millivolts above the output voltage.
SHUTDOWN
This provides a low power shutdown function which turns the regulated output OFF. Tie to V
BIAS
if
this function is not used.
ADJ
The adjust pin is used to set the regulated output voltage by connecting it to the external resistors R1
and R2 (see Typical Application Circuit).
Ordering Information
Order Number
Package Type
Package Drawing
Supplied As
LP38842MR-ADJ
PSOP-8
MRA08A
95 Units Tape and Reel
LP38842MRX-ADJ
PSOP-8
MRA08A
2500 Units Tape and Reel
Block Diagram
20117624
LP38842-ADJ
www.national.com
2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range
-65C to +150C
Lead Temp. (Soldering, 5 seconds)
260C
ESD Rating
Human Body Model (Note 3)
Machine Model (Note 9)
2 kV
200V
Power Dissipation (Note 2)
Internally Limited
V
IN
Supply Voltage (Survival)
-0.3V to +6V
V
BIAS
Supply Voltage (Survival)
-0.3V to +7V
Shutdown Input Voltage (Survival)
-0.3V to +7V
V
ADJ
-0.3V to +6V
I
OUT
(Survival)
Internally Limited
Output Voltage (Survival)
-0.3V to +6V
Junction Temperature
-40C to +150C
Operating Ratings
V
IN
Supply Voltage
(V
OUT
+ V
DO
) to 5.5V
Shutdown Input Voltage
0 to +5.5V
I
OUT
1.5A
Operating Junction
Temperature Range
-40C to +125C
V
BIAS
Supply Voltage
4.5V to 5.5V
V
OUT
0.56V to 1.5V
Electrical Characteristics
Limits in standard typeface are for T
J
= 25C, and limits in boldface type apply
over the full operating temperature range. Unless otherwise specified: V
IN
= V
O
(NOM) + 1V, V
BIAS
= 4.5V, I
L
= 10 mA,
C
IN
= 10 F CER, C
OUT
= 22 F CER, V
S/D
= V
BIAS
. Min/Max limits are guaranteed through testing, statistical correlation, or
design.
Symbol
Parameter
Conditions
MIN
TYP
(Note 4)
MAX
Units
V
ADJ
Adjust Pin Voltage
10 mA
<
I
L
<
1.5A
V
O
(NOM) + 1V
V
IN
5.5V
4.5V
V
BIAS
5.5V
0.552
0.543
0.56
0.568
0.577
V
I
ADJ
Adjust Pin Bias Current
10 mA
<
I
L
<
1.5A
V
O
(NOM) + 1V
V
IN
5.5V
4.5V
V
BIAS
5.5V
1
A
V
O
/
V
IN
Output Voltage Line Regulation
(Note 6)
V
O
(NOM) + 1V
V
IN
5.5V
0.01
%/V
V
O
/
I
L
Output Voltage Load
Regulation (Note 7)
10 mA
<
I
L
<
1.5A
0.1
0.4
1.1
%/A
V
DO
Dropout Voltage (Note 8)
I
L
= 1.5A
115
175
315
mV
I
Q
(V
IN
)
Quiescent Current Drawn from
V
IN
Supply
10 mA
<
I
L
<
1.5A
30
35
40
mA
V
S/D
0.3V
0.06
1
30
A
I
Q
(V
BIAS
)
Quiescent Current Drawn from
V
BIAS
Supply
10 mA
<
I
L
<
1.5A
2
4
6
mA
V
S/D
0.3V
0.03
1
30
A
UVLO
V
BIAS
Voltage Where
Regulator Output Is Enabled
3.8
V
I
SC
Short-Circuit Current
V
OUT
= 0V
4
A
Shutdown Input
V
SDT
Output Turn-off Threshold
Output = ON
0.7
1.3
V
Output = OFF
0.3
0.7
Td (OFF)
Turn-OFF Delay
R
LOAD
X C
OUT
<<
Td (OFF)
20
s
Td (ON)
Turn-ON Delay
R
LOAD
X C
OUT
<<
Td (ON)
15
I
S/D
S/D Input Current
V
S/D
=1.3V
1
A
V
S/D
0.3V
-1
J-A
Junction to Ambient Thermal
Resistance
PSOP-8 Package (Note 10)
43
C/W
LP38842-ADJ
www.national.com
3
Electrical Characteristics
Limits in standard typeface are for T
J
= 25C, and limits in boldface type apply
over the full operating temperature range. Unless otherwise specified: V
IN
= V
O
(NOM) + 1V, V
BIAS
= 4.5V, I
L
= 10 mA,
C
IN
= 10 F CER, C
OUT
= 22 F CER, V
S/D
= V
BIAS
. Min/Max limits are guaranteed through testing, statistical correlation, or
design. (Continued)
Symbol
Parameter
Conditions
MIN
TYP
(Note 4)
MAX
Units
AC Parameters
PSRR (V
IN
)
Ripple Rejection for V
IN
Input
Voltage
V
IN
= V
OUT
+1V, f = 120 Hz
80
dB
V
IN
= V
OUT
+ 1V, f = 1 kHz
65
PSRR (V
BIAS
)
Ripple Rejection for V
BIAS
Voltage
V
BIAS
= V
OUT
+ 3V, f = 120 Hz
58
V
BIAS
= V
OUT
+ 3V, f = 1 kHz
58
Output Noise Density
f = 120 Hz
1
V/root-Hz
e
n
Output Noise Voltage
V
OUT
= 1.5V
BW = 10 Hz - 100 kHz
150
V (rms)
BW = 300 Hz - 300 kHz
90
Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device
is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics. Specifications do not
apply when operating the device outside of its rated operating conditions.
Note 2: At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink thermal values. If power dissipation
causes the junction temperature to exceed specified limits, the device will go into thermal shutdown.
Note 3: The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin.
Note 4: Typical numbers represent the most likely parametric norm for 25C operation.
Note 5: If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground.
Note 6: Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.
Note 7: Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load.
Note 8: Dropout voltage is defined as the minimum input to output differential required to maintain the output with 2% of nominal value.
Note 9: The machine model is a 220 pF capacitor discharged directly into each pin.
Note 10: For optimum heat dissipation, the ground pad must be soldered to a copper plane or connected using vias to an internal copper plane.
LP38842-ADJ
www.national.com
4
Typical Performance Characteristics
Unless otherwise specified: T
J
= 25C, C
IN
= 10 F CER,
C
OUT
= 22 F CER, C
BIAS
= 1 F CER, S/D Pin is tied to V
BIAS
, V
OUT
= 1.2V, I
L
= 10mA, V
BIAS
= 5V, V
IN
= V
OUT
+ 1V.
V
BIAS
Transient Response
Load Transient Response
20117636
20117637
Load Transient Response
Dropout Voltage Over Temperature
20117638
20117639
V
BIAS
PSRR
V
BIAS
PSRR
20117641
20117651
LP38842-ADJ
www.national.com
5
PDF 
ZIP