LP3927
Cellular/PCS System Power Management IC
General Description
The LP3927 system power management IC is designed for
cellular/PCS handsets as well as other portable systems that
require intelligent power management. Each device contains
five low-dropout linear regulators (LDO's), a reset timer, a
power-up control logic, a general-purpose open drain output
that can be used to light LEDs, and a CMOS rail-to-rail
input/output operational amplifier.
Each linear regulator features an extremely low dropout
voltage of 100 mV (typ) at maximum output current. LDO1
and LDO2 are powered on and off by either the KYBD or the
VEXT pin. LDO3, LDO4 and LDO5 each have its indepen-
dent enable pin. LDO1 and LDO4 are rated at 150 mA each,
LDO2 and LDO5 are rated at 200 mA each and LDO3 is
rated at 100 mA. All LDO's are optimized for low noise and
high isolation.
The open drain output current sink can be programmed up to
150 mA by using an external low cost resistor.
A single supply, low voltage operational amplifier has rail to
rail input and output with 600 kHz of gain-bandwidth product.
Key Specifications
n
3.0V to 5.5V Input Voltage Range
n
Two 200 mA, Two 150 mA and One 100 mA LDO's
n
100 mV typ Dropout Voltage
@
I
MAX
n
150 mA General-Purpose Open-drain programmable
current sink for back light LED
n
Low Voltage Rail to Rail Input/Output Operational
Amplifier
n
28 pin LLP package
Applications
n
Cellular/PCS handsets
n
PDA's, Palmtops, and portable terminals
n
SingleCell Li+ Systems
n
2- or 3- Cell NiMH, NiCd or Alkaline System
Typical Application Circuit
20037901
V
DD1
, V
DD2
and V
DD3
must be tied together externally. Collectively called V
DD
.
August 2002
LP3927
Cellular/PCS
System
Power
Management
IC
2002 National Semiconductor Corporation
DS200379
www.national.com
LP3927 Pin Out Diagram (Top View)
20037902
Output Current Rating and Voltage Options
I
MAX
(mA)
Voltage Options (V)
LDO1
150
1.8, 1.9, 2.5, 2.6*, 2.7
LDO2
200
1.8, 2.85*, 2.9, 3.0
LDO3
100
2.7, 2.8, 2.9
*
, 3.0
LDO4
150
2.7, 2.8, 2.9
*
, 3.0
LDO5
200
2.7, 2.8, 2.9, 3.0
*
* denotes the voltage options that are available currently. For other options, please contact the
National Semiconductor factory sales office/distributors for availability and specifications.
Ordering Information
LP3927 Supplied as
1000 Units, tape and
reel
LP3927 Supplied as
4500 Units, tape and
reel
Standard
LDO delay
Optional
LDO delay
VO1
(V)
VO2
(V)
VO3
(V)
VO4
(V)
VO5
(V)
TOP
MARKING
LP3927ILQ-AH
LP3927ILQX-AH
X
2.6
2.85
2.9
2.9
3.0
3927AH
LP3927ILQ-AJ
LP3927ILQX-AJ
X
3927AJ
For LDO delay options, please refer to Electrical Characteristics Table.
LP3927
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2
Pin Description
Pin
Name
Functional Description
1
VO1
150 mA, LDO1 output pin.
2
EN5
LDO5 enable input.
3
EN4
LDO4 enable input.
4
EN3
LDO3 enable input.
5
RST
Externally pulled high, open drain output to processor/memory reset.
6
IRQ
Externally pulled high, open drain output to processor interrupt indicating KYBD has gone
high.
7
PS_HOLD
Input from the processor to the LP3927. A HIGH indicates a steady supply of power is
granted. Refer to 'Application Hints' section for more detail.
8
KYBD
An active high input signal indicating the keyboard "On/Off" button has been asserted. Refer
to 'Application Hints' section for more detail.
9
D_GND
Digital ground, used primarily for the digital and DAC circuits.
10
VEXT
Active low input indicating a battery charger insertion Refer to 'Application Hints' section for
more detail.
11
BYP
Reference bypass pin.
12
TEST_MODE
Pin used for production testing, factory use only. This pin should be grounded in applications.
13
LED_EN
LED driver enable input.
14
LED
LED driver, drain connection of the LED drive MOSFET.
15
LED_PGM
LED drive current programming pin.
16
OP_AMP_OUT
Operational amplifier output pin.
17
IN-
- input of the Op-Amp.
18
IN+
+ input of the Op-Amp.
19
OP_AMP_V
DD
Power supply pin for Op-Amp.
20
A_GND2
Ground for analog.
21
VO5
200 mA, LDO5 output pin.
22
V
DD3
Input power pin for LDO5. V
DD1
, V
DD2
and V
DD3
must be tied together externally.
23
VO4
150 mA, LDO4 output pin.
24
V
DD2
Input power pin for LDO3 and LDO4. V
DD1
, V
DD2
and V
DD3
must be tied together externally.
25
VO3
100 mA, LDO3 output pin.
26
A_GND1
Ground for analog.
27
VO2
200 mA, LDO2 output pin.
28
V
DD1
Input power pin for LDO1 and LDO2. V
DD1
, V
DD2
and V
DD3
must be tied together externally.
LP3927
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Functional Block Diagram
20037903
LP3927
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4
Absolute Maximum Ratings
(Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
All pins except LED_PGM,
BYP, op amp's inputs & output
-0.3V to 6.0V
OP_AMP_OUT, IN-, IN+
-0.3V to 5.5V
GND to GND SLUG
0.3V
Junction Temperature
150C
Storage Information
-65C to 150C
Soldering Temperature
Pad Temperature
235C
Maximum Power Dissipation (Note 3)
2.6W
ESD (Note 4):
KYBD
4 kV
All other pins
2 kV
Operating Ratings
(Notes 1, 2)
V
DD1
, V
DD2
, V
DD3
, KYBD, OP_AMP_V
DD
3.0V to 5.5V
EN3, EN4, EN5
-0.3V to (V
DD
+ 0.3V)
C
OUT
:
Capacitance
1.0 F to 20.0 F
ESR
0.005
to 0.5
Junction Temperature
-40C to 125C
Operating Temperature
-40C to 85C
Thermal Resistance (Note 5)
JA
(LLP28)
30.8C/W
Maximum Power Dissipation (Note 6)
1.78W
Electrical Characteristics, LDO's
Unless otherwise noted, V
DD
= V
OUT(target)
+ 0.7V, C
IN
(V
DD1
, V
DD2
, V
DD3
) = 4.7 F, C
OUT
(VO1 to VO5) = 2.2 F, C
byp
=
0.1 F. Typical values and limits appearing in normal type apply for T
J
= 25C. Limits appearing in boldface type apply over
the entire junction temperature range for operation, -40C to +85C. (Notes 7, 8)
Symbol
Parameter
Conditions
Typical
Limit
Units
Min
Max
V
DD
Input Voltage Range
V
DD1
, V
DD2
, V
DD3
,KYBD
3.7
3
5.5
V
V
OUT
Output Voltage Tolerance
I
OUT
= I
MAX
/2,
V
DD
= 3.7V
-2
+2
%
Load Regulation
I
OUT
= 100 A to I
MAX
,
V
DD
= 3.7V
-2
+2
%
Line Regulation
V
DD
= V
OUT(target)
+0.7V to 5.5V
I
OUT
= I
MAX
/2
-40
+40
mV
Total Accuracy Error
-3.5
+3.5
%
V
IN
- V
OUT
Dropout Voltage
I
OUT
= I
MAX
(Note 9)
100
170
200
mV
e
N
Output Noise Voltage
I
OUT
= 100 A,
10 Hz
f 100 kHz
27
V
rms
PSRR
Power Supply Ripple
Rejection Ratio
C
IN
= 2.2F, I
OUT
= I
MAX
,
f = 100 Hz
f = 1 kHz
f = 10 kHz
f = 100 kHz
45
45
30
10
dB
Cross Talk
(Note 10)
30
dB
I
Q
Quiescent Current
I
OUT
= 0, PS_HOLD = KYBD = 0
VEXT = V
DD
5
8
A
I
GND
Ground Current
I
OUT1
= I
OUT2
= 1 mA,
LDO3, LDO4, LDO5 OFF
100
200
A
I
OUT1
, I
OUT2
, I
OUT3
, I
OUT4
, I
OUT5
= I
MAX
400
950
I
SC
Short Circuit Current Limit
V
OUT
= 0V
400
% of I
MAX
C
OUT
Output Capacitor
Capacitance
1
20
F
ESR
5
500
m
R
SHUNT
V
O2
- V
O5
Output Shunt
Resistor
70
200
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