TL D 11291
NM93C13C14
256-1024-Bit
Serial
EEPROM
September 1994
NM93C13 C14
256- 1024-Bit Serial EEPROM
General Description
The NM93C13 C14 is 256 1024
respectively
bits of
CMOS electrically erasable memory divided into 16 64 16-
bit registers They are fabricated using National Semicon-
ductor's floating-gate CMOS process for high speed high
reliability and low power The NM93C13 C14 is available in
an 8-pin SO package to save board space
The serial interface of the NM93C13 C14 is MICROWIRE
TM
compatible for simple interface to standard microcontrollers
and microprocessors
There are 7 instructions
Read
Erase Write Enable Erase Erase All Write Write All and
Erase Write Disable
All programming cycles are completely self-timed for simpli-
fied operation The ready busy status is available on the DO
pin to indicate the completion of a programming cycle
Features
Y
Typical active current 400 mA Typical standby current
25 mA
Y
Reliable CMOS floating gate technology
Y
4 5V to 5 5V operation in all modes
Y
MICROWIRE compatible serial I O
Y
Self-timed programming cycle
Y
Device status indication during programming mode
Y
15 years data retention
Y
Endurance 100 000 read write cycles minimum
Y
Packages available 8-pin DIP 8-pin SO
Block Diagram
TL D 11291 1
TRI-STATE
is a registered trademark of National Semiconductor Corporation
MICROWIRE
TM
is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M65 Printed in U S A
Connection Diagrams
Dual-In-Line Package (N)
and 8-Pin SO (M8)
TL D 11291 2
Top View
See NS Package Number
N08E and M08A
Alternate SO Pinout (TM8)
NM93C14 Only
TL D 11291 3
See NS Package M08A
Ordering Information
Commercial Temp Range (0 C to
a
70 C)
Order Number
NM93C13N NM93C14N
NM93C13M8 NM93C14M8
NM93C14TM8
Pin Names
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
Ground
V
CC
Power Supply
2
Absolute Maximum Ratings
(Note 1)
Ambient Storage Temperature
b
65 C to
a
150 C
All Input or Output Voltages
a
6 5V to
b
0 3V
with Respect to Ground
Lead Temp (Soldering 10 sec )
a
300 C
ESD Rating
2000V
Operating Conditions
Ambient Operating Temperature
NM93C13 NM93C14
0 C to
a
70 C
Power Supply
4 5V to 5 5V
DC and AC Electrical Characteristics
V
CC
e
5 0V
g
10% (unless otherwise specified) (Note 2)
Symbol
Parameter
Conditions
Min
Max
Units
I
CC1
Operating Current
CS
e
V
IH
SK
e
1 MHz
4
mA
I
CC3
Standby Current
CS
e
0V
200
m
A
I
IL
Input Leakage
V
IN
e
0V to V
CC
b
10
10
m
A
I
OL
Output Leakage
V
IN
e
0V to V
CC
b
10
10
m
A
V
IL
Input Low Voltage
b
0 1
0 8
V
V
IH
Input High Voltage
2
V
CC
a
1
V
OL1
Output Low Voltage
I
OL
e
2 1 mA
0 4
V
V
OH1
Output High Voltage
I
OH
e b
400 mA
2 4
V
V
OL2
Output Low Voltage
I
OL
e
10 mA
0 2
V
V
OH2
Output High Voltage
I
OH
e b
10 mA
V
CC
b
0 2
f
SK
SK Clock Frequency
1
MHz
t
SKH
SK High Time
(Note 3)
300
ns
t
SKL
SK Low Time
(Note 3)
250
ns
t
SKS
SK Setup Time
50
ns
t
CS
Minimum CS Low Time
250
ns
t
CSS
CS Setup Time
50
ns
t
DH
D0 Hold Time
70
ns
t
DIS
DI Setup Time
100
ns
t
CSH
CS Hold Time
0
ns
t
DIH
DI Hold Time
20
ns
t
PD1
Output Delay to ``1''
500
ns
t
PD0
Output Delay to ``0''
500
ns
t
SV
CS to Status Valid
500
ns
t
DF
CS to DO in TRI-STATE
CS
e
V
IL
100
ns
t
WP
Write Cycle Time
10
ms
Capacitance
(Note 4)
T
A
e
25 C f
e
1 MHz
Symbol
Test
Typ
Max
Units
C
OUT
Output Capacitance
5
pF
C
IN
Input Capacitance
5
pF
AC Test Conditions
Output Load
1 TTL Gate and C
L
e
100 pF
Input Pulse Levels
0 4V to 2 4V
Timing Measurement Reference Level
Input
1V and 2V
Output
0 8V and 2V
Note 1
Stress above those listed under ``Absolute Maximum Ratings'' may cause permanent damage to the device This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied Exposure to absolute
maximum rating conditions for extended periods may affect device reliability
Note 2
100% functional test AC DC parameters sample tested to 0 4% AQL
Note 3
The SK frequency specification specifies a minimum SK clock period of 1 ms therefore in an SK clock cycle t
SKH
a
t
SKL
must be greater than or equal to
1 ms For example if the t
SKL
e
500 ns then the minimum t
SKH
e
500 ns in order to meet the SK frequency specification
Note 4
This parameter is periodically sampled and not 100% tested
3
Functional Description
The NM93C13 C14 have 7 instructions as described below
Note that the MSB of any instruction is a ``1'' and is viewed
as a start bit in the interface sequence For the C13 and C14
the next 8 bits carry the op code and the 6-bit address for
register selection
Read (READ)
The READ instruction outputs serial data on the DO pin
After a READ instruction is received the instruction and ad-
dress are decoded followed by data transfer from the se-
lected memory register into a 16-bit serial-out shift register
A dummy bit (logical 0) precedes the 16-bit data output
string Output data changes are initiated by a low to high
transition of the SK clock
Erase Write Enable (EWEN)
When V
CC
is applied to the part it powers up in the Erase
Write Disable (EWDS) state Therefore all programming
modes must be preceded by an Erase Write Enable
(EWEN) instruction Once an Erase Write Enable instruc-
tion is executed programming remains enabled until an
Erase Write Disable (EWDS) instruction is executed or V
CC
is removed from the part
Erase (ERASE)
The ERASE instruction will program all bits in the specified
register to the logical `1' state CS is brought low following
the loading of the last address bit This falling edge of the
CS pin initiates the self-timed programming cycle
The DO pin indicates the READY BUSY status of the chip if
CS is brought high after a minimum of 500 ns (t
CS
)
DO
e
logical `0' indicates that programming is still in prog-
ress DO
e
logical `1' indicates that the register at the
address specified in the instruction has been erased and
the part is ready for another instruction
Write (WRITE)
The WRITE instruction is followed by 16 bits of data to be
written into the specified address After the last bit of data is
put on the data-in (DI) pin CS must be brought low before
the next rising edge of the SK clock This falling edge of CS
initiates the self-timed programming cycle The DO pin indi-
cates the READY BUSY status of the chip if CS is brought
high after a minimum of 500 ns (t
CS
) DO
e
logical 0 indi-
cates that programming is still in progress DO
e
logical 1
indicates that the register at the address specified in the
instruction has been written with the data pattern specified
in the instruction and the part is ready for another instruc-
tion
Erase All (ERAL)
The ERAL instruction will simultaneously program all regis-
ters in the memory array and set each bit to the logical `1'
state The Erase All cycle is identical to the ERASE cycle
except for the different op-code As in the ERASE mode
the DO pin indicates the READY BUSY status of the chip if
CS is brought high after a minimum of 500 ns (t
CS
) The
ERASE ALL instruction is not required see note below
Write All (WRAL)
The WRAL instruction will simultaneously program all regis-
ters with the data pattern specified in the instruction As in
the WRITE mode the DO pin indicates the READY BUSY
status of the chip if CS is brought high after a minimum of
500 ns (t
CS
)
Erase Write Disable (EWDS)
To protect against accidental data disturb the Erase Write
Disable (EWDS) instruction disables all programming modes
and should follow all programming operations Execution of
a READ instruction is independent of both the EWEN and
EWDS instructions
Note
The NM93C13 C14 devices do not require an `ERASE' or `ERASE ALL' prior to the `WRITE' and `WRITE ALL' instructions The `ERASE' and `ERASE ALL'
instructions are included to maintain compatibility with the NMOS NMC9346
Instruction Set for the NM93C13 and NM93C14
Instruction
SB
Op Code
Address
Data
Comments
READ
1
10
A5 A0
Reads data stored in memory at specified address
EWEN
1
00
11XXXX
Write enable must precede all programming modes
ERASE
1
11
A5 A0
Erase selected register
WRITE
1
01
A5 A0
D15 D0
Writes selected register
ERAL
1
00
10XXXX
Erases all registers
WRAL
1
00
01XXXX
D15 D0
Writes all registers
EWDS
1
00
00XXXX
Disables all programming instructions
4
Timing Diagrams
Synchronous Data Timing
TL D 11291 4
READ
Address bits A5 and A4 become ``don't care'' for NM93C13
TL D 11291 5
EWEN
The NM93C13 and NM93C14 require a minimum of 9 clock cycles
TL D 11291 6
5
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