TL D 12315
NM95MS14
Plug
'n
Play
Front-End
Devices
for
ISA-Bus
Systems
November 1996
NM95MS14
Plug 'n Play Front-End Devices for ISA-Bus Systems
General Description
The NM95MS14 is the smaller of a family of devices de-
signed to provide complete Plug 'n Play Capability for ISA
bus systems The NM95MS14 includes the necessary state
machine logic to manage the Plug 'n Play protocol in addi-
tion to switches for steering Interrupt and DMA requests It
also features a built-in 2k bits of serial EEPROM for storing
the resource data specified in the Plug 'n Play Standard In
addition 4k bits of EEPROM is available for use by other on-
board logic This device provides a ``truly complete'' single-
chip solution for implementing Plug 'n Play on ISA-Bus
Adapter cards The NM95MS14 supports one logical device
with a flexible choice of DMA IRQ selection and I O Chip-
select generation
NM95MS14 is implemented using National's Advanced
CMOS process and operates single power supply The
NM95MS14 is available in a 48-pin TQFP package
Features
Y
Complete implementation of Plug 'n Play standard
Direct interface to ISA bus
Y
Two modes of operation
DMA mode
Extended Interrupt mode
Y
6 or 8 ISA bus interrupt lines and 2 DRQ DACK lines
supported
Y
On-chip EEPROM for resource request table
Y
Additional 4 Kbits of on-chip EEPROM available for ex-
ternal access
Y
24 mA drivers for data outputs
Y
48-pin TQFP
Block Diagram
TL D 12315 1
C1996 National Semiconductor Corporation
RRD-B30M126 Printed in U S A
http
www national com
Connection Diagram
Commercial Temperature Range (0 C to
a
70 C)
TL D 12315 2
Order Number NM95MS14VBH
Signals
Type
Description
SA
k
11 0
l
I
Address inputs from the ISA bus
IORD
I
I O read strobe from the ISA bus
IOWR
I
I O write strobe from the ISA bus
AEN
I
Address Enable from ISA Bus
used in conjunction with DMA
SD
k
7 0
l
I O
Data bus
lower byte
from to the ISA bus
OSC (Note 1)
I
``OSC'' Clock from the ISA bus
used for internal state machines
RSTDRV
I
Reset input from the ISA bus
CS
I
Chip select for Microwire port There should be a pulldown resistor of 4 7k on CS pin if
unused externally or directly connected to GND
SK DI
I
Clock and Data input lines for Microwire bus connection to access a portion (4k) on chip
EEPROM
DO
O
Data output line for the Microwire interface detailed above
IRQOUT
k
5 0
l
O
Connection to ISA bus interrupt request pins On-chip interrupt request(s) may be connected to
any 6 of the ISA IRQ lines
IRQIN
k
1 0
l
I
Interrupt request from on-board logic
DRQin IOCS2
I
DMA request from on-board logic or Programmable chipselect (2) depending on mode
selected
DACKOUT
IOCS3
O
DMA Acknowledge for on-board logic or Programmable chipselect (3) depending on mode
selected
ISADRQ
k
1 0
l
O
Connection for two ISA bus DMA Request lines or additional interrupt request lines depending
on the mode selected
IRQOUT
k
7 6
l
ISADACK
k
1 0
l
I
DMA Acknowledge from the ISA bus or additional address lines depending on the mode
selected
SA
k
13 12
l
IOCS
k
1 0
l
O
Programmable chip selects to address on-board peripheral
Signal name with a `` '' means its an active low signal
Note 1
``OSC'' clock from ISA Bus is fixed at a standard frequency of 14 318 MHz NM95MS14 is designed and tested for 14 318 MHz However the NM95MS14
can handle frequencies up to 24 MHz though it is not 100% tested
http
www national com
2
Pinout Details for the NM95MS14
Mode 00
e
DMA Mode
Mode 01
e
Extended Interrupt Mode
Pin
Pin Name
TQFP
DMA
Ext Intr
PLCC
1
RSTDRV
RSTDRV
47
2
IOCS1
IOCS1
48
3
IOCS0
IOCS0
49
4
IORD
IORD
50
5
IOWR
IOWR
51
6
V
CC
V
CC
52
7
DRQIN
IOCS2
2
8
DACKOUT
IOCS3
3
9
GND
GND
4
10
IRQIN1
IRQIN1
5
11
IRQIN0
IRQIN0
6
12
IRQOUT5
IRQOUT5
7
13
IRQOUT4
IRQOUT4
8
14
IRQOUT3
IRQOUT3
9
15
IRQOUT2
IRQOUT2
10
16
IRQOUT1
IRQOUT1
11
Pin
Pin Name
TQFP
DMA
Ext Intr
PLCC
17
IRQOUT0
IRQOUT0
12
18
ISADRQ0
IRQOUT6
13
19
ISADRQ1
IRQOUT7
15
20
ISADACK0
SA12
16
21
ISADACK1
SA13
17
22
CS
CS
18
23
SK
SK
19
24
SA0
SA0
20
25
SA1
SA1
21
26
SA2
SA2
22
27
SA3
SA3
23
28
SA4
SA4
24
29
GND
GND
25
30
SA5
SA5
26
31
SA6
SA6
28
32
SA7
SA7
29
Pin
Pin Name
TQFP
DMA
Ext Intr
PLCC
33
SA8
SA8
30
34
SA9
SA9
31
35
SA10
SA10
32
36
SA11
SA11
33
37
DI
DI
34
38
DO
DO
35
39
AEN
AEN
36
40
OSC
OSC
37
41
SD0
SD0
38
42
SD1
SD1
39
43
SD2
SD2
41
44
SD3
SD3
42
45
SD4
SD4
43
46
SD5
SD5
44
47
SD6
SD6
45
48
SD7
SD7
46
Note
Mode selection (00 or 01) is done by setting MS bits in the EEPROM configuration register Detailed information about this is described in User's Guide
http
www national com
3
Absolute Maximum Ratings
Ambient Storage Temperature
b
65 C to
a
150 C
All Input or Output Voltages
with Respect to Ground
V
CC
a
1V to
b
0 3V
Lead Temperature
(Soldering 10 seconds)
a
300 C
ESD Rating
2000V Min
Operating Conditions
Ambient Operating Temperature
NM95MS14
0 C to
a
70 C
Positive Power Supply (V
CC
)
4 5V to 5 5V
DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Limits
Units
Min
Typ
Max
(Note 1)
I
CCA
Active Power Supply Current
f
SCL
e
100 kHz
TBD
10 0
mA
I
LI
Input Leakage Current
V
IN
e
GND or V
CC
0 2
1 0
m
A
I
LO
Output Leakage Current
V
OUT
e
GND to V
CC
1 0
m
A
V
IL
Input Low Voltage
b
0 1
0 8
V
V
IH
Input High Voltage
2 0
V
CC
a
1 0
V
V
OL
Output Low Voltage
I
OL
e
24 mA (Note 3)
0 4
V
I
OL
e
2 1 mA (Note 4)
V
OH
Output High Voltage
I
OH
e b
3 mA (Note 3)
2 4
V
I
OH
e b
400 mA (Note 4)
2 4
V
Capacitance
T
A
e a
25 C f
e
1 0 MHz V
CC
e
5V
Symbol
Test
Conditions
Max
Units
C
I O
(Note 2)
Input Output Capacitance
V
I O
e
0V
8
pF
C
IN
(Note 2)
Input Capacitance
V
IN
e
0V
6
pF
C
OUT
(Note 2)
Output Capacitance
V
OUT
e
0V
6
pF
Note 1
Typical values are for T
A
e
25 C and nominal supply voltage (5V)
Note 2
This parameter is periodically sampled and not 100% tested
Note 3
These values are for ISA signals like SD 0 7
IRQx DRQx
Note 4
These values are for card signal like IOCS 0 3
DO(EEPROM)
AC Electrical Characteristics
Symbol
Parameter
Min
Max
Unit
t
AEN
AEN Valid to Command Active
100
ns
t
AC
Address Valid to Command Active
88
ns
t
RVD
Active Read to Valid Data
200
ns
t
AH
Address AEN Hold from Inactive Command
30
ns
t
RDH
Read Data Hold from Inactive Read
5
ns
t
WD
Write Data Valid before Write Active
22
ns
t
WDH
Write Data Hold after Write Inactive
25
ns
t
CSA
Chip Selects Valid from Address Valid
5
25
ns
t
CSC
Chip Selects Valid from Command Active
5
25
ns
t
IDD
Propagation Delay for IRQ DRQ DACK
5
25
ns
http
www national com
4
Timing Diagrams
(1) Timings for ISA Read Write Cycle
TL D 12315 3
(2) Decode Delay for Chipselect Generation
TL D 12315 4
(3) Propagation Delay for IRQ DRQ DACK
TL D 12315 5
http
www national com
5
PDF 
ZIP