TL EE12514
NS486SXF
Optimized
32-Bit
486-Class
Controller
with
On-Chip
Peripherals
for
Embedded
Systems
ADVANCE INFORMATION
February 1997
NS486
TM
SXF Optimized 32-Bit 486-Class Controller
with On-Chip Peripherals for Embedded Systems
General Description
The NS486SXF is a highly integrated embedded system
controller incorporating an Intel486
TM
-class 32-bit proces-
sor all of the necessary System Service Elements and a
set of peripheral I O controllers tailored for embedded con-
trol systems It is ideally suited for a wide variety of applica-
tions running in a segmented protect-mode environment
Key Features
Y
100% compatible with VxWorks
VRTX
QNX
Neu-
trino pSOS
a
TM
and other popular real-time executives
and operating system kernels
Y
Intel486 instruction set compatible (protected mode
only) with optimized performance
Y
CPU includes a 1 Kbyte Instruction Cache
Y
Operation at 25 MHz with 5V supply
Y
Low cost 160-pin PQFP package
Y
Industry standard interrupt controller timers real time
clock UART with IrDA v1 0 (Infrared Data Association)
port
Y
Intel 82365 compatible PCMCIA interface
Y
Protected WATCHDOG
TM
timer
Y
Optimized DRAM Controller (supports two banks up to
8 Mbytes each)
Y
Up to nine versatile programmable chip selects
Y
Glueless interface to ISA peripherals
Y
Arbitration support for auxiliary processor
Y
Four external DMA channels (max transfer rate of 25
MByte sec
25 MHz) support many transfer modes
Y
High performance IEEE 1284 (ECP) Bidirectional
Parallel Port
Y
MICROWIRE
TM
Access bus synchronous serial
interfaces
Y
LCD Controller for an up to 4 grey scale supertwist
Liquid Crystal Displays up to 480 X 320
Y
Reconfigurable I O Up to 29 I O pins can be used as
general purpose bidirectional I O lines
Y
Flexible programmable multilevel power saving modes
maximize power savings
NS486SXF Single-Chip Embedded Controller
TL EE 12514 1
TRI-STATE
is a registered trademark of National Semiconductor Corporation
NS486
TM
WATCHDOG
TM
and MICROWIRE
TM
are trademarks of National Semiconductor Corporation
Intel486
TM
is a trademark of Intel Corporation
QNX
is a registered trademark of QNX Software Systems Inc
VRTX
is a registered trademark of Microtec Research Inc
VxWorks
is a registered trademark of Wind River Systems Inc
pSOSa
TM
is a trademark of Integrated Systems Inc
PowerPack
is a registered trademark of Microtek International
C1996 National Semiconductor Corporation
RRD-B30M27 Printed in U S A
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Table of Contents
1 0 SYSTEM OVERVIEW
1 1 NS486SXF System Overview
1 2 32-bit Processor Core
1 3 System Service Elements
1 3 1 DRAM Controller
1 3 2 DMA Controller
1 3 3 Programmable Interval Timer
1 3 4 WATCHDOG Timer
1 3 5 Interrupt Controller
1 3 6 Real Time Clock Calendar
1 3 7 Power Management Features
1 4 NS486SXF System Bus
1 5 Other On-board Peripherals
1 5 1 Reconfigurable I O Lines
1 5 2 IEEE 1284 Bidirectional Port
1 5 3 PCMCIA Interface
1 5 4 MICROWIRE Access bus Interface
1 5 5 UART Serial Port
1 5 6 LCD Controller
1 6 ICE Support
1 7 Other Issues
2 0 PIN DESCRIPTION TABLES
3 0 DEVICE SPECIFICATIONS
3 1 DC Electrical Specifications 5V
g
5%
3 1 1 Recommended Operating Conditions
3 1 2 Absolute Maximum Ratings (Notes 2 and 3)
3 1 3 Capacitance T
A
e
25 C f
e
1 MHz
3 1 4 DC Characteristics
3 2 General AC Specifications
3 2 1 Power Ramp Times
3 2 2 PWRGOOD and Power Rampdown Timing
3 3 AC Switching Specifications
3 3 1 DRAM Interface Timing Specification
3 3 2 ISA-like Bus Cycles Timing Specification
3 3 3 Ready Feedback Timing Specifications
3 3 4 OSCX1 AC Specification
3 3 5 Peripheral Timing Specifications
3 4 Physical Description
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2
List of Figures
FIGURE 1-1
NS486SXF Internal Resource to Pins Map
FIGURE 1-2
NS486SXF Internal Busses
FIGURE 2-1
NS486SXF Package Pinout Diagram
FIGURE 3-1
Switching Characteristic Measurement Waveforms
FIGURE 3-2
More Switching Specifications
FIGURE 3-3
Power Supply Rise and Fall
FIGURE 3-4
PWGOOD in relation to V
DD
FIGURE 3-5
DRAM Timing Diagram
FIGURE 3-6
ISA-like Bus Timing Diagram
FIGURE 3-7
Ready Feedback Timing Diagram
FIGURE 3-8
TTL Clock Input Timing Diagram
FIGURE 3-9
DMA Controller Read Timing Diagram
FIGURE 3-10
DMA Controller Write Timing Diagram
FIGURE 3-11
PIC Timing Diagram
FIGURE 3-12
Memory Read Timing
FIGURE 3-13
Memory Write Timing Diagram
FIGURE 3-14
I O Read Timing
FIGURE 3-15
I O Write Timing Diagram
FIGURE 3-16
Access bus Timing Diagram
FIGURE 3-17
UART Baud Rate and Infrared Clocks
FIGURE 3-18
UART IRQ Timing
FIGURE 3-19
UART Modem Control Timing
FIGURE 3-20
LCD Controller Timing Diagram
FIGURE 3-21
Testmode Timing Diagram
FIGURE 3-22
Plastic Package Specifications
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List of Tables
TABLE 2-1
Bus Interface Unit Pins
TABLE 2-2
DMA Control Pins
TABLE 2-3
DRAM Control Pins
TABLE 2-4
Power Pins
TABLE 2-5
Reset Logic Pins
TABLE 2-6
Auxiliary Processor Interface Pins
TABLE 2-7
Test Pins
TABLE 2-8
Interrupt Control Pins
TABLE 2-9
Real Time Clock Pins
TABLE 2-10
LCD Interface Pins
TABLE 2-11
Oscillator Pins
TABLE 2-12
HP-SIR UART Pins
TABLE 2-13
PCMCIA pins
TABLE 2-14
IEEE-1284 Port (ECP Mode)
TABLE 2-15
Timer Pins
TABLE 2-16
3-Wire Serial I O Pins
TABLE 2-17
General Purpose Chip Select Pins
TABLE 2-18
Summary of Reconfigurable I O Pins
TABLE 3-1
V
DD
Rise and Fall Times
TABLE 3-2
V
DD
Rampdown vs PWRGOOD
TABLE 3-3
4 Cycle Page Miss Preliminary Specifications
TABLE 3-4
3 Cycle Miss Preliminary Specifications
TABLE 3-5
No Command Delay ISA-like Bus Specifications
TABLE 3-6
One Programmed Command Delay ISA-like Bus Specifications
TABLE 3-7
Ready Signal Timing Specifications
TABLE 3-8
TTL Clock Input Specification
TABLE 3-9
DMA Controller Specifications
TABLE 3-10
PIC Timing Specifications
TABLE 3-11
Parallel Port Compatibility Mode Handshake Timing Values
TABLE 3-12
Parallel Port IEEE 1284 Mode Handshake Timing Values
TABLE 3-13
PCMCIA Memory Read Timing Specifications
TABLE 3-14
Memory Write Timing
TABLE 3-15
PCMCIA I O Read Specifications
TABLE 3-16
PCMCIA I O Write Specifications
TABLE 3-17
Access Bus Timing Specifications
TABLE 3-18
LCD Controller Timing Specifications
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1 0 System Overview
1 1 NS486SXF SYSTEM OVERVIEW
The NS486SXF is a highly integrated embedded system
controller It includes an Intel486-class 32-bit processor all
resources required for the System Service Elements of a
Real-Time Executive and a generous set of peripherals
This ``system-on-a-chip'' is ideal for implementing a wide
variety of embedded applications These include (but are
not limited to) fax machines multifunction peripherals (fax
scanners printers) mobile companions (both organizer and
communicator) television set-top boxes and telephones
(mobile and desktop)
The 32-bit processor core executes all of the Intel486 in-
structions with a similar number of clocks per instruction An
on-board 1 kbyte instruction cache provides for efficient ex-
ecution from ROM Intel486 debug features are supported
The processor has been optimized for operating system
kernels such as VRTX VxWorks pSOS
a
and QNX These
environments only need the `486 protected mode operation
(no real mode or virtual 8086 support) flat or linear memory
addressing (no virtual memory paging) and floating point
execution in software only (no co-processor interface)
In fact the NS486SXF includes all of the System Service
Elements required by a typical kernel including an efficient
DRAM controller that supports page-mode DRAMs for data
cache-like performance a six-channel DMA controller with
two channels supporting data transfers from on-chip periph-
erals (the IEEE 1284 ECP or Extended Capabilities Port
and the LCD controller) and four channels supporting exter-
nal devices such as scanners and print engines three timer
channels (including one configured as a protected WATCH-
DOG Timer) two programmable 8259 interrupt controllers
provide 15 on-chip interrupt sources an industry standard
real time clock and calendar (RTC) with battery backup and
support for comprehensive power management schemes
In addition the NS486SXF also incorporates the key I O
peripherals required for implementing a wide variety of em-
bedded applications an IEEE 1284 Bidirectional Parallel
Port that includes both Host and Slave modes an Intel
82365-compatible PCMCIA controller for one card slot an
industry standard high-performance NS16550-compatible
UART with HP-SIR and IrDA v1 0 infrared option an LCD
panel interface with DMA supported refresh for many of the
standard resolutions an 8254 timer and a general purpose
2- or 3-wire synchronous serial interface for easy interface
to low-cost EEPROMs and other serial peripherals System
expansion is supported with nine programmable Chip Select
(CS) signals and a generic ISA-type bus interface for exter-
nal devices and memory
TL EE 12514 2
FIGURE 1-1 NS486SXF Internal Resource to Pins Map
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