COP888CF
8-Bit CMOS ROM Based Microcontrollers with 4k
Memory and A/D Converter

General Description

The COP888CF ROM based microcontrollers are highly in-
tegrated COP8

Feature core devices with 4k memory and

advanced features including an A/D Converter. These single-
chip CMOS devices are suited for applications requiring a
full featured controller with an 8-bit A/D converter. Pin and
software compatible (different V

range) 16k/32k OTP

(One

Time

Programmable)

versions

are

available

(COP87L88CF Family) for pre-production, and for use with a
range of COP8 software and hardware development tools.

Family features include an 8-bit memory mapped architec-
ture, 10 MHz CKI with 1 µs instruction cycle, two multi-
function 16-bit timer/counters, MICROWIRE/PLUS

serial

I/O, one 8-bit/8-channel A/D converter with prescaler and
both differential and single ended modes, crystal or R/C os-
cillator, two power saving HALT/IDLE modes, idle timer,
MIWU, high current outputs, software selectable I/O options,
WATCHDOG

timer and Clock Monitor, 2.5V to 6.0V opera-

tion and 28/40/44 pin packages.

Devices included in this datasheet are:

Device

Memory

RAM

I/O Pins

Packages

Temperature

COP884CF

4k bytes ROM

128 bytes

28 DIP/SOIC

-40 to +85°C

COP984CF

4k bytes ROM

128 bytes

28 DIP/SOIC

-0 to +70°C

COP888CF

4k bytes ROM

128 bytes

34/38

40 DIP, 44 PLCC

-40 to +85°C

COP988CF

4k bytes ROM

128 bytes

34/38

40 DIP, 44 PLCC

-0 to +70°C

Key Features

A/D converter (8-bit, 8-channel, with prescaler and both
differential and single ended modes)

Two 16-bit timers, each with two 16-bit registers
supporting:

-- Processor Independent PWM mode
-- External Event counter mode
-- Input Capture mode

4 kbytes of on-chip ROM

128 bytes of on-chip RAM

Additional Peripheral Features

Idle Timer

Multi-Input Wake Up (MIWU) with optional interrupts (8)

WATCHDOG and Clock Monitor logic

MICROWIRE/PLUS serial I/O

I/O Features

Memory mapped I/O

Software selectable I/O options (TRI-STATE

Output,

Push-Pull Output, Weak Pull-Up Input, High Impedance
Input)

High current outputs

Packages:

-- 44 PLCC with 38 I/O pins
-- 40 DIP with 34 I/O pins
-- 28 DIP/SO with 22 I/O pins

Schmitt trigger inputs on Port G

CPU/Instruction Set Feature

1 µs instruction cycle time

Ten multi-source vectored interrupts servicing

-- External interrupt with selectable edge
-- Idle Timer T0
-- Two Timers (Each with 2 interrupts)
-- MICROWIRE/PLUS
-- Multi-Input Wake Up
-- Software Trap
-- Default VIS (default interrupt)

Versatile and easy to use instruction set

8-bit Stack Pointer (SP) -- stack in RAM

Two 8-bit Register Indirect Data Memory Pointers (B, X)

Fully Static CMOS

Low current drain (typically

1 µA)

Single supply operation: 2.5V to 6.0V

Temperature ranges: 0°C to +70°C, and
-40°C to +85°C

Development Support

Emulation and OTP devices

Real time emulation and full program debug offered by
MetaLink Development System

COP8

is a trademark of National Semiconductor Corporation.

MICROWIRE

is a trademark of National Semiconductor Corporation.

MICROWIRE/PLUS

is a trademark of National Semiconductor Corporation.

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

WATCHDOG

is a trademark of National Semiconductor Corporation.

iceMASTER

is a trademark of MetaLink Corporation.

September 1999

COP888CF

8-Bit

CMOS

ROM

Based

Microcontrollers

with

Memory

and

A/D

Converter

DS009425

www.national.com

Absolute Maximum Ratings

(Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V

)

Voltage at Any Pin

-0.3V to V

+ 0.3V

Total Current into V

Pin (Source)

100 mA

Total Current out of GND Pin (Sink)

110 mA

Storage Temperature Range

-65°C to +140°C

Note 1: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.

DC Electrical Characteristics 988CF:

0°C

+70°C unless otherwise specified

Parameter

Conditions

Min

Typ

Max

Units

Operating Voltage

988CF

2.5

4.0

998CFH

4.0

6.0

Power Supply Ripple (Note 2)

Peak-to-Peak

0.1 V

Supply Current (Note 3)

CKI = 10 MHz

= 6V, t

= 1 µs

12.5

CKI = 4 MHz

= 6V, t

= 2.5 µs

5.5

CKI = 4 MHz

= 4V, t

= 2.5 µs

2.5

CKI = 1 MHz

= 4V, t

= 10 µs

1.4

HALT Current (Note 4)

= 6V, CKI = 0 MHz

0.7

µA

= 4.0V, CKI = 0 MHz

0.3

µA

IDLE Current

CKI = 10 MHz

= 6V, t

= 1 µs

3.5

CKI = 4 MHz

= 6V, t

= 2.5 µs

2.5

CKI = 1 MHz

= 4.0V, t

= 10 µs

0.7

Input Levels

RESET

Logic High

0.8 V

Logic Low

0.2 V

CKI (External and Crystal Osc. Modes)

Logic High

0.7 V

Logic Low

0.2 V

All Other Inputs

Logic High

0.7 V

Logic Low

0.2 V

Hi-Z Input Leakage

= 6V

-1

µA

Input Pullup Current

= 6V, V

= 0V

-40

-250

µA

G and L Port Input Hysteresis

0.35 V

Output Current Levels

D Outputs

Source

= 4V, V

= 3.3V

-0.4

= 2.5V, V

= 1.8V

-0.2

Sink

= 4V, V

= 1V

= 2.5V, V

= 0.4V

2.0

All Others

Source (Weak Pull-Up Mode)

= 4V, V

= 2.7V

-10

-100

µA

= 2.5V, V

= 1.8V

-2.5

-33

µA

Source (Push-Pull Mode)

= 4V, V

= 3.3V

-0.4

= 2.5V, V

= 1.8V

-0.2

Sink (Push-Pull Mode)

= 4V, V

= 0.4V

1.6

= 2.5V, V

= 0.4V

0.7

TRI-STATE Leakage

= 6.0V

-1

µA

COP888CF

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DC Electrical Characteristics 988CF:

(Continued)

0°C

+70°C unless otherwise specified

Parameter

Conditions

Min

Typ

Max

Units

Allowable Sink/Source

Current per Pin

D Outputs (Sink)

All others

Maximum Input Current

= 25°C

100

without Latchup (Note 7)

RAM Retention Voltage, V

500 ns Rise

and Fall Time (Min)

Input Capacitance

Load Capacitance on D2

1000

Note 2: Rate of voltage change must be less then 0.5 V/ms.

Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.

Note 4: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V

, L and G0G5 configured as

outputs and set high. The D port set to zero. The A/D is disabled. V

REF

is tied to AGND (effectively shorting the Reference resistor). The clock monitor is disabled.

A/D Converter Specifications

= 5V

10% (V

- 0.050V)

Any Input

+ 0.050V)

Parameter

Conditions

Min

Typ

Max

Units

Resolution

Bits

Reference Voltage Input

AGND = 0V

Absolute Accuracy

REF

= V

LSB

Non-Linearity

REF

= V

Deviation from the

LSB

Best Straight Line

Differential Non-Linearity

REF

= V

LSB

Input Reference Resistance

1.6

4.8

Common Mode Input Range (Note 8)

AGND

REF

DC Common Mode Error

LSB

Off Channel Leakage Current

µA

On Channel Leakage Current

µA

A/D Clock Frequency (Note 6)

0.1

1.67

MHz

Conversion Time (Note 5)

A/D Clock

Cycles

Note 5: Conversion Time includes sample and hold time.

Note 6: See Prescaler description.

Note 7: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than V

and the pins will

have sink current to V

when biased at voltages greater than V

(the pins do not have source current when biased at a voltage below V

). The effective resis-

tance to V

is 750

(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.

Note 8: For V

(-)

(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input. The diodes will forward conduct for analog

input voltages below ground or above the V

supply. Be careful, during testing at low V

levels (4.5V), as high level analog inputs (5V) can cause this input diode

to conduct -- especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means
that as long as the analog V

does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 V

to 5 V

input

voltage range will therefore require a minimum supply voltage of 4.950 V

over temperature variations, initial tolerance and loading. The voltage at any analog input

should be -0.3V to V

+0.3V.

COP888CF

www.national.com

Absolute Maximum Ratings

(Note 10)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V

)

Voltage at Any Pin

-0.3V to V

+ 0.3V

Total Current into V

Pin (Source)

100 mA

Total Current out of GND Pin (Sink)

110 mA

Storage Temperature Range

-65°C to +140°C

Note 10: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.

DC Electrical Characteristics 888CF:

-40°C

+85°C unless otherwise specified

Parameter

Conditions

Min

Typ

Max

Units

Operating Voltage

2.5

Power Supply Ripple (Note 11)

Peak-to-Peak

0.1 V

Supply Current (Note 12)

CKI = 10 MHz

= 6V, t

= 1 µs

12.5

CKI = 4 MHz

= 4V, t

= 2.5 µs

2.5

HALT Current (Note 13)

= 6V, CKI = 0 MHz

µA

IDLE Current

CKI = 10 MHz

= 6V, t

= 1 µs

3.5

CKI = 1 MHz

= 4V, t

= 10 µs

0.7

Input Levels

RESET

Logic High

0.8 V

Logic Low

0.2 V

CKI (External and Crystal Osc. Modes)

Logic High

0.7 V

Logic Low

0.2 V

All Other Inputs

Logic High

0.7 V

Logic Low

0.2 V

Hi-Z Input Leakage

= 6V

-2

µA

Input Pullup Current

= 6V, V

= 0V

-40

-250

µA

G and L Port Input Hysteresis

0.35 V

Output Current Levels

D Outputs

Source

= 4V, V

= 3.3V

-0.4

= 2.5V, V

= 1.8V

-0.2

Sink

= 4V, V

= 1V

= 2.5V, V

= 0.4V

2.0

All Others

Source (Weak Pull-Up Mode)

= 4V, V

= 2.7V

-10

-100

µA

= 2.5V, V

= 1.8V

-2.5

-33

µA

Source (Push-Pull Mode)

= 4V, V

= 3.3V

-0.4

= 2.5V, V

= 1.8V

-0.2

Sink (Push-Pull Mode)

= 4V, V

= 0.4V

1.6

= 2.5V, V

= 0.4V

0.7

TRI-STATE Leakage

= 6.0V

-2

µA

Allowable Sink/Source

Current per Pin

D Outputs (Sink)

All others

Maximum Input Current
without Latchup (Note 17)

= 25°C

100

COP888CF

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AC Electrical Characteristics 888CF:

-40°C

+85°C unless otherwise specified

Parameter

Conditions

Min

Typ

Max

Units

Instruction Cycle Time (t

)

Crystal, Resonator

µs

2.5V

2.5

µs

R/C Oscillator

µs

2.5V

7.5

µs

Inputs

SETUP

200

2.5V

500

HOLD

2.5V

150

Output Propagation Delay (Note 14)

= 2.2k, C

= 100 pF

PD1

, t

PD0

SO, SK

0.7

µs

2.5V

1.75

µs

All Others

µs

2.5V

2.5

µs

MICROWIRE Setup Time (t

UWS

)

MICROWIRE Hold Time (t

UWH

)

MICROWIRE Output Propagation Delay (t

UPD

)

220

Input Pulse Width

Interrupt Input High Time

Interrupt Input Low Time

Timer Input High Time

Timer Input Low Time

Reset Pulse Width

µs

Note 14: The output propagation delay is referenced to end of the instruction cycle where the output change occurs.

A/D Converter Specifications

= 5V

10% (V

- 0.050V)

Any Input

+ 0.050V)

Parameter

Conditions

Min

Typ

Max

Units

Resolution

Bits

Reference Voltage Input

AGND = 0V

Absolute Accuracy

REF

= V

LSB

Non-Linearity

REF

= V

Deviation from the

LSB

Best Straight Line

Differential Non-Linearity

REF

= V

LSB

Input Reference Resistance

1.6

4.8

Common Mode Input Range (Note 18)

AGND

REF

DC Common Mode Error

LSB

Off Channel Leakage Current

µA

On Channel Leakage Current

µA

A/D Clock Frequency (Note 16)

0.1

1.67

MHz

Conversion Time (Note 15)

A/D Clock

Cycles

Note 15: Conversion Time includes sample and hold time.

Note 16: See Prescaler description.

COP888CF

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A/D Converter Specifications

(Continued)

Note 17: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than V

and the pins will

have sink current to V

when biased at voltages greater than V

(the pins do not have source current when biased at a voltage below V

). The effective resis-

tance to V

is 750

(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.

Note 18: For V

(-)

(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input. The diodes will forward conduct for analog

input voltages below ground or above the V

supply. Be careful, during testing at low V

levels (4.5V), as high level analog inputs (5V) can cause this input diode

to conduct -- especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means
that as long as the analog V

does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 V

to 5 V

input

voltage range will therefore require a minimum supply voltage of 4.950 V

over temperature variations, initial tolerance and loading. The voltage on any analog input

should be -0.3V to V

+0.3V.

DS009425-26

FIGURE 3. MICROWIRE/PLUS Timing

COP888CF

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Typical Performance Characteristics

(-40°C to +85°C) (Continued)

Pin Descriptions

and GND are the power supply pins.

REF

and AGND are the reference voltage pins for the

on-board A/D converter.

CKI is the clock input. This can come from an R/C generated
oscillator, or a crystal oscillator (in conjunction with CKO).
See Oscillator Description section.

RESET is the master reset input. See Reset Description sec-
tion.

The device contains three bidirectional 8-bit I/O ports (C, G
and L), where each individual bit may be independently con-
figured as an input (Schmitt trigger inputs on ports G and L),
output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these
I/O ports. Each I/O port has two associated 8-bit memory
mapped registers, the CONFIGURATION register and the
output DATA register. A memory mapped address is also re-
served for the input pins of each I/O port. (See the memory
map for the various addresses associated with the I/O ports.)
Figure 4 shows the I/O port configurations. The DATA and
CONFIGURATION registers allow for each port bit to be in-
dividually configured under software control as shown below:

CONFIGURA-

TION

DATA

Port Set-Up

Register

Hi-Z Input

(TRI-STATE Output)

Input with Weak Pull-Up

Push-Pull Zero Output

Push-Pull One Output

PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.

Port L supports Multi-Input Wakeup (MIWU) on all eight pins.
L4 and L5 are used for the timer input functions T2A and
T2B. L0 and L1 are not available on the 44-pin version of the
device, since they are replaced by V

REF

and AGND. L0 and

L1 are not terminated on the 44-pin version. Consequently,
reading L0 or L1 as inputs will return unreliable data with the
44-pin package, so this data should be masked out with user
software when the L port is read for input data. It is recom-
mended that the pins be configured as outputs.

Port L has the following alternate features:

MIWU

MIWU or T2B

MIWU or T2A

MIWU

Port D Source Current

DS009425-35

Port D Sink Current

DS009425-36

DS009425-6

FIGURE 4. I/O Port Configurations

COP888CF

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Pin Descriptions

(Continued)

Port G is an 8-bit port with 5 I/O pins (G0, G2G5), an input
pin (G6), and two dedicated output pins (G1 and G7). Pins
G0 and G2G6 all have Schmitt Triggers on their inputs. Pin
G1 serves as the dedicated WDOUT WatchDog output,
while pin G7 is either input or output depending on the oscil-
lator mask option selected. With the crystal oscillator option
selected, G7 serves as the dedicated output pin for the CKO
clock output. With the single-pin R/C oscillator mask option
selected, G7 serves as a general purpose input pin, but is
also used to bring the device out of HALT mode with a low to
high transition on G7. There are two registers associated
with the G Port, a data register and a configuration register.
Therefore, each of the 5 I/O bits (G0, G2G5) can be indi-
vidually configured under software control.

Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin or general purpose input (R/C clock configu-
ration), the associated bits in the data and configuration reg-
isters for G6 and G7 are used for special purpose functions
as outlined below. Reading the G6 and G7 data bits will re-
turn zeros.

Note that the chip will be placed in the HALT mode by writing
a "1" to bit 7 of the Port G Data Register. Similarly the chip
will be placed in the IDLE mode by writing a "1" to bit 6 of the
Port G Data Register.

Writing a "1" to bit 6 of the Port G Configuration Register en-
ables the MICROWIRE/PLUS to operate with the alternate
phase of the SK clock. The G7 configuration bit, if set high,
enables the clock start up delay after HALT when the R/C
clock configuration is used.

Config Reg.

Data Reg.

CLKDLY

HALT

Alternate SK

IDLE

Port G has the following alternate features:

SI (MICROWIRE

Serial Data Input)

SK (MICROWIRE Serial Clock)

SO (MICROWIRE Serial Data Output)

T1A (Timer T1 I/O)

T1B (Timer T1 Capture Input)

INTR (External Interrupt Input)

Port G has the following dedicated functions:

CKO Oscillator dedicated output or general purpose
input

WDOUT WATCHDOG and/or Clock Monitor dedicated
output.

Port C is an 8-bit I/O port. The 40-pin device does not have
a full complement of Port C pins. The unavailable pins are
not terminated. A read operation for these unterminated pins
will return unpredictable values.

Port I is an 8-bit Hi-Z input port, and also provides the analog
inputs to the A/D converter. The 28-pin device does not have
a full complement of Port I pins. The unavailable pins are not
terminated (i.e. they are floating). A read operation from
these unterminated pins will return unpredictable values.
The user should ensure that the software takes this into ac-
count by either masking out these inputs, or else restricting
the accesses to bit operations only. If unterminated, Port I
pins will draw power only when addressed.

Port D is an 8-bit output port that is preset high when RESET
goes low. The user can tie two or more D port outputs (ex-
cept D2) together in order to get a higher drive.

Note: Care must be exercised with the D2 pin operation. At RESET, the ex-

ternal loads on this pin must ensure that the output voltages stay
above 0.8 V

to prevent the chip from entering special modes. Also

keep the external loading on D2 to less than 1000 pF.

Functional Description

The architecture of the device is modified Harvard architec-
ture. With the Harvard architecture, the control store pro-
gram memory (ROM) is separated from the data store
memory (RAM). Both ROM and RAM have their own sepa-
rate addressing space with separate address buses. The ar-
chitecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.

CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (t

) cycle time.

There are five CPU registers:

A is the 8-bit Accumulator Register

PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.

SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM ad-
dress 06F with reset.

All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC).

PROGRAM MEMORY

Program memory consists of 4096 bytes of ROM. These
bytes may hold program instructions or constant data (data
tables for the LAID instruction, jump vectors for the JID in-
struction, and interrupt vectors for the VIS instruction). The
program memory is addressed by the 15-bit program
counter (PC). All interrupts vector to program memory loca-
tion 0FF Hex.

DATA MEMORY

The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X and SP pointers.

The device has 128 bytes of RAM. Sixteen bytes of RAM are
mapped as "registers" at addresses 0F0 to 0FF Hex. These
registers can be loaded immediately, and also decremented
and tested with the DRSZ (decrement register and skip if
zero) instruction. The memory pointer registers X, SP, and B
are memory mapped into this space at address locations
0FC to 0FE Hex respectively, with the other registers (other
than reserved register 0FF) being available for general us-
age.

The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumula-
tor (A) bits can also be directly and individually tested.

Note: RAM contents are undefined upon power-up.

COP888CF

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Reset

The RESET input when pulled low initializes the microcon-
troller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for Ports L, G, and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is dedi-
cated as the WatchDog and/or Clock Monitor error output
pin. Port D is initialized high with RESET. The PC, PSW, CN-
TRL, ICNTRL, and T2CNTRL control registers are cleared.
The Multi-Input Wakeup registers WKEN, WKEDG, and
WKPNDare cleared. The A/D control register ENAD is
cleared, resulting in the ADC being powered down initially.
The Stack Pointer, SP, is initialized to 06F Hex.

The device comes out of reset with both the WatchDog logic
and the Clock Monitor detector armed, and with both the
WatchDog service window bits set and the Clock Monitor bit
set. The WatchDog and Clock Monitor detector circuits are
inhibited during reset. The WatchDog service window bits
are initialized to the maximum WatchDog service window of
64k t

clock cycles. The Clock Monitor bit is initialized high,

and will cause a Clock Monitor error following reset if the
clock has not reached the minimum specified frequency at
the termination of reset. A Clock Monitor error will cause an
active low error output on pin G1. This error output will con-
tinue until 1632 t

clock cycles following the clock fre-

quency reaching the minimum specified value, at which time
the G1 output will enter the TRI-STATE mode.

The external RC network shown in

Figure 5 should be used

to ensure that the RESET pin is held low until the power sup-
ply to the chip stabilizes.

Oscillator Circuits

The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input fre-
quency is divided down by 10 to produce the instruction
cycle clock (1/t

Figure 6 shows the Crystal and R/C diagrams.

CRYSTAL OSCILLATOR

CKI and CKO can be connected to make a closed loop crys-
tal (or resonator) controlled oscillator.

Table 1 shows the component values required for various
standard crystal values.

R/C OSCILLATOR

By selecting CKI as a single pin oscillator input, a single pin
R/C oscillator circuit can be connected to it. CKO is available
as a general purpose input, and/or HALT restart pin.

Table 2 shows the variation in the oscillator frequencies as
functions of the component (R and C) values.

TABLE 1. Crystal Oscillator Configuration, T

= 25°C

CKI

Freq

Conditions

)

(pF)

(MHz)

3036

= 5V

3036

= 5V

200

100150

0.455

= 5V

TABLE 2. R/C Oscillator Configuration, T

= 25°C

CKI Freq

Instr.

Cycle

Conditions

)

(pF)

(MHz)

(µs)

3.3

2.2 to 2.7

3.7 to 4.6

= 5V

5.6

100

1.1 to 1.3

7.4 to 9.0

= 5V

6.8

100

0.9 to 1.1

8.8 to 10.8

= 5V

Note: 3k

200k

50 pF

200 pF

DS009425-7

5 x Power Supply Rise Time

FIGURE 5. Recommended Reset Circuit

DS009425-8

DS009425-9

FIGURE 6. Crystal and R/C Oscillator Diagrams

COP888CF

www.national.com

Control Registers

CNTRL Register (Address X'00EE)

T1C3

T1C2

T1C1

T1C0

MSEL

IEDG

SL1

SL0

Bit 7

Bit 0

The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:

T1C3

Timer T1 mode control bit

T1C2

Timer T1 mode control bit

T1C1

Timer T1 mode control bit

T1C0

Timer T1 Start/Stop control in timer

modes 1 and 2, T1 Underflow Interrupt
Pending Flag in timer mode 3

MSEL

Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively

IEDG

External interrupt edge polarity select

(0 = Rising edge, 1 = Falling edge)

SL1 & SL0

Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)

PSW Register (Address X'00EF)

T1PNDA

T1ENA

EXPND

BUSY

EXEN

GIE

Bit 7

Bit 0

The PSW register contains the following select bits:

Half Carry Flag

Carry Flag

T1PNDA Timer T1 Interrupt Pending Flag (Autoreload

RA in mode 1, T1 Underflow in Mode 2, T1A
capture edge in mode 3)

T1ENA

Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge

EXPND

External interrupt pending

BUSY

MICROWIRE/PLUS busy shifting flag

EXEN

Enable external interrupt

GIE

Global interrupt enable (enables interrupts)

The Half-Carry flag is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and R/C (Reset
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and R/C instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.

ICNTRL Register (Address X'00E8)

Reserved

LPEN

T0PND

T0EN

µWPND

µWEN

T1PNDB

T1ENB

Bit 7

Bit 0

The ICNTRL register contains the following bits:

Reserved This bit is reserved and must be zero

LPEN

L Port Interrupt Enable (Multi-Input Wakeup/
Interrupt)

T0PND

Timer T0 Interrupt pending

T0EN

Timer T0 Interrupt Enable (Bit 12 toggle)

µWPND

MICROWIRE/PLUS interrupt pending

µWEN

Enable MICROWIRE/PLUS interrupt

T1PNDB

Timer T1 Interrupt Pending Flag for T1B cap-
ture edge

T1ENB

Timer T1 Interrupt Enable for T1B Input cap-
ture edge

T2CNTRL Register (Address X'00C6)

T2C3

T2C2

T2C1

T2C0

T2PNDA

T2ENA

T2PNDB

T2ENB

Bit 7

Bit 0

The T2CNTRL control register contains the following bits:

T2C3

Timer T2 mode control bit

T2C2

Timer T2 mode control bit

T2C1

Timer T2 mode control bit

T2C0

Timer

Start/Stop

control

timer

modes 1 and 2, T2 Underflow Interrupt Pend-
ing Flag in timer mode 3

T2PNDA

Timer T2 Interrupt Pending Flag (Autoreload
RA in mode 1, T2 Underflow in mode 2, T2A
capture edge in mode 3)

T2ENA

Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge

T2PNDB

Timer T2 Interrupt Pending Flag for T2B cap-
ture edge

T2ENB

Timer T2 Interrupt Enable for Timer Underflow
or T2B Input capture edge

Timers

The device contains a very versatile set of timers (T0, T1,
T2). All timers and associated autoreload/capture registers
power up containing random data.

Figure 7 shows a block diagram for the timers.

TIMER T0 (IDLE TIMER)

The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer T0, which is a
16-bit timer. The Timer T0 runs continuously at the fixed rate
of the instruction cycle clock, t

. The user cannot read or

write to the IDLE Timer T0, which is a count down timer.

The Timer T0 supports the following functions:

Exit out of the Idle Mode (See Idle Mode description)

WatchDog logic (See WatchDog description)

Start up delay out of the HALT mode

The IDLE Timer T0 can generate an interrupt when the thir-
teenth bit toggles. This toggle is latched into the T0PND
pending flag, and will occur every 4 ms at the maximum
clock frequency (t

= 1 µs). A control flag T0EN allows the in-

terrupt from the thirteenth bit of Timer T0 to be enabled or
disabled. Setting T0EN will enable the interrupt, while reset-
ting it will disable the interrupt.

TIMER T1 AND TIMER T2

The device has a set of two powerful timer/counter blocks,
T1 and T2. The associated features and functioning of a
timer block are described by referring to the timer block Tx.
Since the two timer blocks, T1 and T2, are identical, all com-
ments are equally applicable to either timer block.

Each timer block consists of a 16-bit timer, Tx, and two sup-
porting 16-bit autoreload/capture registers, RxA and RxB.
Each timer block has two pins associated with it, TxA and
TxB. The pin TxA supports I/O required by the timer block,
while the pin TxB is an input to the timer block. The powerful
and flexible timer block allows the device to easily perform all
timer functions with minimal software overhead. The timer
block has three operating modes: Processor Independent
PWM mode, External Event Counter mode, and Input Cap-
ture mode.

COP888CF

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Timers

(Continued)

The control bits TxC3, TxC2, and TxC1 allow selection of the
different modes of operation.

Mode 1. Processor Independent PWM Mode

As the name suggests, this mode allows the COP888CF to
generate a PWM signal with very minimal user intervention.
The user only has to define the parameters of the PWM sig-
nal (ON time and OFF time). Once begun, the timer block will
continuously generate the PWM signal completely indepen-
dent of the microcontroller. The user software services the
timer block only when the PWM parameters require updat-
ing.

In this mode the timer Tx counts down at a fixed rate of t

Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, RxA and RxB. The very
first underflow of the timer causes the timer to reload from
the register RxA. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register RxB.

The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
timer for PWM mode operation.

Figure 8 shows a block diagram of the timer in PWM mode.

The underflows can be programmed to toggle the TxA output
pin. The underflows can also be programmed to generate in-
terrupts.

Underflows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending flags under software control. Two control en-
able flags, TxENA and TxENB, allow the interrupts from the
timer underflow to be enabled or disabled. Setting the timer
enable flag TxENA will cause an interrupt when a timer un-
derflow causes the RxA register to be reloaded into the timer.
Setting the timer enable flag TxENB will cause an interrupt
when a timer underflow causes the RxB register to be re-
loaded into the timer. Resetting the timer enable flags will
disable the associated interrupts.

Either or both of the timer underflow interrupts may be en-
abled. This gives the user the flexibility of interrupting once
per PWM period on either the rising or falling edge of the
PWM output. Alternatively, the user may choose to interrupt
on both edges of the PWM output.

Mode 2. External Event Counter Mode

This mode is quite similar to the processor independent
PWM mode described above. The main difference is that the
timer, Tx, is clocked by the input signal from the TxA pin. The
Tx timer control bits, TxC3, TxC2 and TxC1 allow the timer to
be clocked either on a positive or negative edge from the
TxA pin. Underflows from the timer are latched into the TxP-
NDA pending flag. Setting the TxENA control flag will cause
an interrupt when the timer underflows.

In this mode the input pin TxB can be used as an indepen-
dent positive edge sensitive interrupt input if the TxENB con-
trol flag is set. The occurrence of a positive edge on the TxB
input pin is latched into the TxPNDB flag.

Figure 9 shows a block diagram of the timer in External
Event Counter mode.

Note: The PWM output is not available in this mode since the TxA pin is being

used as the counter input clock.

Mode 3. Input Capture Mode

The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the in-
put capture mode.

In this mode, the timer Tx is constantly running at the fixed t

rate. The two registers, RxA and RxB, act as capture regis-

DS009425-11

FIGURE 7. Timers

DS009425-13

FIGURE 8. Timer in PWM Mode

DS009425-14

FIGURE 9. Timer in External Event Counter Mode

COP888CF

www.national.com

Timers

(Continued)

ters. Each register acts in conjunction with a pin. The register
RxA acts in conjunction with the TxA pin and the register RxB
acts in conjunction with the TxB pin.

The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin. Control bits,
TxC3, TxC2 and TxC1, allow the trigger events to be speci-
fied either as a positive or a negative edge. The trigger con-
dition for each input pin can be specified independently.

The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag Tx-
ENA allows the interrupt on TxA to be either enabled or dis-
abled. Setting the TxENA flag enables interrupts to be gener-
ated when the selected trigger condition occurs on the TxA
pin. Similarly, the flag TxENB controls the interrupts from the
TxB pin.

Underflows from the timer can also be programmed to gen-
erate interrupts. Underflows are latched into the timer TxC0
pending flag (the TxC0 control bit serves as the timer under-
flow interrupt pending flag in the Input Capture mode). Con-
sequently, the TxC0 control bit should be reset when enter-
ing the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
the TxPNDA and TxC0 pending flags in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.

Figure 10 shows a block diagram of the timer in Input Cap-
ture mode.

TIMER CONTROL FLAGS

The control bits and their functions are summarized below.

TxC3

Timer mode control

TxC2

Timer mode control

TxC1

Timer mode control

TxC0

Timer Start/Stop control in Modes 1 and 2 (Pro-
cessor Independent PWM and External Event
Counter), where 1 = Start, 0 = Stop

Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)

TxPNDA Timer Interrupt Pending Flag

TxENA

Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

TxPNDB Timer Interrupt Pending Flag

TxENB

Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

DS009425-15

FIGURE 10. Timer in Input Capture Mode

COP888CF

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Timers

(Continued)

The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:

Mode

TxC3

TxC2

TxC1

Description

Interrupt A

Source

Interrupt B

Source

Timer

Counts On

PWM: TxA Toggle

Autoreload RA

Autoreload RB

PWM: No TxA
Toggle

Autoreload RA

Autoreload RB

External Event
Counter

Timer
Underflow

Pos. TxB Edge

Pos. TxA
Edge

External Event
Counter

Timer
Underflow

Pos. TxB Edge

Pos. TxA
Edge

Captures:

Pos. TxA Edge

Pos. TxB Edge

TxA Pos. Edge

or Timer

TxB Pos. Edge

Underflow

Captures:

Pos. TxA

Neg. TxB

TxA Pos. Edge

Edge or Timer

Edge

TxB Neg. Edge

Underflow

Captures:

Neg. TxA

Neg. TxB

TxA Neg. Edge

Edge or Timer

Edge

TxB Neg. Edge

Underflow

Captures:

Neg. TxA

Neg. TxB

TxA Neg. Edge

Edge or Timer

Edge

TxB Neg. Edge

Underflow

Power Save Modes

The device offers the user two power save modes of opera-
tion: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board oscil-
lator circuitry and timer T0 are active but all other microcon-
troller activities are stopped. In either mode, all on-board
RAM, registers, I/O states, and timers (with the exception of
T0) are unaltered.

HALT MODE

The device is placed in the HALT mode by writing a "1" to the
HALT flag (G7 data bit). All microcontroller activities, includ-
ing the clock, timers, and A/D converter, are stopped. The
WatchDog logic is disabled during the HALT mode. However,
the clock monitor circuitry if enabled remains active and will
cause the WatchDog output pin (WDOUT) to go low. If the
HALT mode is used and the user does not want to activate
the WDOUT pin, the Clock Monitor should be disabled after
the device comes out of reset (resetting the Clock Monitor
control bit with the first write to the WDSVR register). In the
HALT mode, the power requirements of the device are mini-
mal and the applied voltage (V

) may be decreased to V

= 2.0V) without altering the state of the machine.

The device supports three different ways of exiting the HALT
mode. The first method of exiting the HALT mode is with the
Multi-Input Wakeup feature on the L port. The second
method is with a low to high transition on the CKO (G7) pin.
This method precludes the use of the crystal clock configura-
tion (since CKO becomes a dedicated output), and so may
be used with an RC clock configuration. The third method of
exiting the HALT mode is by pulling the RESET pin low.

Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic

resonators have a delayed start up time to reach full ampli-
tude and frequency stability. The IDLE timer is used to gen-
erate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution. In this case,
upon detecting a valid Wakeup signal, only the oscillator cir-
cuitry is enabled. The IDLE timer is loaded with a value of
256 and is clocked with the t

instruction cycle clock. The t

clock is derived by dividing the oscillator clock down by a fac-
tor of 10. The Schmitt trigger following the CKI inverter on
the chip ensures that the IDLE timer is clocked only when the
oscillator has a sufficiently large amplitude to meet the
Schmitt trigger specifications. This Schmitt trigger is not part
of the oscillator closed loop. The startup timeout from the
IDLE timer enables the clock signals to be routed to the rest
of the chip.

If an RC clock option is being used, the fixed delay is intro-
duced optionally. A control bit, CLKDLY, mapped as configu-
ration bit G7, controls whether the delay is to be introduced
or not. The delay is included if CLKDLY is set, and excluded
if CLKDLY is reset. The CLKDLY bit is cleared on reset.

The device has two mask options associated with the HALT
mode. The first mask option enables the HALT mode feature,
while the second mask option disables the HALT mode. With
the HALT mode enable mask option, the device will enter
and exit the HALT mode as described above. With the HALT
disable mask option, the device cannot be placed in the
HALT mode (writing a "1" to the HALT flag will have no ef-
fect).

The WatchDog detector circuit is inhibited during the HALT
mode. However, the clock monitor circuit if enabled remains
active during HALT mode in order to ensure a clock monitor
error if the device inadvertently enters the HALT mode as a
result of a runaway program or power glitch.

COP888CF

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Power Save Modes

(Continued)

IDLE MODE

The device is placed in the IDLE mode by writing a "1" to the
IDLE flag (G6 data bit). In this mode, all activity, except the
associated on-board oscillator circuitry, the WatchDog logic,
the clock monitor and the IDLE Timer T0, is stopped.

As with the HALT mode, the device can be returned to nor-
mal operation with a reset, or with a Multi-Input Wakeup from
the L Port. Alternately, the microcontroller resumes normal
operation from the IDLE mode when the thirteenth bit (repre-
senting 4.096 ms at internal clock frequency of 1 MHz,
t

= 1 µs) of the IDLE Timer toggles.

This toggle condition of the thirteenth bit of the IDLE Timer
T0 is latched into the T0PND pending flag.

The user has the option of being interrupted with a transition
on the thirteenth bit of the IDLE Timer T0. The interrupt can
be enabled or disabled via the T0EN control bit. Setting the
T0EN flag enables the interrupt and vice versa.

The user can enter the IDLE mode with the Timer T0 inter-
rupt enabled. In this case, when the T0PND bit gets set, the
device will first execute the Timer T0 interrupt service routine
and then return to the instruction following the "Enter Idle
Mode" instruction.

Alternatively, the user can enter the IDLE mode with the
IDLE Timer T0 interrupt disabled. In this case, the device will
resume normal operation with the instruction immediately
following the "Enter IDLE Mode" instruction.

Note: It is necessary to program two NOP instructions following both the set

HALT mode and set IDLE mode instructions. These NOP instructions
are necessary to allow clock resynchronization following the HALT or
IDLE modes.

Multi-Input Wakeup

The Multi-Input Wakeup feature is used to return (wakeup)
the device from either the HALT or IDLE modes. Alternately
Multi-Input Wakeup/Interrupt feature may also be used to
generate up to 8 edge selectable external interrupts.

Figure 11 shows the Multi-Input Wakeup logic.

The Multi-Input Wakeup feature utilizes the L Port. The user
selects which particular L port bit (or combination of L Port
bits) will cause the device to exit the HALT or IDLE modes.
The selection is done through the Reg: WKEN. The Reg:
WKEN is an 8-bit read/write register, which contains a con-
trol bit for every L port bit. Setting a particular WKEN bit en-
ables a Wakeup from the associated L port pin.

The user can select whether the trigger condition on the se-
lected L Port pin is going to be either a positive edge (low to
high transition) or a negative edge (high to low transition).
This selection is made via the Reg: WKEDG, which is an
8-bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a

negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a
pseudo Wakeup condition as a result of the edge change.
First, the associated WKEN bit should be reset, followed by
the edge select change in WKEDG. Next, the associated
WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.

An example may serve to clarify this procedure. Suppose we
wish to change the edge select from positive (low going high)
to negative (high going low) for L Port bit 5, where bit 5 has
previously been enabled for an input interrupt. The program
would be as follows:

RBIT 5, WKEN

; Disable MIWU

SBIT 5, WKEDG

; Change edge polarity

RBIT 5, WKPND

; Reset pending flag

SBIT 5, WKEN

; Enable MIWU

If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wakeup/Interrupt, a safety
procedure should also be followed to avoid inherited pseudo
wakeup conditions. After the selected L port bits have been
changed from output to input but before the associated
WKEN bits are enabled, the associated edge select bits in
WKEDG should be set or reset for the desired edge selects,
followed by the associated WKPND bits being cleared.

This same procedure should be used following reset, since
the L port inputs are left floating as a result of reset.

The occurrence of the selected trigger condition for
Multi-Input Wakeup is latched into a pending register called
WKPND. The respective bits of the WKPND register will be
set on the occurrence of the selected trigger edge on the cor-
responding Port L pin. The user has the responsibility of
clearing these pending flags. Since WKPND is a pending
register for the occurrence of selected wakeup conditions,
the device will not enter the HALT mode if any Wakeup bit is
both enabled and pending. Consequently, the user has the
responsibility of clearing the pending flags before attempting
to enter the HALT mode.

The WKEN, WKPND and WKEDG are all read/write regis-
ters, and are cleared at reset.

PORT L INTERRUPTS

Port L provides the user with an additional eight fully select-
able, edge sensitive interrupts which are all vectored into the
same service subroutine.

The interrupt from Port L shares logic with the wake up cir-
cuitry. The register WKEN allows interrupts from Port L to be
individually enabled or disabled. The register WKEDG speci-
fies the trigger condition to be either a positive or a negative
edge. Finally, the register WKPND latches in the pending
trigger conditions.

COP888CF

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Multi-Input Wakeup

(Continued)

The GIE (global interrupt enable) bit enables the interrupt
function. A control flag, LPEN, functions as a global interrupt
enable for Port L interrupts. Setting the LPEN flag will enable
interrupts and vice versa. A separate global pending flag is
not needed since the register WKPND is adequate.

Since Port L is also used for waking the device out of the
HALT or IDLE modes, the user can elect to exit the HALT or
IDLE modes either with or without the interrupt enabled. If he
elects to disable the interrupt, then the device will restart ex-
ecution from the instruction immediately following the in-
struction that placed the microcontroller in the HALT or IDLE
modes. In the other case, the device will first execute the in-
terrupt service routine and then revert to normal operation.

The Wakeup signal will not start the chip running immedi-
ately since crystal oscillators or ceramic resonators have a fi-
nite start up time. The IDLE Timer (T0) generates a fixed de-
lay to ensure that the oscillator has indeed stabilized before
allowing the device to execute instructions. In this case,
upon detecting a valid Wakeup signal, only the oscillator cir-
cuitry and the IDLE Timer T0 are enabled. The IDLE Timer is
loaded with a value of 256 and is clocked from the t

instruc-

tion cycle clock. The t

clock is derived by dividing down the

oscillator clock by a factor of 10. A Schmitt trigger following
the CKI on-chip inverter ensures that the IDLE timer is
clocked only when the oscillator has a sufficiently large am-
plitude to meet the Schmitt trigger specifications. This
Schmitt trigger is not part of the oscillator closed loop. The
startup timeout from the IDLE timer enables the clock signals
to be routed to the rest of the chip.

If the RC clock option is used, the fixed delay is under soft-
ware control. A control flag, CLKDLY, in the G7 configuration
bit allows the clock start up delay to be optionally inserted.
Setting CLKDLY flag high will cause clock start up delay to
be inserted and resetting it will exclude the clock start up de-
lay. The CLKDLY flag is cleared during reset, so the clock
start up delay is not present following reset with the RC clock
options.

A/D Converter

The device contains an 8-channel, multiplexed input, suc-
cessive approximation, A/D converter. Two dedicated pins,
V

REF

and AGND are provided for voltage reference.

OPERATING MODES

The A/D converter supports ratiometric measurements. It
supports both Single Ended and Differential modes of opera-
tion.

Four specific analog channel selection modes are sup-
ported. These are as follows:

Allow any specific channel to be selected at one time. The
A/D converter performs the specific conversion requested
and stops.

Allow any specific channel to be scanned continuously. In
other words, the user will specify the channel and the A/D
converter will keep on scanning it continuously. The user can
come in at any arbitrary time and immediately read the result
of the last conversion. The user does not have to wait for the
current conversion to be completed.

Allow any differential channel pair to be selected at one time.
The A/D converter performs the specific differential conver-
sion requested and stops.

Allow any differential channel pair to be scanned continu-
ously. In other words, the user will specify the differential
channel pair and the A/D converter will keep on scanning it
continuously. The user can come in at any arbitrary time and
immediately read the result of the last differential conversion.
The user does not have to wait for the current conversion to
be completed.

The A/D converter is supported by two memory mapped reg-
isters, the result register and the mode control register.
When the device is reset, the control register is cleared and
the A/D is powered down. The A/D result register has un-
known data following reset.

DS009425-16

FIGURE 11. Multi-Input Wake Up Logic

COP888CF

www.national.com

A/D Converter

(Continued)

A/D Control Register

A control register, Reg: ENAD, contains 3 bits for channel se-
lection, 3 bits for prescaler selection, and 2 bits for mode se-
lection. An A/D conversion is initiated by writing to the ENAD
control register. The result of the conversion is available to
the user from the A/D result register, Reg: ADRSLT.

Reg: ENAD

CHANNEL

SELECT

MODE

SELECT

PRESCALER

SELECT

Bits 7, 6, 5

Bits 4,3

Bits 2, 1, 0

CHANNEL SELECT

This 3-bit field selects one of eight channels to be the V

IN+

The mode selection determines the V

IN-

input.

Single Ended mode:

Bit 7

Bit 6

Bit 5

Channel No.

Differential mode:

Bit 7

Bit 6

Bit 5

Channel Pairs (+. -)

0, 1

1, 0

2, 3

3, 2

4, 5

5, 4

6, 7

7, 6

MODE SELECT

This 2-bit field is used to select the mode of operation (single
conversion, continuous conversions, differential, single
ended) as shown in the following table.

Bit 4

Bit 3

Mode

Single Ended mode, single conversion

Single Ended mode, continuous scan
of a single channel into the result
register

Differential mode, single conversion

Differential mode, continuous scan of
a channel pair into the result register

PRESCALER SELECT

This 3-bit field is used to select one of the seven prescaler
clocks for the A/D converter. The prescaler also allows the
A/D clock inhibit power saving mode to be selected. The fol-
lowing table shows the various prescaler options.

Bit 2

Bit 1

Bit 0

Clock Select

Inhibit A/D clock

Divide by 1

Divide by 2

Divide by 4

Divide by 6

Divide by 12

Divide by 8

Divide by 16

ADC Operation

The A/D converter interface works as follows. Writing to the
A/D control register ENAD initiates an A/D conversion unless
the prescaler value is set to 0, in which case the ADC clock
is stopped and the ADC is powered down. The conversion
sequence starts at the beginning of the write to ENAD opera-
tion powering up the ADC. At the first falling edge of the con-
verter clock following the write operation (not counting the
falling edge if it occurs at the same time as the write opera-
tion ends), the sample signal turns on for two clock cycles.
The ADC is selected in the middle of the sample period. If the
ADC is in single conversion mode, the conversion complete
signal from the ADC will generate a power down for the A/D
converter. If the ADC is in continuous mode, the conversion
complete signal will restart the conversion sequence by de-
selecting the ADC for one converter clock cycle before start-
ing the next sample. The ADC 8-bit result is loaded into the
A/D result register (ADRSLT) except during LOAD clock
high, which prevents transient data (resulting from the ADC
writing a new result over an old one) being read from
ADRSLT.

Inadvertant changes to the ENAD register during conversion
are prevented by the control logic of the A/D. Any attempt to
write any bit of the ENAD Register except ADBSY, while
ADBSY is a one, is ignored. ADBSY must be cleared either
by completion of an A/D conversion or by the user before the
prescaler, conversion mode or channel select values can be
changed. After stopping the current conversion, the user can
load different values for the prescaler, conversion mode or
channel select and start a new conversion in one instruction.

It is important for the user to realize that, when used in differ-
ential mode, only the positive input to the A/D converter is
sampled and held. The negative input is constantly con-
nected and should be held stable for the duration of the con-
version. Failure to maintain a stable negative input will result
in incorrect conversion.

PRESCALER

The A/D Converter (ADC) contains a prescaler option which
allows seven different clock selections. The A/D clock fre-
quency is equal to CKI divided by the prescaler value. Note
that the prescaler value must be chosen such that the A/D
clock falls within the specified range. The maximum A/D fre-
quency is 1.67 MHz. This equates to a 600 ns ADC clock
cycle.

The A/D converter takes 12 ADC clock cycles to complete a
conversion. Thus the minimum ADC conversion time for the
device is 7.2 µs when a prescaler of 6 has been selected.
These 12 ADC clock cycles necessary for a conversion con-

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A/D Converter

(Continued)

sist of 1 cycle at the beginning for reset, 2 cycles for sam-
pling, 8 cycles for converting, and 1 cycle for loading the re-
sult into the A/D result register (ADRSLT). This A/D result
register is a read-only register. The device cannot write into
ADRSLT.

The prescaler also allows an A/D clock inhibit option, which
saves power by powering down the A/D when it is not in use.

Note: The A/D converter is also powered down when the device is in either

the HALT or IDLE modes. If the ADC is running when the device enters
the HALT or IDLE modes, the ADC will power down during the HALT or
IDLE, and then will reinitialize the conversion when the device comes
out of the HALT or IDLE modes.

Analog Input and Source Resistance Considerations

Figure 12 shows the A/D pin model in single ended mode.
The differential mode has similiar A/D pin model. The leads
to the analog inputs should be kept as short as possible.
Both noise and digital clock coupling to an A/D input can
cause conversion errors. The clock lead should be kept
away from the analog input line to reduce coupling. The A/D
channel input pins do not have any internal output driver cir-
cuitry connected to them because this circuitry would load
the analog input signals due to output buffer leakage current.

Source impedances greater than 1 k

on the analog input

lines will adversely affect internal RC charging time during in-
put sampling. As shown in

Figure 12, the analog switch to

the DAC array is closed only during the 2 A/D cycle sample
time. Large source impedances on the analog inputs may re-
sult in the DAC array not being charged to the correct volt-
age levels, causing scale errors.

If large source resistance is necessary, the recommended
solution is to slow down the A/D clock speed in proportion to
the source resistance. The A/D converter may be operated
at the maximum speed for R

less than 1 k

. For R

greater

than 1 k

, A/D clock speed needs to be reduced. For ex-

ample, with R

= 2 k

, the A/D converter may be operated

at half the maximum speed. A/D converter clock speed may
be slowed down by either increasing the A/D prescaler
divide-by or decreasing the CKI clock frequency. The A/D
clock speed may be reduced to its minimum frequency of
100 kHz.

Interrupts

INTRODUCTION

Each device supports nine vectored interrupts. Interrupt
sources include Timer 0, Timer 1, Timer 2, Timer 3, Port L
Wakeup, Software Trap, MICROWIRE/PLUS, and External
Input.

All interrupts force a branch to location 00FF Hex in program
memory. The VIS instruction may be used to vector to the
appropriate service routine from location 00FF Hex.

The Software trap has the highest priority while the default
VIS has the lowest priority.

Each of the 9 maskable inputs has a fixed arbitration ranking
and vector.

Figure 13 shows the Interrupt Block Diagram.

DS009425-28

*The analog switch is closed only during the sample time.

FIGURE 12. A/D Pin Model (Single Ended Mode)

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Interrupts

(Continued)

MASKABLE INTERRUPTS

All interrupts other than the Software Trap are maskable.
Each maskable interrupt has an associated enable bit and
pending flag bit. The pending bit is set to 1 when the interrupt
condition occurs. The state of the interrupt enable bit, com-
bined with the GIE bit determines whether an active pending
flag actually triggers an interrupt. All of the maskable inter-
rupt pending and enable bits are contained in mapped con-
trol registers, and thus can be controlled by the software.

A maskable interrupt condition triggers an interrupt under the
following conditions:

The enable bit associated with that interrupt is set.

The GIE bit is set.

The device is not processing a non-maskable interrupt.
(If a non-maskable interrupt is being serviced, a
maskable interrupt must wait until that service routine is
completed.)

An interrupt is triggered only when all of these conditions are
met at the beginning of an instruction. If different maskable
interrupts meet these conditions simultaneously, the highest
priority interrupt will be serviced first, and the other pending
interrupts must wait.

Upon Reset, all pending bits, individual enable bits, and the
GIE bit are reset to zero. Thus, a maskable interrupt condi-
tion cannot trigger an interrupt until the program enables it by
setting both the GIE bit and the individual enable bit. When
enabling an interrupt, the user should consider whether or
not a previously activated (set) pending bit should be ac-
knowledged. If, at the time an interrupt is enabled, any pre-
vious occurrences of the interrupt should be ignored, the as-
sociated pending bit must be reset to zero prior to enabling
the interrupt. Otherwise, the interrupt may be simply en-
abled; if the pending bit is already set, it will immediately trig-
ger an interrupt. A maskable interrupt is active if its associ-
ated enable and pending bits are set.

An interrupt is an asychronous event which may occur be-
fore, during, or after an instruction cycle. Any interrupt which
occurs during the execution of an instruction is not acknowl-

edged until the start of the next normally executed instruction
is to be skipped, the skip is performed before the pending in-
terrupt is acknowledged.

At the start of interrupt acknowledgment, the following ac-
tions occur:

The GIE bit is automatically reset to zero, preventing any
subsequent maskable interrupt from interrupting the cur-
rent service routine. This feature prevents one maskable
interrupt from interrupting another one being serviced.

The address of the instruction about to be executed is
pushed onto the stack.

The program counter (PC) is loaded with 00FF Hex,
causing a jump to that program memory location.

The device requires seven instruction cycles to perform the
actions listed above.

If the user wishes to allow nested interrupts, the interrupts
service routine may set the GIE bit to 1 by writing to the PSW
register, and thus allow other maskable interrupts to interrupt
the current service routine. If nested interrupts are allowed,
caution must be exercised. The user must write the program
in such a way as to prevent stack overflow, loss of saved
context information, and other unwanted conditions.

The interrupt service routine stored at location 00FF Hex
should use the VIS instruction to determine the cause of the
interrupt, and jump to the interrupt handling routine corre-
sponding to the highest priority enabled and active interrupt.
Alternately, the user may choose to poll all interrupt pending
and enable bits to determine the source(s) of the interrupt. If
more than one interrupt is active, the user's program must
decide which interrupt to service.

Within a specific interrupt service routine, the associated
pending bit should be cleared. This is typically done as early
as possible in the service routine in order to avoid missing
the next occurrence of the same type of interrupt event.
Thus, if the same event occurs a second time, even while the
first occurrence is still being serviced, the second occur-
rence will be serviced immediately upon return from the cur-
rent interrupt routine.

An interrupt service routine typically ends with an RETI in-
struction. This instruction sets the GIE bit back to 1, pops the

DS009425-18

FIGURE 13. Interrupt Block Diagram

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Interrupts

(Continued)

address stored on the stack, and restores that address to the
program counter. Program execution then proceeds with the
next instruction that would have been executed had there
been no interrupt. If there are any valid interrupts pending,
the highest-priority interrupt is serviced immediately upon re-
turn from the previous interrupt.

VIS INSTRUCTION

The general interrupt service routine, which starts at address
00FF Hex, must be capable of handling all types of inter-
rupts. The VIS instruction, together with an interrupt vector
table, directs the device to the specific interrupt handling rou-
tine based on the cause of the interrupt.

VIS is a single-byte instruction, typically used at the very be-
ginning of the general interrupt service routine at address
00FF Hex, or shortly after that point, just after the code used
for context switching. The VIS instruction determines which
enabled and pending interrupt has the highest priority, and
causes an indirect jump to the address corresponding to that
interrupt source. The jump addresses (vectors) for all pos-
sible interrupts sources are stored in a vector table.

The vector table may be as long as 32 bytes (maximum of 16
vectors) and resides at the top of the 256-byte block contain-
ing the VIS instruction. However, if the VIS instruction is at
the very top of a 256-byte block (such as at 00FF Hex), the
vector table resides at the top of the next 256-byte block.
Thus, if the VIS instruction is located somewhere between
00FF and 01DF Hex (the usual case), the vector table is lo-
cated between addresses 01E0 and 01FF Hex. If the VIS in-
struction is located between 01FF and 02DF Hex, then the
vector table is located between addresses 02E0 and 02FF
Hex, and so on.

Each vector is 15 bits long and points to the beginning of a
specific interrupt service routine somewhere in the 32 kbyte
memory space. Each vector occupies two bytes of the vector
table, with the higher-order byte at the lower address. The
vectors are arranged in order of interrupt priority. The vector
of the maskable interrupt with the lowest rank is located to
0yE0 (higher-order byte) and 0yE1 (lower-order byte). The
next priority interrupt is located at 0yE2 and 0yE3, and so
forth in increasing rank. The Software Trap has the highest
rank and its vector is always located at 0yFE and 0yFF. The
number of interrupts which can become active defines the
size of the table.

Table 3 shows the types of interrupts, the interrupt arbitration
ranking, and the locations of the corresponding vectors in
the vector table.

The vector table should be filled by the user with the memory
locations of the specific interrupt service routines. For ex-
ample, if the Software Trap routine is located at 0310 Hex,
then the vector location 0yFE and -0yFF should contain the
data 03 and 10 Hex, respectively. When a Software Trap in-
terrupt occurs and the VIS instruction is executed, the pro-
gram jumps to the address specified in the vector table.

The interrupt sources in the vector table are listed in order of
rank, from highest to lowest priority. If two or more enabled
and pending interrupts are detected at the same time, the
one with the highest priority is serviced first. Upon return
from the interrupt service routine, the next highest-level
pending interrupt is serviced.

If the VIS instruction is executed, but no interrupts are en-
abled and pending, the lowest-priority interrupt vector is
used, and a jump is made to the corresponding address in
the vector table. This is an unusual occurrence, and may be
the result of an error. It can legitimately result from a change
in the enable bits or pending flags prior to the execution of
the VIS instruction, such as executing a single cycle instruc-
tion which clears an enable flag at the same time that the
pending flag is set. It can also result, however, from inadvert-
ent execution of the VIS command outside of the context of
an interrupt.

The default VIS interrupt vector can be useful for applica-
tions in which time critical interrupts can occur during the
servicing of another interrupt. Rather than restoring the pro-
gram context (A, B, X, etc.) and executing the RETI instruc-
tion, an interrupt service routine can be terminated by return-
ing to the VIS instruction. In this case, interrupts will be
serviced in turn until no further interrupts are pending and
the default VIS routine is started. After testing the GIE bit to
ensure that execution is not erroneous, the routine should
restore the program context and execute the RETI to return
to the interrupted program.

This technique can save up to fifty instruction cycles (t

), or

more, (50µs at 10 MHz oscillator) of latency for pending in-
terrupts with a penalty of fewer than ten instruction cycles if
no further interrupts are pending.

To ensure reliable operation, the user should always use the
VIS instruction to determine the source of an interrupt. Al-
though it is possible to poll the pending bits to detect the
source of an interrupt, this practice is not recommended. The
use of polling allows the standard arbitration ranking to be al-
tered, but the reliability of the interrupt system is compro-
mised. The polling routine must individually test the enable
and pending bits of each maskable interrupt. If a Software
Trap interrupt should occur, it will be serviced last, even
though it should have the highest priority. Under certain con-
ditions, a Software Trap could be triggered but not serviced,
resulting in an inadvertent "locking out" of all maskable inter-
rupts by the Software Trap pending flag. Problems such as
this can be avoided by using VIS instruction.

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Interrupts

(Continued)

TABLE 3. Interrupt Vector Table

Arbitration

Source

Description

Vector Address

Ranking

Hi-Low Byte

(1) Highest

Software

INTR Instruction

0yFE0yFF

Reserved

for Future Use

0yFC0yFD

(2)

External

Pin G0 Edge

0yFA0yFB

(3)

Timer T0

Underflow

0yF80yF9

(4)

Timer T1

T1A/Underflow

0yF60yF7

(5)

Timer T1

T1B

0yF40yF5

(6)

MICROWIRE/PLUS

BUSY Goes Low

0yF20yF3

Reserved

for Future Use

0yF00yF1

Reserved

for UART

0yEE0yEF

Reserved

for UART

0yEC0yED

(7)

Timer T2

T2A/Underflow

0yEA0yEB

(8)

Timer T2

T2B

0yE80yE9

Reserved

for Future Use

0yE60yE7

Reserved

for Future Use

0yE40yE5

(9)

Port L/Wakeup

Port L Edge

0yE20yE3

(10) Lowest

Default

VIS Instr. Execution without
Any Interrupts

0yE00yE1

Note 19: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last ad-
dress of a block. In this case, the table must be in the next block.

VIS Execution

When the VIS instruction is executed it activates the arbitra-
tion logic. The arbitration logic generates an even number
between E0 and FE (E0, E2, E4, E6 etc...) depending on
which active interrupt has the highest arbitration ranking at
the time of the 1st cycle of VIS is executed. For example, if
the software trap interrupt is active, FE is generated. If the
external interrupt is active and the software trap interrupt is
not, then FA is generated and so forth. If the only active inter-
rupt is software trap, than E0 is generated. This number re-
places the lower byte of the PC. The upper byte of the PC re-
mains unchanged. The new PC is therefore pointing to the

vector of the active interrupt with the highest arbitration rank-
ing. This vector is read from program memory and placed
into the PC which is now pointed to the 1st instruction of the
service routine of the active interrupt with the highest arbitra-
tion ranking.

Figure 14 illustrates the different steps performed by the VIS
instruction.

Figure 15 shows a flowchart for the VIS instruc-

tion.

The non-maskable interrupt pending flag is cleared by the
RPND (Reset Non-Maskable Pending Bit) instruction (under
certain conditions) and upon RESET.

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Interrupts

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NON-MASKABLE INTERRUPT

Pending Flag

There is a pending flag bit associated with the non-maskable
interrupt, called STPND. This pending flag is not memory-
mapped and cannot be accessed directly by the software.

The pending flag is reset to zero when a device Reset oc-
curs. When the non-maskable interrupt occurs, the associ-
ated pending bit is set to 1. The interrupt service routine
should contain an RPND instruction to reset the pending flag
to zero. The RPND instruction always resets the STPND
flag.

Software Trap

The Software Trap is a special kind of non-maskable inter-
rupt which occurs when the INTR instruction (used to ac-
knowledge interrupts) is fetched from program memory and
placed in the instruction register. This can happen in a vari-
ety of ways, usually because of an error condition. Some ex-
amples of causes are listed below.

If the program counter incorrectly points to a memory loca-
tion beyond the available program memory space, the non-
existent or unused memory location returns zeroes which is
interpreted as the INTR instruction.

If the stack is popped beyond the allowed limit (address 06F
Hex), a 7FFF will be loaded into the PC, if this last location in
program memory is unprogrammed or unavailable, a Soft-
ware Trap will be triggered.

A Software Trap can be triggered by a temporary hardware
condition such as a brownout or power supply glitch.

The Software Trap has the highest priority of all interrupts.
When a Software Trap occurs, the STPND bit is set. The GIE
bit is not affected and the pending bit (not accessible by the
user) is used to inhibit other interrupts and to direct the pro-
gram to the ST service routine with the VIS instruction. Noth-
ing can interrupt a Software Trap service routine except for
another Software Trap. The STPND can be reset only by the
RPND instruction or a chip Reset.

The Software Trap indicates an unusual or unknown error
condition. Generally, returning to normal execution at the
point where the Software Trap occurred cannot be done re-
liably. Therefore, the Software Trap service routine should
reinitialize the stack pointer and perform a recovery proce-
dure that restarts the software at some known point, similar
to a device Reset, but not necessarily performing all the
same functions as a device Reset. The routine must also ex-
ecute the RPND instruction to reset the STPND flag. Other-
wise, all other interrupts will be locked out. To the extent pos-
sible, the interrupt routine should record or indicate the
context of the device so that the cause of the Software Trap
can be determined.

If the user wishes to return to normal execution from the
point at which the Software Trap was triggered, the user
must first execute RPND, followed by RETSK rather than
RETI or RET. This is because the return address stored on
the stack is the address of the INTR instruction that triggered
the interrupt. The program must skip that instruction in order
to proceed with the next one. Otherwise, an infinite loop of
Software Traps and returns will occur.

Programming a return to normal execution requires careful
consideration. If the Software Trap routine is interrupted by
another Software Trap, the RPND instruction in the service
routine for the second Software Trap will reset the STPND

flag; upon return to the first Software Trap routine, the
STPND flag will have the wrong state. This will allow
maskable interrupts to be acknowledged during the servicing
of the first Software Trap. To avoid problems such as this, the
user program should contain the Software Trap routine to
perform a recovery procedure rather than a return to normal
execution.

Under normal conditions, the STPND flag is reset by a
RPND instruction in the Software Trap service routine. If a
programming error or hardware condition (brownout, power
supply glitch, etc.) sets the STPND flag without providing a
way for it to be cleared, all other interrupts will be locked out.
To alleviate this condition, the user can use extra RPND in-
structions in the main program and in the WATCHDOG ser-
vice routine (if present). There is no harm in executing extra
RPND instructions in these parts of the program.

PORT L INTERRUPTS

Port L provides the user with an additional eight fully select-
able, edge sensitive interrupts which are all vectored into the
same service subroutine.

The GIE (Global Interrupt Enable) bit enables the interrupt
function.

A control flag, LPEN, functions as a global interrupt enable
for Port L interrupts. Setting the LPEN flag will enable inter-
rupts and vice versa. A separate global pending flag is not
needed since the register WKPND is adequate.

INTERRUPT SUMMARY

The device uses the following types of interrupts, listed be-
low in order of priority:

The Software Trap non-maskable interrupt, triggered by
the INTR (00 opcode) instruction. The Software Trap is
acknowledged immediately. This interrupt service rou-
tine can be interrupted only by another Software Trap.
The Software Trap should end with two RPND instruc-
tions followed by a restart procedure.

Maskable interrupts, triggered by an on-chip peripheral
block or an external device connected to the device. Un-
der ordinary conditions, a maskable interrupt will not in-
terrupt any other interrupt routine in progress. A
maskable interrupt routine in progress can be inter-
rupted by the non-maskable interrupt request. A
maskable interrupt routine should end with an RETI in-
struction or, prior to restoring context, should return to
execute the VIS instruction. This is particularly useful
when exiting long interrupt service routiness if the time
between interrupts is short. In this case the RETI instruc-
tion would only be executed when the default VIS rou-
tine is reached.

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WATCHDOG

The device contains a WATCHDOG and clock monitor. The
WATCHDOG is designed to detect the user program getting
stuck in infinite loops resulting in loss of program control or
"runaway" programs. The Clock Monitor is used to detect the
absence of a clock or a very slow clock below a specified
rate on the CKI pin.

The WATCHDOG consists of two independent logic blocks:
WD UPPER and WD LOWER. WD UPPER establishes the
upper limit on the service window and WD LOWER defines
the lower limit of the service window.

Servicing the WATCHDOG consists of writing a specific
value to a WATCHDOG Service Register named WDSVR
which is memory mapped in the RAM. This value is com-
posed of three fields, consisting of a 2-bit Window Select, a
5-bit Key Data field, and the 1-bit Clock Monitor Select field.
Table 4 shows the WDSVR register.

TABLE 4. WATCHDOG Service Register (WDSVR)

Window

Select

Key Data

Clock

Monitor

The lower limit of the service window is fixed at 2048 instruc-
tion cycles. Bits 7 and 6 of the WDSVR register allow the
user to pick an upper limit of the service window.

Table 5 shows the four possible combinations of lower and
upper limits for the WATCHDOG service window. This flex-
ibility in choosing the WATCHDOG service window prevents
any undue burden on the user software.

TABLE 5. WATCHDOG Service Window Select

WDSVR

Clock

Service Window

Bit 7

Bit 6

Monitor

(Lower-Upper Limits)

20488k t

Cycles

204816k t

Cycles

204832k t

Cycles

204864k t

Cycles

Clock Monitor Disabled

Clock Monitor Enabled

Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the
5-bit Key Data field. The key data is fixed at 01100. Bit 0 of
the WDSVR Register is the Clock Monitor Select bit.

Clock Monitor

The Clock Monitor aboard the device can be selected or de-
selected under program control. The Clock Monitor is guar-
anteed not to reject the clock if the instruction cycle clock (1/
t

) is greater or equal to 10 kHz. This equates to a clock input

rate on CKI of greater or equal to 100 kHz.

WATCHDOG Operation

The WATCHDOG and Clock Monitor are disabled during re-
set. The device comes out of reset with the WATCHDOG
armed, the WATCHDOG Window Select (bits 6, 7 of the
WDSVR Register) set, and the Clock Monitor bit (bit 0 of the
WDSVR Register) enabled. Thus, a Clock Monitor error will
occur after coming out of reset, if the instruction cycle clock
frequency has not reached a minimum specified value, in-
cluding the case where the oscillator fails to start.

The WDSVR register can be written to only once after reset
and the key data (bits 5 through 1 of the WDSVR Register)
must match to be a valid write. This write to the WDSVR reg-
ister involves two irrevocable choices: (i) the selection of the
WATCHDOG service window (ii) enabling or disabling of the
Clock Monitor. Hence, the first write to WDSVR Register in-
volves selecting or deselecting the Clock Monitor, select the
WATCHDOG service window and match the WATCHDOG
key data. Subsequent writes to the WDSVR register will
compare the value being written by the user to the WATCH-
DOG service window value and the key data (bits 7 through
1) in the WDSVR Register.

Table 6 shows the sequence of

events that can occur.

The user must service the WATCHDOG at least once before
the upper limit of the service window expires. The WATCH-
DOG may not be serviced more than once in every lower
limit of the service window. The user may service the
WATCHDOG as many times as wished in the time period be-
tween the lower and upper limits of the service window. The
first write to the WDSVR Register is also counted as a
WATCHDOG service.

The WATCHDOG has an output pin associated with it. This
is the WDOUT pin, on pin 1 of the port G. WDOUT is active
low. The WDOUT pin is in the high impedance state in the in-
active state. Upon triggering the WATCHDOG, the logic will
pull the WDOUT (G1) pin low for an additional 16 t

32 t

cycles after the signal level on WDOUT pin goes below the
lower Schmitt trigger threshold. After this delay, the device
will stop forcing the WDOUT output low.

The WATCHDOG service window will restart when the WD-
OUT pin goes high. It is recommended that the user tie the
WDOUT pin back to V

through a resistor in order to pull

WDOUT high.

A WATCHDOG service while the WDOUT signal is active will
be ignored. The state of the WDOUT pin is not guaranteed
on reset, but if it powers up low then the WATCHDOG will
time out and WDOUT will enter high impedance state.

The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error. The Clock Monitor error will continue
until the clock frequency has reached the minimum specified
value, after which the G1 output will enter the high imped-
ance TRI-STATE mode following 16 t

32 t

clock cycles.

The Clock Monitor generates a continual Clock Monitor error
if the oscillator fails to start, or fails to reach the minimum
specified frequency. The specification for the Clock Monitor
is as follows:

1/t

10 kHz -- No clock rejection.

1/t

10 Hz -- Guaranteed clock rejection.

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WATCHDOG Operation

(Continued)

TABLE 6. WATCHDOG Service Actions

Key

Window

Clock

Action

Data

Monitor

Match

Valid Service: Restart Service Window

Don't Care

Mismatch

Don't Care

Error: Generate WATCHDOG Output

Mismatch

Don't Care

Error: Generate WATCHDOG Output

Don't Care

Mismatch

Error: Generate WATCHDOG Output

WATCHDOG AND CLOCK MONITOR SUMMARY

The following salient points regarding the WATCHDOG and
CLOCK MONITOR should be noted:

Both the WATCHDOG and Clock Monitor detector circuits
are inhibited during RESET.

Following RESET, the WATCHDOG and CLOCK MONI-
TOR are both enabled, with the WATCHDOG having the
maximum service window selected.

The WATCHDOG service window and Clock Monitor
enable/disable option can only be changed once, during
the initial WATCHDOG service following RESET.

The initial WATCHDOG service must match the key data
value in the WATCHDOG Service register WDSVR in or-
der to avoid a WATCHDOG error.

Subsequent WATCHDOG services must match all three
data fields in WDSVR in order to avoid WATCHDOG er-
rors.

The correct key data value cannot be read from the
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all 0's.

The WATCHDOG detector circuit is inhibited during both
the HALT and IDLE modes.

The Clock Monitor detector circuit is active during both
the HALT and IDLE modes. Consequently, the device in-
advertently entering the HALT mode will be detected as a
Clock Monitor error (provided that the Clock Monitor en-
able option has been selected by the program).

With the single-pin R/C oscillator mask option selected
and the CLKDLY bit reset, the WATCHDOG service win-
dow will resume following HALT mode from where it left
off before entering the HALT mode.

With the crystal oscillator mask option selected, or with
the single-pin R/C oscillator mask option selected and the
CLKDLY bit set, the WATCHDOG service window will be
set to its selected value from WDSVR following HALT.
Consequently, the WATCHDOG should not be serviced
for at least 2048 instruction cycles following HALT, but
must be serviced within the selected window to avoid a
WATCHDOG error.

The IDLE timer T0 is not initialized with RESET.

The user can sync in to the IDLE counter cycle with an
IDLE counter (T0) interrupt or by monitoring the T0PND
flag. The T0PND flag is set whenever the thirteenth bit of
the IDLE counter toggles (every 4096 instruction cycles).
The user is responsible for resetting the T0PND flag.

A hardware WATCHDOG service occurs just as the de-
vice exits the IDLE mode. Consequently, the WATCH-
DOG should not be serviced for at least 2048 instruction
cycles following IDLE, but must be serviced within the se-
lected window to avoid a WATCHDOG error.

Following RESET, the initial WATCHDOG service (where
the service window and the CLOCK MONITOR enable/
disable must be selected) may be programmed anywhere
within the maximum service window (65,536 instruction
cycles) initialized by RESET. Note that this initial WATCH-
DOG service may be programmed within the initial 2048
instruction cycles without causing a WATCHDOG error.

Detection of Illegal Conditions

The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs, etc.

Reading of undefined ROM gets zeros. The opcode for soft-
ware interrupt is zero. If the program fetches instructions
from undefined ROM, this will force a software interrupt, thus
signaling that an illegal condition has occurred.

The subroutine stack grows down for each call (jump to sub-
routine), interrupt, or PUSH, and grows up for each return or
POP. The stack pointer is initialized to RAM location 06F Hex
during reset. Consequently, if there are more returns than
calls, the stack pointer will point to addresses 070 and 071
Hex (which are undefined RAM). Undefined RAM from ad-
dresses 070 to 07F Hex is read as all 1's, which in turn will
cause the program to return to address 7FFF Hex. This is an
undefined ROM location and the instruction fetched (all 0's)
from this location will generate a software interrupt signaling
an illegal condition.

Thus, the chip can detect the following illegal conditions:

Executing from undefined ROM

Over "POP"ing the stack by having more returns than
calls.

When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before restart-
ing (this recovery program is probably similar to that follow-
ing reset, but might not contain the same program initializa-
tion procedures).

COP888CF

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MICROWIRE/PLUS

MICROWIRE/PLUS is a serial synchronous communications
interface. The MICROWIRE/PLUS capability enables the de-
vice to interface with any of National Semiconductor's MI-
CROWIRE peripherals (i.e. A/D converters, display drivers,
E

PROMs etc.) and with other microcontrollers which sup-

port the MICROWIRE interface. It consists of an 8-bit serial
shift register (SIO) with serial data input (SI), serial data out-
put (SO) and serial shift clock (SK).

Figure 16 shows a block

diagram of the MICROWIRE/PLUS logic.

The shift clock can be selected from either an internal source
or an external source. Operating the MICROWIRE/PLUS ar-
rangement with the internal clock source is called the Master
mode of operation. Similarly, operating the MICROWIRE/
PLUS arrangement with an external shift clock is called the
Slave mode of operation.

The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,
the MSEL bit in the CNTRL register is set to one. In the mas-
ter mode the SK clock rate is selected by the two bits, SL0
and SL1, in the CNTRL register.

Table 7 details the different

clock rates that may be selected.

TABLE 7. MICROWIRE/PLUS

Master Mode Clock Selection

SL1

SL0

2 x t

4 x t

8 x t

Where t

is the instruction cycle clock

MICROWIRE/PLUS OPERATION

Setting the BUSY bit in the PSW register causes the
MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave.

Figure 17 shows how

two COP888CF microcontrollers and several peripherals
may be interconnected using the MICROWIRE/PLUS ar-
rangements.

Warning:

The SIO register should only be loaded when the SK clock is
low. Loading the SIO register while the SK clock is high will
result in undefined data in the SIO register. SK clock is nor-
mally low when not shifting.

Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PLUS slave mode may cause the current SK
clock for the SIO shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is low.

MICROWIRE/PLUS Master Mode Operation

In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE
Master always initiates all data exchanges. The MSEL bit in
the CNTRL register must be set to enable the SO and SK
functions onto the G Port. The SO and SK pins must also be
selected as outputs by setting appropriate bits in the Port G
configuration register.

Table 8 summarizes the bit settings

required for Master mode of operation.

DS009425-20

FIGURE 16. MICROWIRE/PLUS Block Diagram

DS009425-21

FIGURE 17. MICROWIRE/PLUS Application

COP888CF

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MICROWIRE/PLUS

(Continued)

MICROWIRE/PLUS Slave Mode Operation

In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and re-
setting the appropriate bit in the Port G configuration regis-
ter.

Table 8 summarizes the settings required to enter the

Slave mode of operation.

TABLE 8. MICROWIRE/PLUS Mode Settings

This table assumes that the control flag MSEL is set.

G4 (SO)

G5 (SK)

Operation

Config. Bit

Fun.

Int.

MICROWIRE/PLUS

Master

TRI-

Int.

MICROWIRE/PLUS

STATE

Master

Ext.

MICROWIRE/PLUS

Slave

TRI-

Ext.

MICROWIRE/PLUS

STATE

Slave

The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by the
Master will be shifted properly. After eight clock pulses the
BUSY flag will be cleared and the sequence may be re-
peated.

Alternate SK Phase Operation

The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register. In
both the modes the SK is normally low. In the normal mode
data is shifted in on the rising edge of the SK clock and the
data is shifted out on the falling edge of the SK clock. The
SIO register is shifted on each falling edge of the SK clock in
the normal mode. In the alternate SK phase mode the SIO
register is shifted on the rising edge of the SK clock.

A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alter-
nate SK clock. The SKSEL is mapped into the G6 configura-
tion bit. The SKSEL flag will power up in the reset condition,
selecting the normal SK signal.

Memory Map

All RAM, ports and registers (except A and PC) are mapped
into data memory address space

Address

Contents

00 to 6F

On-Chip RAM bytes

70 to BF

Unused RAM Address Space

Timer T2 Lower Byte

Timer T2 Upper Byte

Timer T2 Autoload Register T2RA Lower Byte

Timer T2 Autoload Register T2RA Upper Byte

Timer T2 Autoload Register T2RB Lower Byte

Timer T2 Autoload Register T2RB Upper Byte

Timer T2 Control Register

WATCHDOG Service Register (Reg:WDSVR)

MIWU Edge Select Register (Reg:WKEDG)

MIWU Enable Register (Reg:WKEN)

MIWU Pending Register (Reg:WKPND)

A/D Converter Control Register (Reg:ENAD)

A/D Converter Result Register (Reg: ADRSLT)

CD to
CF

Reserved

Port L Data Register

Port L Configuration Register

Port L Input Pins (Read Only)

Reserved for Port L

Port G Data Register

Port G Configuration Register

Port G Input Pins (Read Only)

Port I Input Pins (Read Only)

Port C Data Register

Port C Configuration Register

Port C Input Pins (Read Only)

Reserved for Port C

Port D Data Register

DD to
DF

Reserved for Port D

E0 to E5

Reserved

Timer T1 Autoload Register T1RB Lower Byte

Timer T1 Autoload Register T1RB Upper Byte

ICNTRL Register

MICROWIRE Shift Register

Timer T1 Lower Byte

Timer T1 Upper Byte

Timer T1 Autoload Register T1RA Lower Byte

Timer T1 Autoload Register T1RA Upper Byte

CNTRL Control Register

PSW Register

F0 to FB

On-Chip RAM Mapped as Registers

X Register

SP Register

B Register

Reserved

Note: Reading memory locations 70-7F Hex will return all ones. Reading
other unused memory locations will return undefined data.

COP888CF

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Addressing Modes

The device has ten addressing modes, six for operand ad-
dressing and four for transfer of control.

OPERAND ADDRESSING MODES

Register Indirect

This is the "normal" addressing mode. The operand is the
data memory addressed by the B pointer or X pointer.

Register Indirect (with auto post increment or

decrement of pointer)

This addressing mode is used with the LD and X instruc-
tions. The operand is the data memory addressed by the B
pointer or X pointer. This is a register indirect mode that au-
tomatically post increments or decrements the B or X regis-
ter after executing the instruction.

Direct

The instruction contains an 8-bit address field that directly
points to the data memory for the operand.

Immediate

The instruction contains an 8-bit immediate field as the oper-
and.

Short Immediate

This addressing mode is used with the Load B Immediate in-
struction. The instruction contains a 4-bit immediate field as
the operand.

Indirect

This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.

TRANSFER OF CONTROL ADDRESSING MODES

Relative

This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new pro-
gram location. JP has a range from -31 to +32 to allow a
1-byte relative jump (JP + 1 is implemented by a NOP in-
struction). There are no "pages" when using JP, since all 15
bits of PC are used.

Absolute

This mode is used with the JMP and JSR instructions, with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any loca-
tion in the current 4k program memory segment.

Absolute Long

This mode is used with the JMPL and JSRL instructions, with
the instruction field of 15 bits replacing the entire 15 bits of
the program counter (PC). This allows jumping to any loca-
tion in the current 4k program memory space.

Indirect

This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits of
PC) for accessing a location in the program memory. The
contents of this program memory location serve as a partial
address (lower 8 bits of PC) for the jump to the next instruc-
tion.

Note: The VIS is a special case of the Indirect Transfer of Control addressing

mode, where the double byte vector associated with the interrupt is
transferred from adjacent addresses in the program memory into the
program counter (PC) in order to jump to the associated interrupt ser-
vice routine.

Instruction Set

Register and Symbol Definition

Registers

8-Bit Accumulator Register

8-Bit Address Register

8-Bit Stack Pointer Register

15-Bit Program Counter Register

Upper 7 Bits of PC

Lower 8 Bits of PC

1-Bit of PSW Register for Carry

1-Bit of PSW Register for Half Carry

GIE

1-Bit of PSW Register for Global Interrupt
Enable

Interrupt Vector Upper Byte

Interrupt Vector Lower Byte

Symbols

[B]

Memory Indirectly Addressed by B Register

[X]

Memory Indirectly Addressed by X Register

Direct Addressed Memory

Mem

Direct Addressed Memory or [B]

Meml

Direct Addressed Memory or [B] or Immediate
Data

Imm

8-Bit Immediate Data

Registers

Symbols

Reg

Bit

Bit Number (0 to 7)

Loaded with

Exchanged with

COP888CF

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Instruction Set

(Continued)

INSTRUCTION SET

ADD

A,Meml

ADD

A + Meml

ADC

A,Meml

ADD with Carry

A + Meml + C, C

Carry

Half Carry

SUBC

A,Meml

Subtract with Carry

A Meml + C, C

Carry

Half Carry

AND

A,Meml

Logical AND

A and Meml

ANDSZ

A,Imm

Logical AND Immed., Skip if Zero

Skip next if (A and Imm) = 0

A,Meml

Logical OR

A or Meml

XOR

A,Meml

Logical EXclusive OR

A xor Meml

IFEQ

MD,Imm

IF EQual

Compare MD and Imm, Do next if MD = Imm

IFEQ

A,Meml

IF EQual

Compare A and Meml, Do next if A = Meml

IFNE

A,Meml

IF Not Equal

Compare A and Meml, Do next if A

Meml

IFGT

A,Meml

IF Greater Than

Compare A and Meml, Do next if A

Meml

IFBNE

If B Not Equal

Do next if lower 4 bits of B

Imm

DRSZ

Reg

Decrement Reg., Skip if Zero

Reg

Reg- 1, Skip if Reg = 0

SBIT

#,Mem

Set BIT

1 to bit, Mem (bit = 0 to 7 immediate)

RBIT

#,Mem

Reset BIT

0 to bit, Mem

IFBIT

#,Mem

IF BIT

If bit in A or Mem is true do next instruction

RPND

Reset PeNDing Flag

Reset Software Interrupt Pending Flag

A,Mem

EXchange A with Memory

Mem

A,[X]

EXchange A with Memory [X]

[X]

A,Meml

LoaD A with Memory

Meml

A,[X]

LoaD A with Memory [X]

[X]

B,Imm

LoaD B with Immed.

Imm

Mem,Imm

LoaD Memory Immed

Mem

Imm

Reg,Imm

LoaD Register Memory Immed.

Reg

Imm

A, [B

]

EXchange A with Memory [B]

[B], (B

A, [X

]

EXchange A with Memory [X]

[X], (X

A, [B

]

LoaD A with Memory [B]

[B], (B

A, [X

]

LoaD A with Memory [X]

[X], (X

],Imm

LoaD Memory [B] Immed.

[B]

Imm, (B

CLR

CLeaR A

INC

INCrement A

A + 1

DEC

DECrementA

A - 1

LAID

Load A InDirect from ROM

ROM (PU,A)

DCOR

Decimal CORrect A

BCD correction of A (follows ADC, SUBC)

RRC

Rotate A Right thru C

...

RLC

Rotate A Left thru C

...

SWAP

SWAP nibbles of A

A7...A4

A3...A0

Set C

1, HC

Reset C

0, HC

IFC

IF C

IF C is true, do next instruction

IFNC

IF Not C

If C is not true, do next instruction

POP

POP the stack into A

SP + 1, A

[SP]

PUSH

PUSH A onto the stack

[SP]

A, SP

SP - 1

VIS

Vector to Interrupt Service Routine

[VU], PL

[VL]

JMPL

Addr.

Jump absolute Long

ii (ii = 15 bits, 0 to 32k)

JMP

Addr.

Jump absolute

PC9...0

i (i = 12 bits)

Disp.

Jump relative short

PC + r (r is -31 to +32, except 1)

COP888CF

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Instruction Execution Time

Most instructions are single byte (with immediate addressing
mode instructions taking two bytes).

Most single byte instructions take one cycle time to execute.

Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped
instruction opcode.

See the BYTES and CYCLES per INSTRUCTION table for
details.

Bytes and Cycles per Instruction

The following table shows the number of bytes and cycles for
each instruction in the format of byte/cycle.

Arithmetic and Logic Instructions

[B]

Direct

Immed.

ADD

1/1

3/4

2/2

ADC

1/1

3/4

2/2

SUBC

1/1

3/4

2/2

AND

1/1

3/4

2/2

1/1

3/4

2/2

XOR

1/1

3/4

2/2

IFEQ

1/1

3/4

2/2

IFNE

1/1

3/4

2/2

IFGT

1/1

3/4

2/2

IFBNE

1/1

DRSZ

1/3

SBIT

1/1

3/4

RBIT

1/1

3/4

IFBIT

1/1

3/4

RPND

1/1

Instructions Using A & C

CLRA

1/1

INCA

1/1

DECA

1/1

LAID

1/3

DCOR

1/1

RRCA

1/1

RLCA

1/1

SWAPA

1/1

IFC

1/1

IFNC

1/1

PUSHA

1/3

POPA

1/3

ANDSZ

2/2

Transfer of Control Instructions

JMPL

3/4

JMP

2/3

1/3

JSRL

3/5

JSR

2/5

JID

1/3

VIS

1/5

RET

1/5

RETSK

1/5

RETI

1/5

INTR

1/7

NOP

1/1

Memory Transfer Instructions

Register

Direct

Immed.

Register Indirect

Indirect

Auto Incr. & Decr.

[B]

[X]

[B+, B-]

[X+, X-]

X A, (Note 20)

1/1

1/3

2/3

1/2

1/3

LD A, (Note 20)

1/1

1/3

2/3

2/2

1/2

1/3

LD B, Imm

1/1

(IF B

16)

LD B, Imm

2/2

(IF B

15)

LD Mem, Imm

2/2

3/3

2/2

LD Reg, Imm

2/3

IFEQ MD, Imm

3/3

Note 20: Memory location addressed by B or X or directly.

COP888CF

www.national.com

Instruction Execution Time

(Continued)

OPCODE

TABLE

Upper

Nibble

876

LowerNibble

JP-15

JP-31

0F0,

DRSZ

0F0

RRCA

ADC

A,#i

ADC

A,[B]

IFBIT

0,[B]

ANDSZ

B,#0F

IFBNE

JSR

x000

x0FF

JMP

x000

x0FF

JP+17

INTR

JP-14

JP-30

0F1,

DRSZ

0F1

SUBC

A,[B]

IFBIT

1,[B]

B,#0E

IFBNE

JSR

x100

x1FF

JMP

x100

x1FF

JP+18

JP+2

JP-13

JP-29

0F2,

DRSZ

0F2

A,[X+]

A,[B+]

IFEQ

A,#i

IFEQ

A,[B]

IFBIT

2,[B]

B,#0D

IFBNE

JSR

x200

x2FF

JMP

x200

x2FF

JP+19

JP+3

JP-12

JP-28

0F3,

DRSZ

0F3

A,[X-]

A,[B-]

IFGT

A,#i

IFGT

A,[B]

IFBIT

3,[B]

B,#0C

IFBNE

JSR

x300

x3FF

JMP

x300

x3FF

JP+20

JP+4

JP-11

JP-27

0F4,

DRSZ

0F4

VIS

LAID

ADD

A,#i

ADD

A,[B]

IFBIT

4,[B]

CLRA

B,#0B

IFBNE

JSR

x400

x4FF

JMP

x400

x4FF

JP+21

JP+5

JP-10

JP-26

0F5,

DRSZ

0F5

RPND

JID

AND

A,#i

AND

A,[B]

IFBIT

5,[B]

SWAPA

B,#0A

IFBNE

JSR

x500

x5FF

JMP

x500

x5FF

JP+22

JP+6

JP-9

JP-25

0F6,

DRSZ

0F6

A,[X]

A,[B]

XOR

A,#i

XOR

A,[B]

IFBIT

6,[B]

DCORA

B,#09

IFBNE

JSR

x600

x6FF

JMP

x600

x6FF

JP+23

JP+7

JP-8

JP-24

0F7,

DRSZ

0F7

A,#i

A,[B]

IFBIT

7,[B]

PUSHA

B,#08

IFBNE

JSR

x700

x7FF

JMP

x700

x7FF

JP+24

JP+8

JP-7

JP-23

0F8,

DRSZ

0F8

NOP

RLCA

A,#i

IFC

SBIT

0,[B]

RBIT

0,[B]

B,#07

IFBNE

JSR

x800

x8FF

JMP

x800

x8FF

JP+25

JP+9

JP-6

JP-22

0F9,

DRSZ

0F9

IFNE

A,[B]

IFEQ

Md,#i

IFNE

A,#i

IFNC

SBIT

1,[B]

RBIT

1,[B]

B,#06

IFBNE

JSR

x900

x9FF

JMP

x900

x9FF

JP+26

JP+10

JP-5

JP-21

0FA,

DRSZ

0FA

A,[X+]

A,[B+]

[B+],#i

INCA

SBIT

2,[B]

RBIT

2,[B]

B,#05

IFBNE

JSR

xA00

xAFF

JMP

xA00

xAFF

JP+27

JP+11

JP-4

JP-20

0FB,

DRSZ

0FB

A,[X-]

A,[B-]

[B-],#i

DECA

SBIT

3,[B]

RBIT

3,[B]

B,#04

IFBNE

JSR

xB00

xBFF

JMP

xB00

xBFF

JP+28

JP+12

JP-3

JP-19

0FC,

DRSZ

0FC

Md,#i

JMPL

A,Md

POPA

SBIT

4,[B]

RBIT

4,[B]

B,#03

IFBNE

JSR

xC00

xCFF

JMP

xC00

xCFF

JP+29

JP+13

JP-2

JP-18

0FD,

DRSZ

0FD

DIR

JSRL

A,Md

RETSK

SBIT

5,[B]

RBIT

5,[B]

B,#02

IFBNE

JSR

xD00

xDFF

JMP

xD00

xDFF

JP+30

JP+14

JP-1

JP-17

0FE,

DRSZ

0FE

A,[X]

A,[B]

[B],#i

RET

SBIT

6,[B]

RBIT

6,[B]

B,#01

IFBNE

JSR

xE00

xEFF

JMP

xE00

xEFF

JP+31

JP+15

JP-0

JP-16

0FF,

DRSZ

0FF

B,#i

RETI

SBIT

7,[B]

RBIT

7,[B]

B,#00

IFBNE

JSR

xF00

xFFF

JMP

xF00

xFFF

JP+32

JP+16

Where,

i
s

the

immediate

data

directly

addressed

memory

location

i
s

unused

opcode

The

opcode

Hex

also

the

opcode

for

IFBIT

#i,A

COP888CF

www.national.com

Mask Options

The mask programmable options are shown below. The op-
tions are programmed at the same time as the ROM pattern
submission.

OPTION 1: CLOCK CONFIGURATION

= 1

Crystal Oscillator (CKI/10)

G7 (CKO) is clock generator

output to crystal/resonator

CKI is the clock input

= 2

Single-pin RC controlled

oscillator (CKI/10)

G7 is available as a HALT

restart and/or general

purpose input

OPTION 2: HALT

= 1

Enable HALT mode

= 2

Disable HALT mode

OPTION 3: BONDING

= 1

44-Pin PLCC

= 2

40-Pin DIP

= 3

N/A

= 4

28-Pin DIP

= 5

28-Pin SO

Development Tools Support

OVERVIEW

National is engaged with an international community of inde-
pendent 3rd party vendors who provide hardware and soft-
ware development tool support. Through National's interac-
tion and guidance, these tools cooperate to form a choice of
solutions that fits each developer's needs.

This section provides a summary of the tool and develop-
ment kits currently available. Up-to-date information, selec-
tion guides, free tools, demos, updates, and purchase infor-
mation

can

obtained

our

web

site

at:

www.national.com/cop8.

SUMMARY OF TOOLS

COP8 Evaluation Tools

COP8NSEVAL: Free Software Evaluation package for
Windows. A fully integrated evaluation environment for
COP8, including versions of WCOP8 IDE (Integrated De-
velopment Environment), COP8-NSASM, COP8-MLSIM,
COP8C, DriveWay

COP8, Manuals, and other COP8

information.

COP8MLSIM: Free Instruction Level Simulator tool for
Windows. For testing and debugging software instruc-
tions only (No I/O or interrupt support).

COP8EPU: Very Low cost COP8 Evaluation & Pro-
gramming

Unit.

Windows

based

evaluation

and

hardware-simulation tool, with COP8 device programmer
and erasable samples. Includes COP8-NSDEV, Drive-
way COP8 Demo, MetaLink Debugger, I/O cables and
power supply.

COP8EVAL-ICUxx: Very Low cost evaluation and de-
sign test board for COP8ACC and COP8SGx Families,
from ICU. Real-time environment with add-on A/D, D/A,
and EEPROM. Includes software routines and reference
designs.

Manuals, Applications Notes, Literature: Available free
from our web site at: www.national.com/cop8.

COP8 Integrated Software/Hardware Design Develop-
ment Kits

COP8-EPU: Very Low cost Evaluation & Programming
Unit. Windows based development and hardware-
simulation tool for COPSx/xG families, with COP8 device
programmer and samples. Includes COP8-NSDEV,
Driveway COP8 Demo, MetaLink Debugger, cables and
power supply.

COP8-DM: Moderate cost Debug Module from MetaLink.
A Windows based, real-time in-circuit emulation tool with
COP8 device programmer. Includes COP8-NSDEV,
DriveWay COP8 Demo, MetaLink Debugger, power sup-
ply, emulation cables and adapters.

COP8 Development Languages and Environments

COP8-NSASM: Free COP8 Assembler v5 for Win32.
Macro assembler, linker, and librarian for COP8 software
development. Supports all COP8 devices. (DOS/Win16
v4.10.2 available with limited support). (Compatible with
WCOP8 IDE, COP8C, and DriveWay COP8).

COP8-NSDEV: Very low cost Software Development
Package for Windows. An integrated development envi-
ronment for COP8, including WCOP8 IDE, COP8-
NSASM, COP8-MLSIM.

COP8C: Moderately priced C Cross-Compiler and Code
Development System from Byte Craft (no code limit). In-
cludes BCLIDE (Byte Craft Limited Integrated Develop-
ment Environment) for Win32, editor, optimizing C Cross-
Compiler, macro cross assembler, BC-Linker, and
MetaLink tools support. (DOS/SUN versions available;
Compiler is installable under WCOP8 IDE; Compatible
with DriveWay COP8).

EWCOP8-KS: Very Low cost ANSI C-Compiler and Em-
bedded

Workbench

from

IAR

(Kickstart

version:

COP8Sx/Fx only with 2k code limit; No FP). A fully inte-
grated Win32 IDE, ANSI C-Compiler, macro assembler,
editor, linker, Liberian, C-Spy simulator/debugger, PLUS
MetaLink EPU/DM emulator support.

EWCOP8-AS: Moderately priced COP8 Assembler and
Embedded Workbench from IAR (no code limit). A fully in-
tegrated Win32 IDE, macro assembler, editor, linker, li-
brarian, and C-Spy high-level simulator/debugger with
I/O and interrupts support. (Upgradeable with optional
C-Compiler and/or MetaLink Debugger/Emulator sup-
port).

EWCOP8-BL: Moderately priced ANSI C-Compiler and
Embedded Workbench from IAR (Baseline version: All
COP8 devices; 4k code limit; no FP). A fully integrated
Win32 IDE, ANSI C-Compiler, macro assembler, editor,
linker, librarian, and C-Spy high-level simulator/debugger.
(Upgradeable; CWCOP8-M MetaLink tools interface sup-
port optional).

EWCOP8: Full featured ANSI C-Compiler and Embed-
ded Workbench for Windows from IAR (no code limit). A
fully integrated Win32 IDE, ANSI C-Compiler, macro as-
sembler, editor, linker, librarian, and C-Spy high-level
simulator/debugger. (CWCOP8-M MetaLink tools inter-
face support optional).

EWCOP8-M: Full featured ANSI C-Compiler and Embed-
ded Workbench for Windows from IAR (no code limit). A
fully integrated Win32 IDE, ANSI C-Compiler, macro as-
sembler,

editor,

linker,

librarian,

C-Spy

high-level

simulator/debugger, PLUS MetaLink debugger/hardware
interface (CWCOP8-M).

COP888CF

www.national.com

Development Tools Support

(Continued)

COP8 Productivity Enhancement Tools

WCOP8 IDE: Very Low cost IDE (Integrated Develop-
ment Environment) from KKD. Supports COP8C, COP8-
NSASM, COP8-MLSIM, DriveWay COP8, and MetaLink
debugger under a common Windows Project Manage-
ment environment. Code development, debug, and emu-
lation tools can be launched from the project window
framework.

DriveWay-COP8: Low cost COP8 Peripherals Code
Generation tool from Aisys Corporation. Automatically
generates tested and documented C or Assembly source
code modules containing I/O drivers and interrupt han-
dlers for each on-chip peripheral. Application specific
code can be inserted for customization using the inte-
grated editor. (Compatible with COP8-NSASM, COP8C,
and WCOP8 IDE.)

COP8-UTILS: Free set of COP8 assembly code ex-
amples, device drivers, and utilities to speed up code de-
velopment.

COP8-MLSIM: Free Instruction Level Simulator tool for
Windows. For testing and debugging software instruc-
tions only (No I/O or interrupt support).

COP8 Real-Time Emulation Tools

COP8-DM: MetaLink Debug Module. A moderately
priced real-time in-circuit emulation tool, with COP8 de-
vice programmer. Includes COP8-NSDEV, DriveWay
COP8 Demo, MetaLink Debugger, power supply, emula-
tion cables and adapters.

IM-COP8: MetaLink iceMASTER

. A full featured, real-

time in-circuit emulator for COP8 devices. Includes Met-
aLink Windows Debugger, and power supply. Package-
specific probes and surface mount adaptors are ordered
separately.

COP8 Device Programmer Support

MetaLink's EPU and Debug Module include development
device programming capability for COP8 devices.

Third-party programmers and automatic handling equip-
ment cover needs from engineering prototype and pilot
production, to full production environments.

Factory programming available for high-volume require-
ments.

TOOLS ORDERING NUMBERS FOR THE COP888CF FAMILY DEVICES

Vendor

Tools

Order Number

Cost

Notes

National

COP8-NSEVAL

Free

Web site download

COP8-NSASM

Free

Included in EPU and DM. Web site download

COP8-MLSIM

Free

Included in EPU and DM. Web site download

COP8-NSDEV

Included in EPU and DM. Order CD from website

COP8-EPU

Not available for this device

COP8-DM

Contact MetaLink

Development
Devices

COP87L84CF
COP87L88CF

16k OTP devices. No windowed devices

IM-COP8

Contact MetaLink

MetaLink COP8-EPU

Not available for this device

COP8-DM

DM4-COP8-888CF (10
MHz), plus PS-10, plus
DM-COP8/xxx (ie. 28D)

Included p/s (PS-10), target cable of choice (DIP or
PLCC; i.e. DM-COP8/28D), 16/20/28/40 DIP/SO and
44 PLCC programming sockets. Add target adapter (if
needed)

DM Target
Adapters

MHW-CONV39

DM target converters for 28SO

IM-COP8

IM-COP8-AD-464 (-220)
(10 MHz maximum)

Base unit 10 MHz; -220 = 220V; add probe card
(required) and target adapter (if needed); included
software and manuals

IM Probe Card

PC-884CF28DW-AD-10

10 MHz 28 DIP probe card; 2.5V to 6.0V

PC-8884CF40DW-AD-10

10 MHz 40 DIP probe card; 2.5V to 6.0V

PC-8884CF44PW-AD-10

10 MHz 44 PLCC probe card; 2.5V to 6.0V

IM Probe Target
Adapter

MHW-SOIC28

28 pin SOIC adapter for probe card

ICU

COP8-EVAL

Not available for this device

KKD

WCOP8-IDE

Included in EPU and DM

IAR

EWCOP8-xx

See summary above

L - H

Included all software and manuals

Byte

Craft

COP8C

Included all software and manuals

Aisys

DriveWay COP8

Included all software and manuals

COP888CF

www.national.com

Development Tools Support

(Continued)

OTP Programmers

Contact vendors

L - H

For approved programmer listings and vendor
information, go to our OTP support page at:
www.national.com/cop8

Cost: Free; VL =

$100; L = $100 - $300; M = $300 - $1k; H = $1k - $3k; VH = $3k - $5k

WHERE TO GET TOOLS

Tools are ordered directly from the following vendors. Please go to the vendor's web site for current listings of distributors.

Vendor

Home Office

Electronic Sites

Other Main Offices

Aisys

U.S.A.: Santa Clara, CA

www.aisysinc.com

Distributors

1-408-327-8820

info

aisysinc.com

fax: 1-408-327-8830

Byte Craft

U.S.A.

www.bytecraft.com

Distributors

1-519-888-6911

info

bytecraft.com

fax: 1-519-746-6751

IAR

Sweden: Uppsala

www.iar.se

U.S.A.: San Francisco

+46 18 16 78 00

info

iar.se

1-415-765-5500

fax: +46 18 16 78 38

info

iar.com

fax: 1-415-765-5503

info

iarsys.co.uk

U.K.: London

info

iar.de

+44 171 924 33 34

fax: +44 171 924 53 41

Germany: Munich

+49 89 470 6022

fax: +49 89 470 956

ICU

Sweden: Polygonvaegen

www.icu.se

Switzeland: Hoehe

+46 8 630 11 20

support

icu.se

+41 34 497 28 20

fax: +46 8 630 11 70

support

icu.ch

fax: +41 34 497 28 21

KKD

Denmark:

www.kkd.dk

MetaLink

U.S.A.: Chandler, AZ

www.metaice.com

Germany: Kirchseeon

1-800-638-2423

sales

metaice.com

80-91-5696-0

fax: 1-602-926-1198

support

metaice.com

fax: 80-91-2386

bbs: 1-602-962-0013

islanger

metalink.de

www.metalink.de

Distributors Worldwide

National

U.S.A.: Santa Clara, CA

www.national.com/cop8

Europe: +49 (0) 180 530 8585

1-800-272-9959

support

nsc.com

fax: +49 (0) 180 530 8586

fax: 1-800-737-7018

europe.support

nsc.com

Distributors Worldwide

The following companies have approved COP8 program-
mers in a variety of configurations. Contact your local office
or distributor. You can link to their web sites and get the lat-
est listing of approved programmers from National's COP8
OTP Support page at: www.national.com/cop8.

Advantech; Advin; BP Microsystems; Data I/O; Hi-Lo Sys-
tems; ICE Technology; Lloyd Research; Logical Devices;
MQP; Needhams; Phyton; SMS; Stag Programmers; Sys-
tem General; Tribal Microsystems; Xeltek.

Customer Support

Complete product information and technical support is avail-
able from National's customer response centers, and from
our on-line COP8 customer support sites.

COP888CF

www.national.com

Notes

LIFE SUPPORT POLICY

NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.

National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com

National Semiconductor
Europe

Fax: +49 (0) 180-530 85 86

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208
English

Tel: +44 (0) 870 24 0 2171

Français Tel: +33 (0) 1 41 91 8790

National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: ap.support@nsc.com

National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507

www.national.com

COP888CF

8-Bit

CMOS

ROM

Based

Microcontrollers

with

Memory

and

A/D

Converter

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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